| From 03e737c8ed9ca6ea6aa33c165b13bd49991a8e4f Mon Sep 17 00:00:00 2001 |
| From: Takeshi Kihara <takeshi.kihara.df@renesas.com> |
| Date: Fri, 4 Nov 2016 14:58:07 +0100 |
| Subject: [PATCH 195/299] clk: renesas: r8a7795: Fix HDMI parent clock |
| |
| Correct HDMI parent clock so that the rate of the |
| HDMI clock is 1/4 rather than 1/2 of the rate of PLL1 |
| as per the v0.52 (Jun, 15) manual. |
| |
| Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| (cherry picked from commit 0a30284b9fe19780d4587e74578e460469d88706) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/clk/renesas/r8a7795-cpg-mssr.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c |
| +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c |
| @@ -98,7 +98,7 @@ static const struct cpg_core_clk r8a7795 |
| DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), |
| |
| DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), |
| - DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250), |
| + DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), |
| DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), |
| DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), |
| |
