| From 5dc43314ce4663a705a0a91a3ad6e9aba3457de1 Mon Sep 17 00:00:00 2001 |
| From: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> |
| Date: Mon, 21 Nov 2016 22:26:43 +0000 |
| Subject: [PATCH 037/103] fpga zynq: Add missing \n to messages |
| |
| Function dev_err doesn't add a newline at the end of the string. This will |
| lead to a hard to read kernel log. |
| |
| Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> |
| Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com> |
| Reviewed-by: Matthias Brugger <mbrugger@suse.com> |
| Acked-by: Alan Tull <atull@opensource.altera.com> |
| --- |
| drivers/fpga/zynq-fpga.c | 22 +++++++++++----------- |
| 1 file changed, 11 insertions(+), 11 deletions(-) |
| |
| --- a/drivers/fpga/zynq-fpga.c |
| +++ b/drivers/fpga/zynq-fpga.c |
| @@ -218,7 +218,7 @@ static int zynq_fpga_ops_write_init(stru |
| INIT_POLL_DELAY, |
| INIT_POLL_TIMEOUT); |
| if (err) { |
| - dev_err(priv->dev, "Timeout waiting for PCFG_INIT"); |
| + dev_err(priv->dev, "Timeout waiting for PCFG_INIT\n"); |
| goto out_err; |
| } |
| |
| @@ -232,7 +232,7 @@ static int zynq_fpga_ops_write_init(stru |
| INIT_POLL_DELAY, |
| INIT_POLL_TIMEOUT); |
| if (err) { |
| - dev_err(priv->dev, "Timeout waiting for !PCFG_INIT"); |
| + dev_err(priv->dev, "Timeout waiting for !PCFG_INIT\n"); |
| goto out_err; |
| } |
| |
| @@ -246,7 +246,7 @@ static int zynq_fpga_ops_write_init(stru |
| INIT_POLL_DELAY, |
| INIT_POLL_TIMEOUT); |
| if (err) { |
| - dev_err(priv->dev, "Timeout waiting for PCFG_INIT"); |
| + dev_err(priv->dev, "Timeout waiting for PCFG_INIT\n"); |
| goto out_err; |
| } |
| } |
| @@ -263,7 +263,7 @@ static int zynq_fpga_ops_write_init(stru |
| /* check that we have room in the command queue */ |
| status = zynq_fpga_read(priv, STATUS_OFFSET); |
| if (status & STATUS_DMA_Q_F) { |
| - dev_err(priv->dev, "DMA command queue full"); |
| + dev_err(priv->dev, "DMA command queue full\n"); |
| err = -EBUSY; |
| goto out_err; |
| } |
| @@ -332,7 +332,7 @@ static int zynq_fpga_ops_write(struct fp |
| zynq_fpga_write(priv, INT_STS_OFFSET, intr_status); |
| |
| if (!((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) { |
| - dev_err(priv->dev, "Error configuring FPGA"); |
| + dev_err(priv->dev, "Error configuring FPGA\n"); |
| err = -EFAULT; |
| } |
| |
| @@ -428,7 +428,7 @@ static int zynq_fpga_probe(struct platfo |
| priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node, |
| "syscon"); |
| if (IS_ERR(priv->slcr)) { |
| - dev_err(dev, "unable to get zynq-slcr regmap"); |
| + dev_err(dev, "unable to get zynq-slcr regmap\n"); |
| return PTR_ERR(priv->slcr); |
| } |
| |
| @@ -436,26 +436,26 @@ static int zynq_fpga_probe(struct platfo |
| |
| priv->irq = platform_get_irq(pdev, 0); |
| if (priv->irq < 0) { |
| - dev_err(dev, "No IRQ available"); |
| + dev_err(dev, "No IRQ available\n"); |
| return priv->irq; |
| } |
| |
| err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, |
| dev_name(dev), priv); |
| if (err) { |
| - dev_err(dev, "unable to request IRQ"); |
| + dev_err(dev, "unable to request IRQ\n"); |
| return err; |
| } |
| |
| priv->clk = devm_clk_get(dev, "ref_clk"); |
| if (IS_ERR(priv->clk)) { |
| - dev_err(dev, "input clock not found"); |
| + dev_err(dev, "input clock not found\n"); |
| return PTR_ERR(priv->clk); |
| } |
| |
| err = clk_prepare_enable(priv->clk); |
| if (err) { |
| - dev_err(dev, "unable to enable clock"); |
| + dev_err(dev, "unable to enable clock\n"); |
| return err; |
| } |
| |
| @@ -467,7 +467,7 @@ static int zynq_fpga_probe(struct platfo |
| err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager", |
| &zynq_fpga_ops, priv); |
| if (err) { |
| - dev_err(dev, "unable to register FPGA manager"); |
| + dev_err(dev, "unable to register FPGA manager\n"); |
| clk_unprepare(priv->clk); |
| return err; |
| } |