| From e623e96e9d8f94460fcb2488613e64c9583ca4d0 Mon Sep 17 00:00:00 2001 |
| From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
| Date: Wed, 29 Mar 2017 21:36:51 +0300 |
| Subject: [PATCH 169/286] pinctrl: sh-pfc: r8a7791: Add missing DVC_MUTE signal |
| |
| The R8A7791 PFC driver was apparently based on the preliminary revisions |
| of the user's manual, which omitted the DVC_MUTE signal altogether in |
| the PFC section. The modern manual has the signal described, so just add |
| the necassary data to the driver... |
| |
| Fixes: 508845196238 ("pinctrl: sh-pfc: r8a7791 PFC support") |
| Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| (cherry picked from commit 3908632fb829d73317c64c3d04f584b49f62e4ae) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 7 ++++--- |
| 1 file changed, 4 insertions(+), 3 deletions(-) |
| |
| diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c |
| index cc852e68162c..41ac1a3b1964 100644 |
| --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c |
| +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c |
| @@ -203,7 +203,7 @@ enum { |
| |
| /* IPSR6 */ |
| FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, |
| - FN_SCIF_CLK, FN_BPFCLK_E, |
| + FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, |
| FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, |
| FN_SCIFA2_RXD, FN_FMIN_E, |
| FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, |
| @@ -573,7 +573,7 @@ enum { |
| |
| /* IPSR6 */ |
| AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK, |
| - SCIF_CLK_MARK, BPFCLK_E_MARK, |
| + SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK, |
| AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, |
| SCIFA2_RXD_MARK, FMIN_E_MARK, |
| AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, |
| @@ -1093,6 +1093,7 @@ static const u16 pinmux_data[] = { |
| PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), |
| PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), |
| PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0), |
| + PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE), |
| PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4), |
| PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC), |
| PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), |
| @@ -5899,7 +5900,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { |
| 0, 0, |
| /* IP6_2_0 [3] */ |
| FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, |
| - FN_SCIF_CLK, 0, FN_BPFCLK_E, |
| + FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, |
| 0, 0, } |
| }, |
| { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, |
| -- |
| 2.13.3 |
| |
