blob: 6e00d0a2053c382cc22b41588d8765ed162af704 [file] [log] [blame]
From c3bcbf251d600d2aa5c561a8ba939b454baa5d3e Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Thu, 12 Oct 2017 11:35:06 +0200
Subject: [PATCH 0378/1795] ARM: dts: r8a73a4: Add clock for CA15 CPU0 core
Improve hardware description by adding a clocks property to the device
node corresponding to the primary CA15 CPU core, which is for now the
only one described.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit a7869a5bc82682ac31452e178b4b3e9f8b48e7df)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a73a4.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 310222634570..dd4d09712a2a 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -27,6 +27,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
+ clocks = <&cpg_clocks R8A73A4_CLK_Z>;
clock-frequency = <1500000000>;
power-domains = <&pd_a2sl>;
next-level-cache = <&L2_CA15>;
--
2.19.0