| From 6fc1a00cad9bba2e6f8a15bb9025d95b174f04b4 Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Thu, 15 Mar 2018 10:43:47 +0100 |
| Subject: [PATCH 1147/1795] clk: renesas: r8a73a4: Always use readl()/writel() |
| |
| On arm32, there is no reason to use the (soon deprecated) |
| clk_readl()/clk_writel(). Hence use the generic readl()/writel() |
| instead. |
| |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Reviewed-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit b86b493eb29120b82ba919e2653c863c0b3804d6) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| --- |
| drivers/clk/renesas/clk-r8a73a4.c | 11 +++++------ |
| 1 file changed, 5 insertions(+), 6 deletions(-) |
| |
| diff --git a/drivers/clk/renesas/clk-r8a73a4.c b/drivers/clk/renesas/clk-r8a73a4.c |
| index 28d204bb659e..7b903ce4c901 100644 |
| --- a/drivers/clk/renesas/clk-r8a73a4.c |
| +++ b/drivers/clk/renesas/clk-r8a73a4.c |
| @@ -71,7 +71,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, |
| |
| |
| if (!strcmp(name, "main")) { |
| - u32 ckscr = clk_readl(cpg->reg + CPG_CKSCR); |
| + u32 ckscr = readl(cpg->reg + CPG_CKSCR); |
| |
| switch ((ckscr >> 28) & 3) { |
| case 0: /* extal1 */ |
| @@ -95,14 +95,14 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, |
| * clock implementation and we currently have no need to change |
| * the multiplier value. |
| */ |
| - u32 value = clk_readl(cpg->reg + CPG_PLL0CR); |
| + u32 value = readl(cpg->reg + CPG_PLL0CR); |
| |
| parent_name = "main"; |
| mult = ((value >> 24) & 0x7f) + 1; |
| if (value & BIT(20)) |
| div = 2; |
| } else if (!strcmp(name, "pll1")) { |
| - u32 value = clk_readl(cpg->reg + CPG_PLL1CR); |
| + u32 value = readl(cpg->reg + CPG_PLL1CR); |
| |
| parent_name = "main"; |
| /* XXX: enable bit? */ |
| @@ -125,7 +125,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, |
| default: |
| return ERR_PTR(-EINVAL); |
| } |
| - value = clk_readl(cpg->reg + cr); |
| + value = readl(cpg->reg + cr); |
| switch ((value >> 5) & 7) { |
| case 0: |
| parent_name = "main"; |
| @@ -161,8 +161,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, |
| shift = 0; |
| } |
| div *= 32; |
| - mult = 0x20 - ((clk_readl(cpg->reg + CPG_FRQCRC) >> shift) |
| - & 0x1f); |
| + mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f); |
| } else { |
| struct div4_clk *c; |
| |
| -- |
| 2.19.0 |
| |