tree 40c9c8016a4a3743faaca528d628bd9353b2c637
parent 3123109284176b1532874591f7c81f3837bbdc17
author Phil Edworthy <phil.edworthy@renesas.com> 1651578947 +0100
committer Geert Uytterhoeven <geert+renesas@glider.be> 1651745098 +0200

dt-bindings: clock: Add r9a09g011 CPG Clock Definitions

Define RZ/V2M (R9A09G011) Clock Pulse Generator module clock outputs
(CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
in Section 48.5 ("Register Description") of the RZ/V2M Hardware User's
Manual (Rev. 1.10, Sep. 2021).

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-3-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>