tree 76288ff1dca066a581bfdf46bdfbe8a679c991d7
parent be50358fe5cddcfaf6aee93e200200bec692d4fe
author Geert Uytterhoeven <geert+renesas@glider.be> 1498827003 +0200
committer Geert Uytterhoeven <geert+renesas@glider.be> 1504173690 +0200

ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15

On Cortex-A7, the arch timer CNTVOFF register is uninitialized.
Ideally it should be initialized by the boot loader, but it isn't.

For the boot CPU, CNTVOFF is initialized by Linux since commit
9ce3fa6816c2fb59 ("ARM: shmobile: rcar-gen2: Add CA7 arch_timer
initialization for r8a7794").
For secondary CPU cores, no such initialization is done.

Hence when enabling SMP on r8a7794, the kernel log is spammed with:

    WARNING: Underflow in clocksource 'arch_sys_counter' observed, time update ignored.
	     Please report this, consider using a different clocksource, if possible.
	     Your kernel is probably still fine.

As Marc Zyngier pointed out that Cortex-A15 and Cortex-A7 are similar with
respect to CNTVOFF, we have been very lucky this just worked on R-Car
Gen2 SoCs with Cortex-A15 cores.

To fix this:
  - Move the existing inline asm code to initialize CNTVOFF to an
    assembler source file (adding comments and replacing hardcoded
    constants by definitions in the process), so it can be reused,
  - Perform the initialization of CNTVOFF on the boot CPU (Cortex-A15 or
    Cortex-A7) on all R-Car Gen2 and RZ/G1 parts,
  - Wrap the standard secondary_startup() routine inside a routine which
    initializes CNTVOFF.

Based on patches by Hisashi Nakamura in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Replace "isb" by "instr_sync" to fix the arm v6 build (e.g.
    allmodconfig),

v2:
  - Initialize CNTVOFF on Cortex-A15, too,
  - Use *_MODE definitions instead of hardcoded values,
  - Reduce duplication by calling the asm version from C,
  - Always build headsmp-apmu.o on R-Car Gen2.