tree 576eec4a8aacf56f1383d06154768ed6d3fcf293
parent 3c14505c68ca6b3b4d5258886e238f2a81729f06
author Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> 1551988399 +0300
committer Geert Uytterhoeven <geert+renesas@glider.be> 1554193865 +0200

clk: renesas: r8a77980: Fix RPC-IF module clock's parent

Testing has shown that the RPC-IF module clock's parent is the RPCD2
clock, not the RPC one -- the RPC-IF register reads stall otherwise...

Fixes: 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>