| commit | 1e019b186f8a86bce745f2e65a66af311c2774f7 | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Fri Jul 05 15:45:42 2024 +0200 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Tue Jul 16 13:42:42 2024 +0200 |
| tree | 953586c611daa44c397ff0ee35d9b5228d8c20ad | |
| parent | 4d5b457744f3ba20c1ae77634c2a6eb9f1f83ecc [diff] |
clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs Currently, all PLLs are modelled as fixed divider clocks, based on the state of the mode pins. However, the boot loader stack may have changed the actual PLL configuration from the default, leading to incorrect clock frequencies. Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, PLL4, and PLL6 as variable fractional PLLs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>