tree fadce3a81e55073799d080f8ff0d8f9721d555ff
parent 1e019b186f8a86bce745f2e65a66af311c2774f7
author Geert Uytterhoeven <geert+renesas@glider.be> 1720601187 +0200
committer Geert Uytterhoeven <geert+renesas@glider.be> 1721130162 +0200

clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type

The variable PLL2 clock type was superseded by the more generic
variable fractional 8.25 PLL clock type, and its sole user was converted.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>