clk: renesas: rcar-gen3: Fix Z and Z2 clock frequency
This patch fixes the problem that the clock frequency of the Z and Z2
clock is higher than the R-Car Gen3 Hardware User's Manual specification
Rev.0.55.
For Z clock, the clock frequency that can be referenced from the
clk_summary is the same value as specification.
# grep -E -w "pll0|z" /sys/kernel/debug/clk/clk_summary
.pll0 0 0 2995200000 0 0
z 0 0 1497600000 0 0
However, the clock frequency ratio of the FRQCRC.ZFC[4:0] register is
set to 16/32.
For Z2 clock, the clock frequency that can be referenced from the
clk_summary is doubled from specification.
# grep -E -w "pll2|z2" /sys/kernel/debug/clk/clk_summary
.pll2 0 0 2396160000 0 0
z2 0 0 2396160000 0 0
To correct these, add a parameter to set fixed divider that exists in
the path between the PLL output and clock output of Z and Z2.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 file changed
