tree 1938d5a2b61fbd907179621a26f89fc173727507
parent a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd
author Geert Uytterhoeven <geert+renesas@glider.be> 1641566076 +0100
committer Geert Uytterhoeven <geert+renesas@glider.be> 1645519880 +0100

clk: renesas: r8a779f0: Fix RSW2 clock divider

According to Section 8.1.2 Figure 8.1.1 ("Block Diagram of CPG"), Note
22 ("RSW2 divider"), and Table 8.1.4d ("Lists of CPG clocks generated
from CPGMA1"), the RSwitch2 and PCI Express clock is generated from PLL5
by dividing by two, followed by the RSW2 divider.  As PLL5 runs at 3200
MHz, and RSW2 is fixed to 320 MHz, the RSW2 divider must be 5.

Correct the parent and the fixed divider.

Fixes: 24aaff6a6ce4c4de ("clk: renesas: cpg-mssr: Add support for R-Car S4-8")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d6a406f31e6f02f892e0253f4e8a9a2f68fd652e.1641566003.git.geert+renesas@glider.be