tree 9ffbab66263db58d02b91dcfa52a86c5cce5e7ab
parent c2182095c850a02e150613ac026be99ce1c2ff9f
author Takeshi Kihara <takeshi.kihara.df@renesas.com> 1538119080 +0900
committer Geert Uytterhoeven <geert+renesas@glider.be> 1554192509 +0200

clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC

The clock sources of the AXI BUS clock (266.66 MHz) used for SYS-DMAC
DMA transfers are:

    Channel      R-Car H3    R-Car M3-W    R-Car M3-N
    -------------------------------------------------
    SYS-DMAC0    S0D3        S0D3          S0D3
    SYS-DMAC1    S3D1        S3D1          S3D1
    SYS-DMAC2    S3D1        S3D1          S3D1

As a result, change the parent clocks of the SYS-DMAC{1,2} module clocks
on R-Car H3, R-Car M3-W, and R-Car M3-N to S3D1.

NOTE: This information will be reflected in a future revision of the
      R-Car Gen3 Hardware Manual.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>