commit d088502a519fb7834bf6e34cb4e531c1e8113bd1
author Geert Uytterhoeven <geert+renesas@glider.be> Tue Nov 12 10:31:12 2024 +0100
committer Geert Uytterhoeven <geert+renesas@glider.be> Tue Jan 14 11:33:43 2025 +0100
tree 458690e5ce58e1c0c318645db33abd95f57cd327
parent e0a984fbf69f2ab114e2e28579ad58c9598d22d8

[LOCAL] riscv: renesas: defconfig: Update rzfive_defconfig

Update the defconfig for Renesas RZ/Five systems:
  - Compile the kernel with warnings as errors,
  - Disable support for ISA extensions that are not supported by
    RZ/Five:
      - Svnapot extension support for supervisor mode NAPOT pages,
      - Svpbmt extension support for supervisor mode page-based memory
	types,
      - VECTOR extension support,
      - Zawrs extension support for more efficient busy waiting,
      - Zba and Zbb extension support for bit manipulation instructions,
      - Zbc extension support for carry-less multiplication
	instructions,
      - Zicboz extension support for faster zeroing of memory.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

arch/riscv/configs/rzfive_defconfig

diff --git a/arch/riscv/configs/rzfive_defconfig b/arch/riscv/configs/rzfive_defconfig
index fe44f9c..8b6090f 100644
--- a/arch/riscv/configs/rzfive_defconfig
+++ b/arch/riscv/configs/rzfive_defconfig
@@ -1,3 +1,4 @@
+CONFIG_WERROR=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_NO_HZ_IDLE=y
@@ -30,7 +31,15 @@
 CONFIG_ERRATA_SIFIVE=y
 CONFIG_NONPORTABLE=y
 # CONFIG_RISCV_ISA_SUPM is not set
+# CONFIG_RISCV_ISA_SVNAPOT is not set
+# CONFIG_RISCV_ISA_SVPBMT is not set
+# CONFIG_RISCV_ISA_V is not set
+# CONFIG_RISCV_ISA_ZAWRS is not set
+# CONFIG_RISCV_ISA_ZBA is not set
+# CONFIG_RISCV_ISA_ZBB is not set
+# CONFIG_RISCV_ISA_ZBC is not set
 # CONFIG_RISCV_ISA_ZICBOM is not set
+# CONFIG_RISCV_ISA_ZICBOZ is not set
 # CONFIG_EFI is not set
 CONFIG_PM_AUTOSLEEP=y
 CONFIG_CPU_IDLE=y