| commit | 23426d1be3c20907b4f3d72bf95234d4ee254393 | [log] [tgz] |
|---|---|---|
| author | Phil Edworthy <phil.edworthy@renesas.com> | Wed May 04 15:54:46 2022 +0100 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Fri May 06 09:38:40 2022 +0200 |
| tree | 2ec446e7cc89360c1d00315d51a112af86be1095 | |
| parent | 1dd65bb08604ad2906d839c243e1bede2b0efe53 [diff] |
clk: renesas: r9a09g011: Add eth clock and reset entries Add ethernet clock/reset entries to CPG driver. Note that the AXI and CHI clocks are both enabled and disabled using the same register bit. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220504145454.71287-2-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>