| commit | f5a672b0ed67fa75083e13e5f82832cbe7a55e20 | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Wed Jul 10 10:57:16 2024 +0200 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Tue Jul 16 13:42:42 2024 +0200 |
| tree | 4548489913f389ca88dd8870d9986cb02068bb4c | |
| parent | 323e29ef0f2ca7eea932de2a619c9e7e79a668ca [diff] |
clk: renesas: rcar-gen4: Remove unused fixed PLL clock types All users of the fixed default PLL2/3/4/6 clock types have been converted to fixed or variable fractional PLL clock types. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>