clk: renesas: rcar-gen4: Remove unused fixed PLL clock types
All users of the fixed default PLL2/3/4/6 clock types have been
converted to fixed or variable fractional PLL clock types.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c
index 5fcfd0b..b180ca2 100644
--- a/drivers/clk/renesas/rcar-gen4-cpg.c
+++ b/drivers/clk/renesas/rcar-gen4-cpg.c
@@ -439,31 +439,11 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
div = cpg_pll_config->pll1_div;
break;
- case CLK_TYPE_GEN4_PLL2:
- mult = cpg_pll_config->pll2_mult;
- div = cpg_pll_config->pll2_div;
- break;
-
- case CLK_TYPE_GEN4_PLL3:
- mult = cpg_pll_config->pll3_mult;
- div = cpg_pll_config->pll3_div;
- break;
-
- case CLK_TYPE_GEN4_PLL4:
- mult = cpg_pll_config->pll4_mult;
- div = cpg_pll_config->pll4_div;
- break;
-
case CLK_TYPE_GEN4_PLL5:
mult = cpg_pll_config->pll5_mult;
div = cpg_pll_config->pll5_div;
break;
- case CLK_TYPE_GEN4_PLL6:
- mult = cpg_pll_config->pll6_mult;
- div = cpg_pll_config->pll6_div;
- break;
-
case CLK_TYPE_GEN4_PLL2X_3X:
value = readl(base + core->offset);
mult = (FIELD_GET(CPG_PLLxCR_STC, value) + 1) * 2;
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
index 9bca280..13f4ae2 100644
--- a/drivers/clk/renesas/rcar-gen4-cpg.h
+++ b/drivers/clk/renesas/rcar-gen4-cpg.h
@@ -12,12 +12,8 @@
enum rcar_gen4_clk_types {
CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,
CLK_TYPE_GEN4_PLL1,
- CLK_TYPE_GEN4_PLL2,
CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
- CLK_TYPE_GEN4_PLL3,
- CLK_TYPE_GEN4_PLL4,
CLK_TYPE_GEN4_PLL5,
- CLK_TYPE_GEN4_PLL6,
CLK_TYPE_GEN4_PLL_F8_25, /* Fixed fractional 8.25 PLL */
CLK_TYPE_GEN4_PLL_V8_25, /* Variable fractional 8.25 PLL */
CLK_TYPE_GEN4_PLL_F9_24, /* Fixed fractional 9.24 PLL */
