refs/tags/clk-renesas-rzg3e-plldsi-tag - pub/scm/linux/kernel/git/geert/renesas-drivers

tag: 3b7c85ac4758fa9d309af5e8ab4d8ff3b7483b00
tagger: Geert Uytterhoeven <geert+renesas@glider.be>
Mon May 04 14:04:16 2026 +0200
object: 272a6e2ad164094045af520299b5df3ce1763061

clk: renesas: rzg3e: Add support for DSI clocks

RZ/G3E Clock Pulse Generator PLLDSI limits, shared by clock and MIPI DSI
driver source files.

commit: 272a6e2ad164094045af520299b5df3ce1763061
[log]
author: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Wed Apr 08 12:36:53 2026 +0200
committer: Geert Uytterhoeven <geert+renesas@glider.be>
Mon May 04 14:03:08 2026 +0200
tree: 7846f09560b3dcaad92e19289dd9b5c94fdb9e46
parent: fe9a5541f096da191a153e92e04a1887307e4186 [diff]

clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets

Add LCDC{0,1} clocks and resets entries to the r9a09g047 CPG driver.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/c1b5afcef8068d4d074aff97e30b4d64b7c38eaf.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

drivers/clk/renesas/r9a09g047-cpg.c[diff]

1 file changed

tree: 7846f09560b3dcaad92e19289dd9b5c94fdb9e46