| From d70f7d31a9e2088e8a507194354d41ea10062994 Mon Sep 17 00:00:00 2001 |
| From: Dmitry Osipenko <digetx@gmail.com> |
| Date: Tue, 30 Jul 2019 20:23:39 +0300 |
| Subject: ARM: tegra: Fix FLOW_CTLR_HALT register clobbering by tegra_resume() |
| |
| From: Dmitry Osipenko <digetx@gmail.com> |
| |
| commit d70f7d31a9e2088e8a507194354d41ea10062994 upstream. |
| |
| There is an unfortunate typo in the code that results in writing to |
| FLOW_CTLR_HALT instead of FLOW_CTLR_CSR. |
| |
| Cc: <stable@vger.kernel.org> |
| Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> |
| Signed-off-by: Dmitry Osipenko <digetx@gmail.com> |
| Signed-off-by: Thierry Reding <treding@nvidia.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm/mach-tegra/reset-handler.S | 6 +++--- |
| 1 file changed, 3 insertions(+), 3 deletions(-) |
| |
| --- a/arch/arm/mach-tegra/reset-handler.S |
| +++ b/arch/arm/mach-tegra/reset-handler.S |
| @@ -56,16 +56,16 @@ ENTRY(tegra_resume) |
| cmp r6, #TEGRA20 |
| beq 1f @ Yes |
| /* Clear the flow controller flags for this CPU. */ |
| - cpu_to_csr_reg r1, r0 |
| + cpu_to_csr_reg r3, r0 |
| mov32 r2, TEGRA_FLOW_CTRL_BASE |
| - ldr r1, [r2, r1] |
| + ldr r1, [r2, r3] |
| /* Clear event & intr flag */ |
| orr r1, r1, \ |
| #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG |
| movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps |
| @ & ext flags for CPU power mgnt |
| bic r1, r1, r0 |
| - str r1, [r2] |
| + str r1, [r2, r3] |
| 1: |
| |
| mov32 r9, 0xc09 |
