Merge branch 'v4.14.75-ltsi/dts-rcar-gen3.rc8' into v4.14.75-ltsi/rcar-3.9.0
* v4.14.75-ltsi/dts-rcar-gen3.rc8: (310 commits)
arm64: dts: r8a77990: Support IPMMU(MMU mode) for IPMMU-VP0 and IPMMU-VC0
arm64: dts: r8a77965: Support IPMMU(MMU mode) for IPMMU-VP0 and IPMMU-VC0
arm64: dts: r8a7796: Support IPMMU(MMU mode) for IPMMU-VC0
arm64: dts: r8a7795: Support IPMMU(MMU mode) for IPMMU-VP0/1 and IPMMU VC0/1
arm64: dts: r8a77990: Change IPMMU-MM and IPMMU-caches order in DT
arm64: dts: r8a77965: Change IPMMU-MM and IPMMU-caches order in DT
arm64: dts: r8a7796: Change IPMMU-MM and IPMMU-caches order in DT
arm64: dts: r8a7795: Change IPMMU-MM and IPMMU-caches order in DT
arm64: dts: r8a77990: Tie Audio-DMAC to IPMMU-MP
arm64: dts: r8a77965: Tie Audio-DMAC to IPMMU-MP
arm64: dts: r8a7795-es1: Add power domains property for IPMMU device nodes
arm64: dts: renesas: r8a77990: Change default of all IPMMU devices to disable
arm64: dts: renesas: r8a77965: Change default of all IPMMU devices to disable
arm64: dts: r8a77990: Detach IPMMU-VI0/1 from FCPVD
Revert "arm64: dts: renesas: r8a7795: Point DU/VSPD via FCPVD to IPMMU-VI0/1"
Revert "arm64: dts: renesas: r8a7795-es1: Point DU/VSPD via FCPVD to IPMMU-VI0"
Revert "arm64: dts: renesas: r8a7795: Connect Ethernet-AVB to IPMMU-DS0"
Revert "arm64: dts: renesas: r8a7795: Connect SATA to IPMMU-HC"
Revert "arm64: dts: renesas: r8a7795: Enable IPMMU-VI0, VP1, DS0, DS1 and MM"
Revert "arm64: dts: renesas: r8a7795: Enable IPMMU devices"
Revert "arm64: dts: renesas: r8a7795-es1: Enable IPMMU-MP1"
Revert "arm64: dts: renesas: r8a7795-es1: Enable IPMMU devices"
Revert "arm64: dts: renesas: r8a7796: Point FDP1 via FCPF to IPMMU-VI0"
Revert "arm64: dts: renesas: r8a7796: Connect Ethernet-AVB to IPMMU-DS0"
Revert "arm64: dts: renesas: r8a7796: Enable IPMMU-DS0, DS1, MP, VI0, VC0 and MM"
Revert "arm64: dts: renesas: r8a7796: Enable IPMMU devices"
arm64: dts: ulcb: Change to use "audio-graph-card"
arm64: dts: r8a7795-h3ulcb-4x2g: Overwrite dma-ranges of pcie nodes for R-Car H3 ES2.0/3.0
arm64: dts: r8a7795-h3ulcb-4x2g.dts: Add H3ULCB (4 x 2 GiB) support
arm64: dts: r8a7795-h3ulcb: Fix source clock for DU2
...
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index d8cf740..3965ce3 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -81,6 +81,7 @@
compatible = "renesas,gose", "renesas,r8a7793"
- H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1))
H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0))
+ H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA03 (H3 ES2.0))
compatible = "renesas,h3ulcb", "renesas,r8a7795"
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index f24fde5..c8f2891 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -2,15 +2,21 @@
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
+dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs-4x2g.dtb
+dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs-2x2g.dtb
+dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-4x2g.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb r8a7795-es1-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-h3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
+dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs-2x4g.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
+dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu-4d.dtb
+dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-es10-ebisu.dtb r8a77990-es10-ebisu-4d.dtb
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
always := $(dtb-y)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
index 009cb1c..2f24dfc 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the H3ULCB Kingfisher board
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include "r8a7795-es1-h3ulcb.dts"
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts
index dd4f9b6..119f06c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
*
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
/dts-v1/;
@@ -37,4 +34,68 @@
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress@54000000 {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma@57000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x19000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia@70000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x70000000 0x0 0x10000000>;
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+};
+
+&sdhi2 {
+ /delete-property/ mmc-hs400-1_8v;
+};
+
+&vspbc {
+ status = "okay";
+};
+
+&vspbd {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
+
+&vspi1 {
+ status = "okay";
+};
+
+&vspi2 {
+ status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
index 3f46345..5c3935e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X board with R-Car H3 ES1.x
*
* Copyright (C) 2015 Renesas Electronics Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
/dts-v1/;
@@ -36,6 +33,58 @@
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress@54000000 {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+
+ /* For Audio DSP */
+ adsp_reserved: linux,adsp@57000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x01000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x58000000 0x0 0x18000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia@70000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x70000000 0x0 0x10000000>;
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+};
+
+&adsp {
+ status = "okay";
+ memory-region = <&adsp_reserved>;
};
&du {
@@ -43,15 +92,24 @@
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
- <&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+ clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
+&lvds0 {
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+ };
+};
+
&ehci2 {
status = "okay";
};
@@ -116,6 +174,7 @@
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
+ reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
@@ -127,6 +186,7 @@
};
};
rsnd_port2: port@2 {
+ reg = <2>;
rsnd_endpoint2: endpoint {
remote-endpoint = <&dw_hdmi1_snd_in>;
@@ -157,3 +217,23 @@
status = "okay";
};
+
+&vspbc {
+ status = "okay";
+};
+
+&vspbd {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
+
+&vspi1 {
+ status = "okay";
+};
+
+&vspi2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index e19dcd6..600f56c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the r8a7795 ES1.x SoC
+ * Device Tree Source for the R-Car H3 (R8A77950) ES1.x SoC
*
* Copyright (C) 2015 Renesas Electronics Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include "r8a7795.dtsi"
@@ -31,14 +28,18 @@
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xec680000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 5>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_sy: mmu@e7730000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe7730000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
/delete-node/ usb-phy@ee0e0200;
@@ -49,38 +50,115 @@
/delete-node/ dma-controller@e6460000;
/delete-node/ dma-controller@e6470000;
- fcpf2: fcp@fe952000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe952000 0 0x200>;
- clocks = <&cpg CPG_MOD 613>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 613>;
- iommus = <&ipmmu_vp0 2>;
+ vcp4@fe8f0000 {
+ compatible = "renesas,vcp4-vcpl4";
+ reg = <0 0xfe8f0000 0 0x200>, <0 0xfe8f0200 0 0x200>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 129>;
+ power-domains = <&sysc R8A7795_PD_A2VC0>;
+ resets = <&cpg 129>;
+ renesas,#ch = <1>;
+ renesas,#fcp_ch = <1>;
};
- vspi2: vsp@fe9c0000 {
- compatible = "renesas,vsp2";
+ vcp4@fe900000 {
+ renesas,#ch = <2>;
+ };
+
+ vcp4@fe8d0000 {
+ renesas,#ch = <3>;
+ renesas,#fcp_ch = <2>;
+ };
+
+ fcpci0: vcp4@fe8df000 {
+ compatible = "renesas,vcp4-fcpci0";
+ reg = <0 0xfe8df000 0 0x200>;
+ clocks = <&cpg CPG_MOD 617>;
+ power-domains = <&sysc R8A7795_PD_A3VC>;
+ resets = <&cpg 617>;
+ renesas,#ch = <2>;
+ };
+
+ fcpci1: vcp4@fe8ff000 {
+ compatible = "renesas,vcp4-fcpci1";
+ reg = <0 0xfe8ff000 0 0x200>;
+ clocks = <&cpg CPG_MOD 616>;
+ power-domains = <&sysc R8A7795_PD_A3VC>;
+ resets = <&cpg 616>;
+ renesas,#ch = <1>;
+ };
+
+ stb: vcp4@fe8a0000 {
+ compatible = "renesas,vcp4-stb";
+ reg = <0 0xfe8a0000 0 0x200>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 104>;
+ power-domains = <&sysc R8A7795_PD_A3VC>;
+ resets = <&cpg 104>;
+ };
+
+ vspm@fe920000 {
+ renesas,#rpf_clut = <4>;
+ /delete-property/ renesas,#start_reservation;
+ /delete-property/ renesas,#burst_access;
+ };
+
+ vspm@fe960000 {
+ renesas,#rpf_clut = <4>;
+ /delete-property/ renesas,#start_reservation;
+ /delete-property/ renesas,#burst_access;
+ };
+
+ vspm@fe9a0000 {
+ /delete-property/ renesas,#start_reservation;
+ };
+
+ vspm@fe9b0000 {
+ /delete-property/ renesas,#start_reservation;
+ };
+
+ vsp@fe9c0000 {
+ compatible = "renesas,vspm-vsp2";
reg = <0 0xfe9c0000 0 0x8000>;
- interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 629>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 629>;
-
- renesas,fcp = <&fcpvi2>;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hgo;
+ renesas,has-hgt;
+ renesas,#rpf = <1>;
+ renesas,#uds = <1>;
+ renesas,#wpf = <1>;
};
- fcpvi2: fcp@fe9cf000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9cf000 0 0x200>;
- clocks = <&cpg CPG_MOD 609>;
+ vspi2: vspm@fe9c0000 {
+ compatible = "renesas,vspm";
+ reg = <0 0xfe9c0000 0 0x8000>, <0 0xfe9cf000 0 0x200>;
+ interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 629>, <&cpg CPG_MOD 609>;
+ clock-names = "vsp", "fcp";
+ renesas,#ch = <2>;
+ renesas,#rpf = <1>;
+ renesas,#rpf_clut = <1>;
+ renesas,#wpf_rot = <1>;
+ renesas,has-sru;
+ renesas,has-uds;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hst;
+ renesas,has-hsi;
+ renesas,has-hgo;
+ renesas,has-hgt;
+ renesas,has-shp;
+ renesas,#read_outstanding = <2>;
power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 609>;
- iommus = <&ipmmu_vp0 10>;
+ resets = <&cpg 629>, <&cpg 609>;
+ reset-names = "vsp", "fcp";
+ status = "disabled";
};
vspd3: vsp@fea38000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea38000 0 0x8000>;
+ reg = <0 0xfea38000 0 0x5000>;
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 620>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -95,17 +173,18 @@
clocks = <&cpg CPG_MOD 600>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 600>;
- iommus = <&ipmmu_vi0 11>;
};
- fdp1@fe948000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe948000 0 0x2400>;
+ fdp2: fdpm@fe948000 {
+ compatible = "renesas,fdpm";
+ reg = <0 0xfe948000 0 0x2400>, <0 0xfe952000 0 0x200>;
interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 117>;
+ clocks = <&cpg CPG_MOD 117>, <&cpg CPG_MOD 613>;
+ clock-names = "fdp", "fcp";
power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 117>;
- renesas,fcp = <&fcpf2>;
+ resets = <&cpg 117>, <&cpg 613>;
+ reset-names = "fdp", "fcp";
+ renesas,#ch = <2>;
};
csi21: csi2@fea90000 {
@@ -210,22 +289,6 @@
<&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
};
-&fcpvb1 {
- iommus = <&ipmmu_vp0 7>;
-};
-
-&fcpf1 {
- iommus = <&ipmmu_vp0 1>;
-};
-
-&fcpvi1 {
- iommus = <&ipmmu_vp0 9>;
-};
-
-&fcpvd2 {
- iommus = <&ipmmu_vi0 10>;
-};
-
&du {
vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
};
@@ -235,7 +298,7 @@
port@1 {
vin0csi21: endpoint@1 {
reg = <1>;
- remote-endpoint= <&csi21vin0>;
+ remote-endpoint = <&csi21vin0>;
};
};
};
@@ -246,7 +309,7 @@
port@1 {
vin1csi21: endpoint@1 {
reg = <1>;
- remote-endpoint= <&csi21vin1>;
+ remote-endpoint = <&csi21vin1>;
};
};
};
@@ -257,7 +320,7 @@
port@1 {
vin2csi21: endpoint@1 {
reg = <1>;
- remote-endpoint= <&csi21vin2>;
+ remote-endpoint = <&csi21vin2>;
};
};
};
@@ -268,7 +331,7 @@
port@1 {
vin3csi21: endpoint@1 {
reg = <1>;
- remote-endpoint= <&csi21vin3>;
+ remote-endpoint = <&csi21vin3>;
};
};
};
@@ -279,7 +342,7 @@
port@1 {
vin4csi21: endpoint@1 {
reg = <1>;
- remote-endpoint= <&csi21vin4>;
+ remote-endpoint = <&csi21vin4>;
};
};
};
@@ -290,7 +353,7 @@
port@1 {
vin5csi21: endpoint@1 {
reg = <1>;
- remote-endpoint= <&csi21vin5>;
+ remote-endpoint = <&csi21vin5>;
};
};
};
@@ -301,7 +364,7 @@
port@1 {
vin6csi21: endpoint@1 {
reg = <1>;
- remote-endpoint= <&csi21vin6>;
+ remote-endpoint = <&csi21vin6>;
};
};
};
@@ -312,7 +375,7 @@
port@1 {
vin7csi21: endpoint@1 {
reg = <1>;
- remote-endpoint= <&csi21vin7>;
+ remote-endpoint = <&csi21vin7>;
};
};
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-4x2g.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-4x2g.dts
new file mode 100644
index 0000000..15c034b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-4x2g.dts
@@ -0,0 +1,47 @@
+/*
+ * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "r8a7795-h3ulcb.dts"
+
+/ {
+ model = "Renesas H3ULCB board based on H3ULCB + with 8GiB (4 x 2 GiB)";
+ compatible = "renesas,h3ulcb", "renesas,r8a7795";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ memory@500000000 {
+ device_type = "memory";
+ reg = <0x5 0x00000000 0x0 0x80000000>;
+ };
+
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x80000000>;
+ };
+
+ memory@700000000 {
+ device_type = "memory";
+ reg = <0x7 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&pciec0 {
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+};
+
+&pciec1 {
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts
index 4403227..80791ed 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the H3ULCB Kingfisher board
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include "r8a7795-h3ulcb.dts"
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index 0afe777..87132c0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
*
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2018 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
/dts-v1/;
@@ -37,6 +34,60 @@
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress@54000000 {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma@57000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x19000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia@70000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x70000000 0x0 0x10000000>;
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+
+ versaclock5_out3: versaclk-3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* Initial value of versaclock out3 */
+ clock-frequency = <33000000>;
+ };
+
+ versaclock5_out4: versaclk-4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* Initial value of versaclock out4 */
+ clock-frequency = <33000000>;
+ };
};
&du {
@@ -44,11 +95,26 @@
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
- <&cpg CPG_MOD 727>,
<&versaclock5 1>,
- <&versaclock5 3>,
- <&versaclock5 4>,
+ <&versaclock5_out3>,
+ <&versaclock5_out4>,
<&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+ clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
+
+&vspbc {
+ status = "okay";
+};
+
+&vspbd {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
+
+&vspi1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 0efbef5..6928afb 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X board with R-Car H3 ES2.0
*
* Copyright (C) 2015 Renesas Electronics Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
/dts-v1/;
@@ -36,6 +33,58 @@
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress@54000000 {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+
+ /* For Audio DSP */
+ adsp_reserved: linux,adsp@57000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x01000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x58000000 0x0 0x18000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia@70000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x70000000 0x0 0x10000000>;
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+};
+
+&adsp {
+ status = "okay";
+ memory-region = <&adsp_reserved>;
};
&du {
@@ -43,12 +92,11 @@
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
- <&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+ clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
@@ -108,6 +156,16 @@
remote-endpoint = <&rcar_dw_hdmi1_out>;
};
+&lvds0 {
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+ };
+};
+
&ohci2 {
status = "okay";
};
@@ -116,6 +174,7 @@
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
+ reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
@@ -127,6 +186,7 @@
};
};
rsnd_port2: port@2 {
+ reg = <2>;
rsnd_endpoint2: endpoint {
remote-endpoint = <&dw_hdmi1_snd_in>;
@@ -157,3 +217,19 @@
status = "okay";
};
+
+&vspbc {
+ status = "okay";
+};
+
+&vspbd {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
+
+&vspi1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs-2x2g.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs-2x2g.dts
new file mode 100644
index 0000000..5f43545
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs-2x2g.dts
@@ -0,0 +1,40 @@
+/*
+ * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES3.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "r8a7795-salvator-xs.dts"
+
+/ {
+ model = "Renesas Salvator-X 2nd version board based on r8a7795 ES3.0+ with 4GiB (2 x 2 GiB)";
+ compatible = "renesas,salvator-xs", "renesas,r8a7795";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ memory@500000000 {
+ device_type = "memory";
+ reg = <0x5 0x00000000 0x0 0x80000000>;
+ };
+
+ /delete-node/ memory@600000000;
+ /delete-node/ memory@700000000;
+};
+
+&pciec0 {
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+};
+
+&pciec1 {
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs-4x2g.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs-4x2g.dts
new file mode 100644
index 0000000..5fd5b59
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs-4x2g.dts
@@ -0,0 +1,47 @@
+/*
+ * Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES3.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "r8a7795-salvator-xs.dts"
+
+/ {
+ model = "Renesas Salvator-X 2nd version board based on r8a7795 ES3.0+ with 8GiB (4 x 2 GiB)";
+ compatible = "renesas,salvator-xs", "renesas,r8a7795";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ memory@500000000 {
+ device_type = "memory";
+ reg = <0x5 0x00000000 0x0 0x80000000>;
+ };
+
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x80000000>;
+ };
+
+ memory@700000000 {
+ device_type = "memory";
+ reg = <0x7 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&pciec0 {
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+};
+
+&pciec1 {
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
index e231b5a..498f788 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X 2nd version board with R-Car H3 ES2.0
*
* Copyright (C) 2015-2017 Renesas Electronics Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
/dts-v1/;
@@ -36,6 +33,58 @@
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x40000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress@54000000 {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+
+ /* For Audio DSP */
+ adsp_reserved: linux,adsp@57000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x01000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x58000000 0x0 0x18000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia@70000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x70000000 0x0 0x10000000>;
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+};
+
+&adsp {
+ status = "okay";
+ memory-region = <&adsp_reserved>;
};
&du {
@@ -43,12 +92,11 @@
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
- <&cpg CPG_MOD 727>,
<&versaclock6 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock6 2>;
- clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+ clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
@@ -118,6 +166,16 @@
remote-endpoint = <&rcar_dw_hdmi1_out>;
};
+&lvds0 {
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+ };
+};
+
&ohci2 {
status = "okay";
};
@@ -131,6 +189,7 @@
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
+ reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
@@ -142,6 +201,7 @@
};
};
rsnd_port2: port@2 {
+ reg = <2>;
rsnd_endpoint2: endpoint {
remote-endpoint = <&dw_hdmi1_snd_in>;
@@ -192,3 +252,19 @@
status = "okay";
};
+
+&vspbc {
+ status = "okay";
+};
+
+&vspbd {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
+
+&vspi1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index d842940..1896e52 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the r8a7795 SoC
+ * Device Tree Source for the R-Car H3 (R8A77950) SoC
*
- * Copyright (C) 2015 Renesas Electronics Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2015-2017 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
@@ -28,6 +25,10 @@
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
+ spi0 = &msiof0;
+ spi1 = &msiof1;
+ spi2 = &msiof2;
+ spi3 = &msiof3;
};
/*
@@ -60,7 +61,7 @@
clock-frequency = <0>;
};
- cluster0_opp: opp_table0 {
+ cluster0_opp0: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
@@ -94,7 +95,245 @@
};
};
- cluster1_opp: opp_table1 {
+ cluster0_opp1: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <890000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster0_opp2: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <810000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <810000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <810000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <880000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <930000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster0_opp3: opp_table3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <870000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <910000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster0_opp4: opp_table4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <790000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <790000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <790000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <860000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <890000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster0_opp5: opp_table5 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <780000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <780000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <780000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <850000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <880000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster0_opp6: opp_table6 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <770000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <770000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <770000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <870000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster0_opp7: opp_table7 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <760000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <760000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <760000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <860000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster1_opp: opp_table10 {
compatible = "operating-points-v2";
opp-shared;
@@ -112,6 +351,7 @@
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
+ opp-suspend;
};
};
@@ -119,6 +359,38 @@
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&a57_0>;
+ };
+ core1 {
+ cpu = <&a57_1>;
+ };
+ core2 {
+ cpu = <&a57_2>;
+ };
+ core3 {
+ cpu = <&a57_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&a53_0>;
+ };
+ core1 {
+ cpu = <&a53_1>;
+ };
+ core2 {
+ cpu = <&a53_2>;
+ };
+ core3 {
+ cpu = <&a53_3>;
+ };
+ };
+ };
+
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
@@ -126,9 +398,18 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
+ dynamic-power-coefficient = <854>;
+ cooling-min-level = <0>;
+ cooling-max-level = <2>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp0>,
+ <&cluster0_opp1>, <&cluster0_opp2>,
+ <&cluster0_opp3>, <&cluster0_opp4>,
+ <&cluster0_opp5>, <&cluster0_opp6>,
+ <&cluster0_opp7>;
#cooling-cells = <2>;
+ capacity-dmips-mhz = <1024>;
};
a57_1: cpu@1 {
@@ -138,9 +419,15 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp0>,
+ <&cluster0_opp1>, <&cluster0_opp2>,
+ <&cluster0_opp3>, <&cluster0_opp4>,
+ <&cluster0_opp5>, <&cluster0_opp6>,
+ <&cluster0_opp7>;
#cooling-cells = <2>;
+ capacity-dmips-mhz = <1024>;
};
a57_2: cpu@2 {
@@ -150,9 +437,15 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp0>,
+ <&cluster0_opp1>, <&cluster0_opp2>,
+ <&cluster0_opp3>, <&cluster0_opp4>,
+ <&cluster0_opp5>, <&cluster0_opp6>,
+ <&cluster0_opp7>;
#cooling-cells = <2>;
+ capacity-dmips-mhz = <1024>;
};
a57_3: cpu@3 {
@@ -162,9 +455,15 @@
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp0>,
+ <&cluster0_opp1>, <&cluster0_opp2>,
+ <&cluster0_opp3>, <&cluster0_opp4>,
+ <&cluster0_opp5>, <&cluster0_opp6>,
+ <&cluster0_opp7>;
#cooling-cells = <2>;
+ capacity-dmips-mhz = <1024>;
};
a53_0: cpu@100 {
@@ -174,8 +473,14 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <277>;
+ cooling-min-level = <0>;
+ cooling-max-level = <2>;
+ cpu-idle-states = <&CPU_SLEEP_1>;
+ clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <540>;
};
a53_1: cpu@101 {
@@ -185,8 +490,10 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+ cpu-idle-states = <&CPU_SLEEP_1>;
+ clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <540>;
};
a53_2: cpu@102 {
@@ -196,8 +503,10 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+ cpu-idle-states = <&CPU_SLEEP_1>;
+ clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <540>;
};
a53_3: cpu@103 {
@@ -207,8 +516,10 @@
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+ cpu-idle-states = <&CPU_SLEEP_1>;
+ clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <540>;
};
L2_CA57: cache-controller-0 {
@@ -224,6 +535,30 @@
cache-unified;
cache-level = <2>;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <400>;
+ exit-latency-us = <500>;
+ min-residency-us = <4000>;
+ status = "okay";
+ };
+
+ CPU_SLEEP_1: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <700>;
+ exit-latency-us = <700>;
+ min-residency-us = <5000>;
+ status = "okay";
+ };
+ };
};
extal_clk: extal {
@@ -240,6 +575,188 @@
clock-frequency = <0>;
};
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ gsx_opp0: gsx_opp_table0 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <830000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <830000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <830000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <830000>;
+ };
+ };
+
+ gsx_opp1: gsx_opp_table1 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <820000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <820000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <820000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <820000>;
+ };
+ };
+
+ gsx_opp2: gsx_opp_table2 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <810000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <810000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <810000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <810000>;
+ };
+ };
+
+ gsx_opp3: gsx_opp_table3 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ };
+ };
+
+ gsx_opp4: gsx_opp_table4 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <790000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <790000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <790000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <790000>;
+ };
+ };
+
+ gsx_opp5: gsx_opp_table5 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <780000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <780000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <780000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <780000>;
+ };
+ };
+
+ gsx_opp6: gsx_opp_table6 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <770000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <770000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <770000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <770000>;
+ };
+ };
+
+ gsx_opp7: gsx_opp_table7 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <760000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <760000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <760000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <760000>;
+ };
+ };
+
+ /* MSIOF reference clock - to be overridden by boards that provide it */
+ msiof_ref_clk: msiof-ref-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
@@ -291,7 +808,22 @@
#size-cells = <2>;
ranges;
- wdt0: watchdog@e6020000 {
+ mfis: mfis@e6260000 {
+ compatible = "renesas,mfis-lock-r8a7795",
+ "renesas,mfis-lock";
+ reg = <0 0xe6260000 0 0x1000>;
+ #hwlock-cells = <1>;
+
+ mfis_as: mfis-as {
+ compatible = "renesas,mfis-as-r8a7795",
+ "renesas,mfis-as";
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eicr0";
+ renesas,mfis-ch = <0>;
+ };
+ };
+
+ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
@@ -425,6 +957,12 @@
reg = <0 0xe6060000 0 0x50c>;
};
+ avs: avs@e60a013c {
+ compatible = "renesas,r8a7795-avs", "renesas,rcar-gen3-avs";
+ reg = <0 0xe60a013c 0 0x04>;
+ target_devices = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>, <&gsx>;
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7795-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@@ -472,9 +1010,7 @@
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
};
i2c0: i2c@e6500000 {
@@ -656,7 +1192,7 @@
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
<&dmac2 0x35>, <&dmac2 0x34>;
- dma-names = "tx", "rx";
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 518>;
status = "disabled";
@@ -699,9 +1235,9 @@
hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7795",
"renesas,rcar-gen3-usbhs";
- reg = <0 0xe6590000 0 0x100>;
+ reg = <0 0xe6590000 0 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>;
+ clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
@@ -709,16 +1245,16 @@
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
+ resets = <&cpg 704>, <&cpg 703>;
status = "disabled";
};
hsusb3: usb@e659c000 {
compatible = "renesas,usbhs-r8a7795",
"renesas,rcar-gen3-usbhs";
- reg = <0 0xe659c000 0 0x100>;
+ reg = <0 0xe659c000 0 0x200>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 705>;
+ clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>;
dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
<&usb_dmac3 0>, <&usb_dmac3 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
@@ -726,7 +1262,7 @@
phys = <&usb2_phy3>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 705>;
+ resets = <&cpg 705>, <&cpg 700>;
status = "disabled";
};
@@ -925,12 +1461,23 @@
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
};
+ ipmmu_mm: mmu@e67b0000 {
+ compatible = "renesas,ipmmu-r8a7795";
+ reg = <0 0xe67b0000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
ipmmu_ds0: mmu@e6740000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_ds1: mmu@e7740000 {
@@ -939,6 +1486,7 @@
renesas,ipmmu-main = <&ipmmu_mm 1>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_hc: mmu@e6570000 {
@@ -947,6 +1495,7 @@
renesas,ipmmu-main = <&ipmmu_mm 2>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_ir: mmu@ff8b0000 {
@@ -955,15 +1504,7 @@
renesas,ipmmu-main = <&ipmmu_mm 3>;
power-domains = <&sysc R8A7795_PD_A3IR>;
#iommu-cells = <1>;
- };
-
- ipmmu_mm: mmu@e67b0000 {
- compatible = "renesas,ipmmu-r8a7795";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_mp0: mmu@ec670000 {
@@ -972,6 +1513,7 @@
renesas,ipmmu-main = <&ipmmu_mm 4>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_pv0: mmu@fd800000 {
@@ -980,6 +1522,7 @@
renesas,ipmmu-main = <&ipmmu_mm 6>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_pv1: mmu@fd950000 {
@@ -988,6 +1531,7 @@
renesas,ipmmu-main = <&ipmmu_mm 7>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_pv2: mmu@fd960000 {
@@ -996,6 +1540,7 @@
renesas,ipmmu-main = <&ipmmu_mm 8>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_pv3: mmu@fd970000 {
@@ -1004,6 +1549,7 @@
renesas,ipmmu-main = <&ipmmu_mm 9>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_rt: mmu@ffc80000 {
@@ -1012,22 +1558,25 @@
renesas,ipmmu-main = <&ipmmu_mm 10>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_vc0: mmu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a7795";
+ compatible = "renesas,ipmmu-mmu-r8a7795";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
power-domains = <&sysc R8A7795_PD_A3VC>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_vc1: mmu@fe6f0000 {
- compatible = "renesas,ipmmu-r8a7795";
+ compatible = "renesas,ipmmu-mmu-r8a7795";
reg = <0 0xfe6f0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 13>;
power-domains = <&sysc R8A7795_PD_A3VC>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_vi0: mmu@febd0000 {
@@ -1036,6 +1585,7 @@
renesas,ipmmu-main = <&ipmmu_mm 14>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_vi1: mmu@febe0000 {
@@ -1044,22 +1594,30 @@
renesas,ipmmu-main = <&ipmmu_mm 15>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_vp0: mmu@fe990000 {
- compatible = "renesas,ipmmu-r8a7795";
+ compatible = "renesas,ipmmu-mmu-r8a7795";
reg = <0 0xfe990000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 16>;
power-domains = <&sysc R8A7795_PD_A3VP>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_vp1: mmu@fe980000 {
- compatible = "renesas,ipmmu-r8a7795";
+ compatible = "renesas,ipmmu-mmu-r8a7795";
reg = <0 0xfe980000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 17>;
power-domains = <&sysc R8A7795_PD_A3VP>;
#iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ qos@e67e0000 {
+ compatible = "renesas,qos";
+ reg = <0 0xe67e0000 0 0x10090>;
};
avb: ethernet@e6800000 {
@@ -1102,7 +1660,6 @@
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
- iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1278,9 +1835,6 @@
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
- dmas = <&dmac1 0x13>, <&dmac1 0x12>,
- <&dmac2 0x13>, <&dmac2 0x12>;
- dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
@@ -1340,7 +1894,8 @@
"renesas,rcar-gen3-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
+ clocks = <&cpg CPG_MOD 211>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
dma-names = "tx", "rx", "tx", "rx";
@@ -1356,7 +1911,8 @@
"renesas,rcar-gen3-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
+ clocks = <&cpg CPG_MOD 210>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
@@ -1372,7 +1928,8 @@
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
+ clocks = <&cpg CPG_MOD 209>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -1387,7 +1944,8 @@
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
+ clocks = <&cpg CPG_MOD 208>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -1419,11 +1977,11 @@
vin0csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin0>;
+ remote-endpoint = <&csi20vin0>;
};
vin0csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin0>;
+ remote-endpoint = <&csi40vin0>;
};
};
};
@@ -1451,11 +2009,11 @@
vin1csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin1>;
+ remote-endpoint = <&csi20vin1>;
};
vin1csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin1>;
+ remote-endpoint = <&csi40vin1>;
};
};
};
@@ -1483,11 +2041,11 @@
vin2csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin2>;
+ remote-endpoint = <&csi20vin2>;
};
vin2csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin2>;
+ remote-endpoint = <&csi40vin2>;
};
};
};
@@ -1515,11 +2073,11 @@
vin3csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin3>;
+ remote-endpoint = <&csi20vin3>;
};
vin3csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin3>;
+ remote-endpoint = <&csi40vin3>;
};
};
};
@@ -1547,11 +2105,11 @@
vin4csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin4>;
+ remote-endpoint = <&csi20vin4>;
};
vin4csi41: endpoint@3 {
reg = <3>;
- remote-endpoint= <&csi41vin4>;
+ remote-endpoint = <&csi41vin4>;
};
};
};
@@ -1579,11 +2137,11 @@
vin5csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin5>;
+ remote-endpoint = <&csi20vin5>;
};
vin5csi41: endpoint@3 {
reg = <3>;
- remote-endpoint= <&csi41vin5>;
+ remote-endpoint = <&csi41vin5>;
};
};
};
@@ -1611,11 +2169,11 @@
vin6csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin6>;
+ remote-endpoint = <&csi20vin6>;
};
vin6csi41: endpoint@3 {
reg = <3>;
- remote-endpoint= <&csi41vin6>;
+ remote-endpoint = <&csi41vin6>;
};
};
};
@@ -1643,11 +2201,11 @@
vin7csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin7>;
+ remote-endpoint = <&csi20vin7>;
};
vin7csi41: endpoint@3 {
reg = <3>;
- remote-endpoint= <&csi41vin7>;
+ remote-endpoint = <&csi41vin7>;
};
};
};
@@ -1967,20 +2525,6 @@
dma-names = "rx", "tx", "rxu", "txu";
};
};
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- };
- port@2 {
- reg = <2>;
- };
- };
};
audma0: dma-controller@ec700000 {
@@ -2067,6 +2611,65 @@
<&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
};
+ adsp: adsp@ec800000 {
+ compatible = "renesas,r8a7795-adsp",
+ "renesas,rcar-gen3-adsp";
+ reg = <0 0xec800000 0 0x80fc>,
+ <0 0xece60000 0 0x10000>,
+ <0 0xece78000 0 0x8000>,
+ <0 0xece80000 0 0x10000>,
+ <0 0xece90000 0 0x10000>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 506>,
+ <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&cpg CPG_MOD 501>, <&cpg CPG_MOD 502>,
+ <&cpg CPG_MOD 922>;
+ clock-names = "adsp",
+ "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "audmac.1", "audmac.0",
+ "adg";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 506>,
+ <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>,
+ <&cpg 501>, <&cpg 502>,
+ <&cpg 922>;
+ reset-names = "adsp",
+ "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "audmac.1", "audmac.0",
+ "adg";
+ status = "disabled";
+ };
+
xhci0: usb@ee000000 {
compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
reg = <0 0xee000000 0 0xc00>;
@@ -2092,11 +2695,11 @@
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 703>, <&cpg 704>;
status = "disabled";
};
@@ -2128,11 +2731,11 @@
compatible = "generic-ohci";
reg = <0 0xee0e0000 0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 700>;
+ clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
phys = <&usb2_phy3>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 700>;
+ resets = <&cpg 700>, <&cpg 705>;
status = "disabled";
};
@@ -2140,12 +2743,12 @@
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>;
phy-names = "usb";
companion = <&ohci0>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 703>, <&cpg 704>;
status = "disabled";
};
@@ -2179,12 +2782,12 @@
compatible = "generic-ehci";
reg = <0 0xee0e0100 0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 700>;
+ clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
phys = <&usb2_phy3>;
phy-names = "usb";
companion = <&ohci3>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 700>;
+ resets = <&cpg 700>, <&cpg 705>;
status = "disabled";
};
@@ -2193,9 +2796,9 @@
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 703>, <&cpg 704>;
#phy-cells = <0>;
status = "disabled";
};
@@ -2227,9 +2830,9 @@
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee0e0200 0 0x700>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 700>;
+ clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 700>;
+ resets = <&cpg 700>, <&cpg 705>;
#phy-cells = <0>;
status = "disabled";
};
@@ -2291,7 +2894,6 @@
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 815>;
status = "disabled";
- iommus = <&ipmmu_hc 2>;
};
gic: interrupt-controller@f1010000 {
@@ -2305,10 +2907,20 @@
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
+ };
+
+ gsx: gsx@fd000000 {
+ compatible = "renesas,gsx";
+ reg = <0 0xfd000000 0 0x40000>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 112>;
+ operating-points-v2 = <&gsx_opp0>, <&gsx_opp1>,
+ <&gsx_opp2>, <&gsx_opp3>,
+ <&gsx_opp4>, <&gsx_opp5>,
+ <&gsx_opp6>, <&gsx_opp7>;
+ power-domains = <&sysc R8A7795_PD_3DG_E>;
+ resets = <&cpg 112>;
};
pciec0: pcie@fe000000 {
@@ -2405,78 +3017,74 @@
resets = <&cpg 820>;
};
- fdp1@fe940000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe940000 0 0x2400>;
+ fcpcs: vcp4@fe90f000 {
+ compatible = "renesas,vcp4-fcpcs";
+ reg = <0 0xfe90f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 619>;
+ power-domains = <&sysc R8A7795_PD_A3VC>;
+ resets = <&cpg 619>;
+ renesas,#ch = <0>;
+ };
+
+ ivdp1c: vcp4@fe8d0000 {
+ compatible = "renesas,vcp4-ivdp1c";
+ reg = <0 0xfe8d0000 0 0x200>, <0 0xfe8d0200 0 0x200>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 128>;
+ power-domains = <&sysc R8A7795_PD_A2VC0>;
+ resets = <&cpg 128>;
+ renesas,#ch = <2>;
+ renesas,#fcp_ch = <0>;
+ };
+
+ vcplf: vcp4@fe910000 {
+ compatible = "renesas,vcp4-vcplf";
+ reg = <0 0xfe910000 0 0x200>, <0 0xfe910200 0 0x200>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 130>;
+ power-domains = <&sysc R8A7795_PD_A2VC1>;
+ resets = <&cpg 130>;
+ renesas,#ch = <0>;
+ renesas,#fcp_ch = <0>;
+ };
+
+ vdpb: vcp4@fe900000 {
+ compatible = "renesas,vcp4-vdpb";
+ reg = <0 0xfe900000 0 0x200>, <0 0xfe900200 0 0x200>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A7795_PD_A2VC1>;
+ resets = <&cpg 131>;
+ renesas,#ch = <1>;
+ renesas,#fcp_ch = <0>;
+ };
+
+ fdp0: fdpm@fe940000 {
+ compatible = "renesas,fdpm";
+ reg = <0 0xfe940000 0 0x2400>, <0 0xfe950000 0 0x200>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 119>;
+ clocks = <&cpg CPG_MOD 119>, <&cpg CPG_MOD 615>;
+ clock-names = "fdp", "fcp";
power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 119>;
- renesas,fcp = <&fcpf0>;
+ resets = <&cpg 119>, <&cpg 615>;
+ reset-names = "fdp", "fcp";
+ renesas,#ch = <0>;
};
- fdp1@fe944000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe944000 0 0x2400>;
+ fdp1: fdpm@fe944000 {
+ compatible = "renesas,fdpm";
+ reg = <0 0xfe944000 0 0x2400>, <0 0xfe951000 0 0x200>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 118>;
+ clocks = <&cpg CPG_MOD 118>, <&cpg CPG_MOD 614>;
+ clock-names = "fdp", "fcp";
power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 118>;
- renesas,fcp = <&fcpf1>;
- };
-
- fcpf0: fcp@fe950000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe950000 0 0x200>;
- clocks = <&cpg CPG_MOD 615>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 615>;
- iommus = <&ipmmu_vp0 0>;
- };
-
- fcpf1: fcp@fe951000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe951000 0 0x200>;
- clocks = <&cpg CPG_MOD 614>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 614>;
- iommus = <&ipmmu_vp1 1>;
- };
-
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 607>;
- iommus = <&ipmmu_vp0 5>;
- };
-
- fcpvb1: fcp@fe92f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe92f000 0 0x200>;
- clocks = <&cpg CPG_MOD 606>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 606>;
- iommus = <&ipmmu_vp1 7>;
- };
-
- fcpvi0: fcp@fe9af000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9af000 0 0x200>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 611>;
- iommus = <&ipmmu_vp0 8>;
- };
-
- fcpvi1: fcp@fe9bf000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9bf000 0 0x200>;
- clocks = <&cpg CPG_MOD 610>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 610>;
- iommus = <&ipmmu_vp1 9>;
+ resets = <&cpg 118>, <&cpg 614>;
+ reset-names = "fdp", "fcp";
+ renesas,#ch = <1>;
};
fcpvd0: fcp@fea27000 {
@@ -2485,7 +3093,6 @@
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 603>;
- iommus = <&ipmmu_vi0 8>;
};
fcpvd1: fcp@fea2f000 {
@@ -2494,7 +3101,6 @@
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 602>;
- iommus = <&ipmmu_vi0 9>;
};
fcpvd2: fcp@fea37000 {
@@ -2503,45 +3109,87 @@
clocks = <&cpg CPG_MOD 601>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 601>;
- iommus = <&ipmmu_vi1 10>;
};
- vspbd: vsp@fe960000 {
- compatible = "renesas,vsp2";
+ vsp@fe960000 {
+ compatible = "renesas,vspm-vsp2";
reg = <0 0xfe960000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 626>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 626>;
-
- renesas,fcp = <&fcpvb0>;
+ renesas,has-bru;
+ renesas,#rpf = <5>;
+ renesas,#uds = <0>;
+ renesas,#wpf = <1>;
};
- vspbc: vsp@fe920000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe920000 0 0x8000>;
- interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 624>;
+ vspbd: vspm@fe960000 {
+ compatible = "renesas,vspm";
+ reg = <0 0xfe960000 0 0x8000>, <0 0xfe96f000 0 0x200>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 626>, <&cpg CPG_MOD 607>;
+ clock-names = "vsp", "fcp";
+ renesas,#ch = <3>;
+ renesas,#rpf = <31>;
+ renesas,#rpf_clut = <6>;
+ renesas,#wpf_rot = <0>;
+ renesas,has-bru;
+ renesas,#read_outstanding = <0>;
+ renesas,#start_reservation = <2>;
+ renesas,#burst_access = <0>;
power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 624>;
+ resets = <&cpg 626>, <&cpg 607>;
+ reset-names = "vsp", "fcp";
+ status = "disabled";
+ };
- renesas,fcp = <&fcpvb1>;
+ vsp@fe920000 {
+ compatible = "renesas,vspm-vsp2";
+ reg = <0 0xfe920000 0 0x8000>;
+ renesas,has-bru;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hgo;
+ renesas,#rpf = <5>;
+ renesas,#uds = <0>;
+ renesas,#wpf = <1>;
+ };
+
+ vspbc: vspm@fe920000 {
+ compatible = "renesas,vspm";
+ reg = <0 0xfe920000 0 0x8000>, <0 0xfe92f000 0 0x200>;
+ interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 624>, <&cpg CPG_MOD 606>;
+ clock-names = "vsp", "fcp";
+ renesas,#ch = <4>;
+ renesas,#rpf = <31>;
+ renesas,#rpf_clut = <6>;
+ renesas,#wpf_rot = <0>;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hgo;
+ renesas,has-bru;
+ renesas,#read_outstanding = <0>;
+ renesas,#start_reservation = <2>;
+ renesas,#burst_access = <1>;
+ power-domains = <&sysc R8A7795_PD_A3VP>;
+ resets = <&cpg 624>, <&cpg 606>;
+ reset-names = "vsp", "fcp";
+ status = "disabled";
};
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x8000>;
+ reg = <0 0xfea20000 0 0x5000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 623>;
+ renesas,#brs = <2>;
renesas,fcp = <&fcpvd0>;
};
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x8000>;
+ reg = <0 0xfea28000 0 0x5000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2552,7 +3200,7 @@
vspd2: vsp@fea30000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea30000 0 0x8000>;
+ reg = <0 0xfea30000 0 0x5000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -2561,26 +3209,82 @@
renesas,fcp = <&fcpvd2>;
};
- vspi0: vsp@fe9a0000 {
- compatible = "renesas,vsp2";
+ vsp@fe9a0000 {
+ compatible = "renesas,vspm-vsp2";
reg = <0 0xfe9a0000 0 0x8000>;
- interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 631>;
- power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 631>;
-
- renesas,fcp = <&fcpvi0>;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hgo;
+ renesas,has-hgt;
+ renesas,#rpf = <1>;
+ renesas,#uds = <1>;
+ renesas,#wpf = <1>;
};
- vspi1: vsp@fe9b0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9b0000 0 0x8000>;
- interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 630>;
+ vspi0: vspm@fe9a0000 {
+ compatible = "renesas,vspm";
+ reg = <0 0xfe9a0000 0 0x8000>, <0 0xfe9af000 0 0x200>;
+ interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 631>, <&cpg CPG_MOD 611>;
+ clock-names = "vsp", "fcp";
+ renesas,#ch = <0>;
+ renesas,#rpf = <1>;
+ renesas,#rpf_clut = <1>;
+ renesas,#wpf_rot = <1>;
+ renesas,has-sru;
+ renesas,has-uds;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hst;
+ renesas,has-hsi;
+ renesas,has-hgo;
+ renesas,has-hgt;
+ renesas,has-shp;
+ renesas,#read_outstanding = <2>;
+ renesas,#start_reservation = <2>;
power-domains = <&sysc R8A7795_PD_A3VP>;
- resets = <&cpg 630>;
+ resets = <&cpg 631>, <&cpg 611>;
+ reset-names = "vsp", "fcp";
+ status = "disabled";
+ };
- renesas,fcp = <&fcpvi1>;
+ vsp@fe9b0000 {
+ compatible = "renesas,vspm-vsp2";
+ reg = <0 0xfe9b0000 0 0x8000>;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hgo;
+ renesas,has-hgt;
+ renesas,#rpf = <1>;
+ renesas,#uds = <1>;
+ renesas,#wpf = <1>;
+ };
+
+ vspi1: vspm@fe9b0000 {
+ compatible = "renesas,vspm";
+ reg = <0 0xfe9b0000 0 0x8000>, <0 0xfe9bf000 0 0x200>;
+ interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 630>, <&cpg CPG_MOD 610>;
+ clock-names = "vsp", "fcp";
+ renesas,#ch = <1>;
+ renesas,#rpf = <1>;
+ renesas,#rpf_clut = <1>;
+ renesas,#wpf_rot = <1>;
+ renesas,has-sru;
+ renesas,has-uds;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hst;
+ renesas,has-hsi;
+ renesas,has-hgo;
+ renesas,has-hgt;
+ renesas,has-shp;
+ renesas,#read_outstanding = <2>;
+ renesas,#start_reservation = <2>;
+ power-domains = <&sysc R8A7795_PD_A3VP>;
+ resets = <&cpg 630>, <&cpg 610>;
+ reset-names = "vsp", "fcp";
+ status = "disabled";
};
csi20: csi2@fea80000 {
@@ -2776,9 +3480,7 @@
du: display@feb00000 {
compatible = "renesas,du-r8a7795";
- reg = <0 0xfeb00000 0 0x80000>,
- <0 0xfeb90000 0 0x14>;
- reg-names = "du", "lvds.0";
+ reg = <0 0xfeb00000 0 0x80000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
@@ -2786,9 +3488,13 @@
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
- <&cpg CPG_MOD 721>,
- <&cpg CPG_MOD 727>;
- clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+ <&cpg CPG_MOD 721>;
+ clock-names = "du.0", "du.1", "du.2", "du.3";
+ resets = <&cpg 724>,
+ <&cpg 724>,
+ <&cpg 722>,
+ <&cpg 722>;
+ reset-names = "du.0", "du.1", "du.2", "du.3";
vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
status = "disabled";
@@ -2816,6 +3522,33 @@
port@3 {
reg = <3>;
du_out_lvds0: endpoint {
+ remote-endpoint = <&lvds0_in>;
+ };
+ };
+ };
+ };
+
+ lvds0: lvds@feb90000 {
+ compatible = "renesas,r8a7795-lvds";
+ reg = <0 0xfeb90000 0 0x14>;
+ clocks = <&cpg CPG_MOD 727>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 727>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
};
};
};
@@ -2828,69 +3561,68 @@
};
thermal-zones {
+ emergency {
+ polling-delay = <1000>;
+ on-temperature = <110000>;
+ off-temperature = <95000>;
+ target_cpus = <&a57_1>,
+ <&a57_2>,
+ <&a57_3>,
+ <&a53_0>,
+ <&a53_1>,
+ <&a53_2>,
+ <&a53_3>;
+ status = "disabled";
+ };
+
sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+ polling-delay = <0>;
thermal-sensors = <&tsc 0>;
+ sustainable-power = <6313>;
trips {
- sensor1_passive: sensor1-passive {
- temperature = <95000>;
- hysteresis = <1000>;
- type = "passive";
- };
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&sensor1_passive>;
- cooling-device = <&a57_0 4 4>;
- };
- };
};
sensor_thermal2: sensor-thermal2 {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+ polling-delay = <0>;
thermal-sensors = <&tsc 1>;
+ sustainable-power = <6313>;
trips {
- sensor2_passive: sensor2-passive {
- temperature = <95000>;
- hysteresis = <1000>;
- type = "passive";
- };
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&sensor2_passive>;
- cooling-device = <&a57_0 4 4>;
- };
- };
};
sensor_thermal3: sensor-thermal3 {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+ polling-delay = <0>;
thermal-sensors = <&tsc 2>;
trips {
- sensor3_passive: sensor3-passive {
- temperature = <95000>;
+ threshold: trip-point0 {
+ temperature = <90000>;
hysteresis = <1000>;
type = "passive";
};
+
+ target: trip-point1 {
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <1000>;
@@ -2900,8 +3632,15 @@
cooling-maps {
map0 {
- trip = <&sensor3_passive>;
- cooling-device = <&a57_0 4 4>;
+ trip = <&target>;
+ cooling-device = <&a57_0 0 2>;
+ contribution = <1024>;
+ };
+
+ map1 {
+ trip = <&target>;
+ cooling-device = <&a53_0 0 2>;
+ contribution = <1024>;
};
};
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts
index de2390f..2df50eb 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3ULCB Kingfisher board
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include "r8a7796-m3ulcb.dts"
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index daee1f1..c962301 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board
*
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2018 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
/dts-v1/;
@@ -17,6 +14,12 @@
model = "Renesas M3ULCB board based on r8a7796";
compatible = "renesas,m3ulcb", "renesas,r8a7796";
+ cpus {
+ idle-states {
+ /delete-node/ cpu-sleep-1;
+ };
+ };
+
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
@@ -27,16 +30,86 @@
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x40000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress@54000000 {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma@57000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x19000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia@70000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x70000000 0x0 0x10000000>;
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+
+ versaclock5_out3: versaclk-3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* Initial value of versaclock out3 */
+ clock-frequency = <33000000>;
+ };
+};
+
+&a53_0 {
+ /delete-property/ cpu-idle-states;
+};
+
+&a53_1 {
+ /delete-property/ cpu-idle-states;
+};
+
+&a53_2 {
+ /delete-property/ cpu-idle-states;
+};
+
+&a53_3 {
+ /delete-property/ cpu-idle-states;
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
- <&cpg CPG_MOD 727>,
<&versaclock5 1>,
- <&versaclock5 3>,
+ <&versaclock5_out3>,
<&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.2", "lvds.0",
+ clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
+
+&vspb {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index 90cca09..02a938b 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X board with R-Car M3-W
*
* Copyright (C) 2016 Renesas Electronics Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
/dts-v1/;
@@ -26,17 +23,68 @@
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress@54000000 {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+
+ /* For Audio DSP */
+ adsp_reserved: linux,adsp@57000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x01000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x58000000 0x0 0x18000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia@70000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x70000000 0x0 0x10000000>;
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+};
+
+&adsp {
+ status = "okay";
+ memory-region = <&adsp_reserved>;
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
- <&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&x21_clk>,
<&versaclock5 2>;
- clock-names = "du.0", "du.1", "du.2", "lvds.0",
+ clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
@@ -68,6 +116,16 @@
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
+&lvds0 {
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+ };
+};
+
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
@@ -84,3 +142,11 @@
};
};
};
+
+&vspb {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs-2x4g.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs-2x4g.dts
new file mode 100644
index 0000000..ceacc90
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs-2x4g.dts
@@ -0,0 +1,32 @@
+/*
+ * Device Tree Source for the Salvator-X 2nd version board with R-Car M3 ES3.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "r8a7796-salvator-xs.dts"
+
+/ {
+ model = "Renesas Salvator-X 2nd version board based on r8a7796 ES3.0+ with 8GiB (2 x 4 GiB)";
+ compatible = "renesas,salvator-xs", "renesas,r8a7796";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ memory@400000000 {
+ device_type = "memory";
+ reg = <0x4 0x80000000 0x0 0x80000000>;
+ };
+
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x1 0x00000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
index ddf35d4..bd66be1 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X 2nd version board with R-Car M3-W
*
* Copyright (C) 2015-2017 Renesas Electronics Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
/dts-v1/;
@@ -26,17 +23,68 @@
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress@54000000 {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+
+ /* For Audio DSP */
+ adsp_reserved: linux,adsp@57000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x01000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x58000000 0x0 0x18000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia@70000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x70000000 0x0 0x10000000>;
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+};
+
+&adsp {
+ status = "okay";
+ memory-region = <&adsp_reserved>;
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
- <&cpg CPG_MOD 727>,
<&versaclock6 1>,
<&x21_clk>,
<&versaclock6 2>;
- clock-names = "du.0", "du.1", "du.2", "lvds.0",
+ clock-names = "du.0", "du.1", "du.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
@@ -68,6 +116,16 @@
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
+&lvds0 {
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+ };
+};
+
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
@@ -84,3 +142,11 @@
};
};
};
+
+&vspb {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 7c25be6..c00d1da 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the r8a7796 SoC
+ * Device Tree Source for the R-Car M3-W (R8A77960) SoC
*
- * Copyright (C) 2016 Renesas Electronics Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
@@ -28,6 +25,10 @@
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
+ spi0 = &msiof0;
+ spi1 = &msiof1;
+ spi2 = &msiof2;
+ spi3 = &msiof3;
};
/*
@@ -60,24 +61,25 @@
clock-frequency = <0>;
};
- cluster0_opp: opp_table0 {
+ cluster0_opp0: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
+ opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
@@ -99,7 +101,288 @@
};
};
- cluster1_opp: opp_table1 {
+ cluster0_opp1: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <890000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <890000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster0_opp2: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <810000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <810000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <810000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <880000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <880000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <930000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster0_opp3: opp_table3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <870000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <870000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <910000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster0_opp4: opp_table4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <790000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <790000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <790000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <860000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <860000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <890000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster0_opp5: opp_table5 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <780000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <780000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <780000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <850000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <850000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <880000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster0_opp6: opp_table6 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <770000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <770000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <770000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <870000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster0_opp7: opp_table7 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <760000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <760000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <760000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <860000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+
+ };
+
+ cluster1_opp: opp_table10 {
compatible = "operating-points-v2";
opp-shared;
@@ -117,6 +400,7 @@
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
+ opp-suspend;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
@@ -130,6 +414,32 @@
#address-cells = <1>;
#size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&a57_0>;
+ };
+ core1 {
+ cpu = <&a57_1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&a53_0>;
+ };
+ core1 {
+ cpu = <&a53_1>;
+ };
+ core2 {
+ cpu = <&a53_2>;
+ };
+ core3 {
+ cpu = <&a53_3>;
+ };
+ };
+ };
+
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>;
@@ -137,9 +447,18 @@
power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
+ dynamic-power-coefficient = <854>;
+ cooling-min-level = <0>;
+ cooling-max-level = <2>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp0>,
+ <&cluster0_opp1>, <&cluster0_opp2>,
+ <&cluster0_opp3>, <&cluster0_opp4>,
+ <&cluster0_opp5>, <&cluster0_opp6>,
+ <&cluster0_opp7>;
#cooling-cells = <2>;
+ capacity-dmips-mhz = <1024>;
};
a57_1: cpu@1 {
@@ -149,9 +468,15 @@
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
- operating-points-v2 = <&cluster0_opp>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp0>,
+ <&cluster0_opp1>, <&cluster0_opp2>,
+ <&cluster0_opp3>, <&cluster0_opp4>,
+ <&cluster0_opp5>, <&cluster0_opp6>,
+ <&cluster0_opp7>;
#cooling-cells = <2>;
+ capacity-dmips-mhz = <1024>;
};
a53_0: cpu@100 {
@@ -161,8 +486,14 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <277>;
+ cooling-min-level = <0>;
+ cooling-max-level = <2>;
+ cpu-idle-states = <&CPU_SLEEP_1>;
+ clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <543>;
};
a53_1: cpu@101 {
@@ -172,8 +503,10 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ cpu-idle-states = <&CPU_SLEEP_1>;
+ clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <543>;
};
a53_2: cpu@102 {
@@ -183,8 +516,10 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ cpu-idle-states = <&CPU_SLEEP_1>;
+ clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <543>;
};
a53_3: cpu@103 {
@@ -194,8 +529,10 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
- clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ cpu-idle-states = <&CPU_SLEEP_1>;
+ clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
+ capacity-dmips-mhz = <543>;
};
L2_CA57: cache-controller-0 {
@@ -211,6 +548,30 @@
cache-unified;
cache-level = <2>;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <400>;
+ exit-latency-us = <500>;
+ min-residency-us = <4000>;
+ status = "okay";
+ };
+
+ CPU_SLEEP_1: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <700>;
+ exit-latency-us = <700>;
+ min-residency-us = <5000>;
+ status = "okay";
+ };
+ };
};
extal_clk: extal {
@@ -227,6 +588,188 @@
clock-frequency = <0>;
};
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ gsx_opp0: gsx_opp_table0 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <830000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <830000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <830000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <830000>;
+ };
+ };
+
+ gsx_opp1: gsx_opp_table1 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <820000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <820000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <820000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <820000>;
+ };
+ };
+
+ gsx_opp2: gsx_opp_table2 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <810000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <810000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <810000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <810000>;
+ };
+ };
+
+ gsx_opp3: gsx_opp_table3 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ };
+ };
+
+ gsx_opp4: gsx_opp_table4 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <790000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <790000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <790000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <790000>;
+ };
+ };
+
+ gsx_opp5: gsx_opp_table5 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <780000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <780000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <780000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <780000>;
+ };
+ };
+
+ gsx_opp6: gsx_opp_table6 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <770000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <770000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <770000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <770000>;
+ };
+ };
+
+ gsx_opp7: gsx_opp_table7 {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <760000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <760000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <760000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <760000>;
+ };
+ };
+
+ /* MSIOF reference clock - to be overridden by boards that provide it */
+ msiof_ref_clk: msiof-ref-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
@@ -269,7 +812,22 @@
#size-cells = <2>;
ranges;
- wdt0: watchdog@e6020000 {
+ mfis: mfis@e6260000 {
+ compatible = "renesas,mfis-lock-r8a7796",
+ "renesas,mfis-lock";
+ reg = <0 0xe6260000 0 0x1000>;
+ #hwlock-cells = <1>;
+
+ mfis_as: mfis-as {
+ compatible = "renesas,mfis-as-r8a7796",
+ "renesas,mfis-as";
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eicr0";
+ renesas,mfis-ch = <0>;
+ };
+ };
+
+ rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7796-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
@@ -404,6 +962,12 @@
reg = <0 0xe6060000 0 0x50c>;
};
+ avs: avs@e60a013c {
+ compatible = "renesas,r8a7796-avs", "renesas,rcar-gen3-avs";
+ reg = <0 0xe60a013c 0 0x04>;
+ target_devices = <&a57_0>, <&a57_1>, <&gsx>;
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7796-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@@ -451,9 +1015,7 @@
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
};
i2c0: i2c@e6500000 {
@@ -678,9 +1240,9 @@
hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7796",
"renesas,rcar-gen3-usbhs";
- reg = <0 0xe6590000 0 0x100>;
+ reg = <0 0xe6590000 0 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>;
+ clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
@@ -688,7 +1250,7 @@
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
+ resets = <&cpg 704>, <&cpg 703>;
status = "disabled";
};
@@ -859,12 +1421,23 @@
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
};
+ ipmmu_mm: mmu@e67b0000 {
+ compatible = "renesas,ipmmu-r8a7796";
+ reg = <0 0xe67b0000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
ipmmu_ds0: mmu@e6740000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_ds1: mmu@e7740000 {
@@ -873,6 +1446,7 @@
renesas,ipmmu-main = <&ipmmu_mm 1>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_hc: mmu@e6570000 {
@@ -881,6 +1455,7 @@
renesas,ipmmu-main = <&ipmmu_mm 2>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_ir: mmu@ff8b0000 {
@@ -889,15 +1464,7 @@
renesas,ipmmu-main = <&ipmmu_mm 3>;
power-domains = <&sysc R8A7796_PD_A3IR>;
#iommu-cells = <1>;
- };
-
- ipmmu_mm: mmu@e67b0000 {
- compatible = "renesas,ipmmu-r8a7796";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_mp: mmu@ec670000 {
@@ -906,6 +1473,7 @@
renesas,ipmmu-main = <&ipmmu_mm 4>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_pv0: mmu@fd800000 {
@@ -914,6 +1482,7 @@
renesas,ipmmu-main = <&ipmmu_mm 5>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_pv1: mmu@fd950000 {
@@ -922,6 +1491,7 @@
renesas,ipmmu-main = <&ipmmu_mm 6>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_rt: mmu@ffc80000 {
@@ -930,14 +1500,16 @@
renesas,ipmmu-main = <&ipmmu_mm 7>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_vc0: mmu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a7796";
+ compatible = "renesas,ipmmu-mmu-r8a7796";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
power-domains = <&sysc R8A7796_PD_A3VC>;
#iommu-cells = <1>;
+ status = "disabled";
};
ipmmu_vi0: mmu@febd0000 {
@@ -946,6 +1518,12 @@
renesas,ipmmu-main = <&ipmmu_mm 9>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ qos@e67e0000 {
+ compatible = "renesas,qos";
+ reg = <0 0xe67e0000 0 0x10090>;
};
avb: ethernet@e6800000 {
@@ -988,7 +1566,6 @@
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
- iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1223,7 +1800,8 @@
"renesas,rcar-gen3-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
+ clocks = <&cpg CPG_MOD 211>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
dma-names = "tx", "rx", "tx", "rx";
@@ -1239,7 +1817,8 @@
"renesas,rcar-gen3-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
+ clocks = <&cpg CPG_MOD 210>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
@@ -1255,7 +1834,8 @@
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
+ clocks = <&cpg CPG_MOD 209>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1270,7 +1850,8 @@
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
+ clocks = <&cpg CPG_MOD 208>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1302,11 +1883,11 @@
vin0csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin0>;
+ remote-endpoint = <&csi20vin0>;
};
vin0csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin0>;
+ remote-endpoint = <&csi40vin0>;
};
};
};
@@ -1334,11 +1915,11 @@
vin1csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin1>;
+ remote-endpoint = <&csi20vin1>;
};
vin1csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin1>;
+ remote-endpoint = <&csi40vin1>;
};
};
};
@@ -1366,11 +1947,11 @@
vin2csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin2>;
+ remote-endpoint = <&csi20vin2>;
};
vin2csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin2>;
+ remote-endpoint = <&csi40vin2>;
};
};
};
@@ -1398,11 +1979,11 @@
vin3csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin3>;
+ remote-endpoint = <&csi20vin3>;
};
vin3csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin3>;
+ remote-endpoint = <&csi40vin3>;
};
};
};
@@ -1430,11 +2011,11 @@
vin4csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin4>;
+ remote-endpoint = <&csi20vin4>;
};
vin4csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin4>;
+ remote-endpoint = <&csi40vin4>;
};
};
};
@@ -1462,11 +2043,11 @@
vin5csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin5>;
+ remote-endpoint = <&csi20vin5>;
};
vin5csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin5>;
+ remote-endpoint = <&csi40vin5>;
};
};
};
@@ -1494,11 +2075,11 @@
vin6csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin6>;
+ remote-endpoint = <&csi20vin6>;
};
vin6csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin6>;
+ remote-endpoint = <&csi40vin6>;
};
};
};
@@ -1526,11 +2107,11 @@
vin7csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin7>;
+ remote-endpoint = <&csi20vin7>;
};
vin7csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin7>;
+ remote-endpoint = <&csi40vin7>;
};
};
};
@@ -1947,6 +2528,64 @@
<&ipmmu_mp 30>, <&ipmmu_mp 31>;
};
+ adsp: adsp@ec800000 {
+ compatible = "renesas,r8a7796-adsp", "renesas,rcar-gen3-adsp";
+ reg = <0 0xec800000 0 0x80fc>,
+ <0 0xece60000 0 0x10000>,
+ <0 0xece78000 0 0x8000>,
+ <0 0xece80000 0 0x10000>,
+ <0 0xece90000 0 0x10000>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 506>,
+ <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&cpg CPG_MOD 501>, <&cpg CPG_MOD 502>,
+ <&cpg CPG_MOD 922>;
+ clock-names = "adsp",
+ "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "audmac.1", "audmac.0",
+ "adg";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 506>,
+ <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>,
+ <&cpg 501>, <&cpg 502>,
+ <&cpg 922>;
+ reset-names = "adsp",
+ "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "audmac.1", "audmac.0",
+ "adg";
+ status = "disabled";
+ };
+
xhci0: usb@ee000000 {
compatible = "renesas,xhci-r8a7796",
"renesas,rcar-gen3-xhci";
@@ -1973,11 +2612,11 @@
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 703>, <&cpg 704>;
status = "disabled";
};
@@ -1997,12 +2636,12 @@
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>;
phy-names = "usb";
- companion= <&ohci0>;
+ companion = <&ohci0>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 703>, <&cpg 704>;
status = "disabled";
};
@@ -2013,7 +2652,7 @@
clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
- companion= <&ohci1>;
+ companion = <&ohci1>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
@@ -2024,9 +2663,9 @@
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 703>, <&cpg 704>;
#phy-cells = <0>;
status = "disabled";
};
@@ -2101,20 +2740,74 @@
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
+ };
+
+ gsx: gsx@fd000000 {
+ compatible = "renesas,gsx";
+ reg = <0 0xfd000000 0 0x40000>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 112>;
+ operating-points-v2 = <&gsx_opp0>, <&gsx_opp1>,
+ <&gsx_opp2>, <&gsx_opp3>,
+ <&gsx_opp4>, <&gsx_opp5>,
+ <&gsx_opp6>, <&gsx_opp7>;
+ power-domains = <&sysc R8A7796_PD_3DG_B>;
+ resets = <&cpg 112>;
};
pciec0: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a7796",
+ "renesas,pcie-rcar-gen3";
reg = <0 0xfe000000 0 0x80000>;
- /* placeholder */
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
};
pciec1: pcie@ee800000 {
+ compatible = "renesas,pcie-r8a7796",
+ "renesas,pcie-rcar-gen3";
reg = <0 0xee800000 0 0x80000>;
- /* placeholder */
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
+ 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
+ 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
+ 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
};
imr-lx4@fe860000 {
@@ -2137,39 +2830,71 @@
resets = <&cpg 822>;
};
- fdp1@fe940000 {
- compatible = "renesas,fdp1";
- reg = <0 0xfe940000 0 0x2400>;
+ fcpci0: vcp4@fe8df000 {
+ compatible = "renesas,vcp4-fcpci0";
+ reg = <0 0xfe8df000 0 0x200>;
+ clocks = <&cpg CPG_MOD 617>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 617>;
+ renesas,#ch = <1>;
+ };
+
+ fcpcs: vcp4@fe90f000 {
+ compatible = "renesas,vcp4-fcpcs";
+ reg = <0 0xfe90f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 619>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 619>;
+ renesas,#ch = <0>;
+ };
+
+ ivdp1c: vcp4@fe8d0000 {
+ compatible = "renesas,vcp4-ivdp1c";
+ reg = <0 0xfe8d0000 0 0x200>, <0 0xfe8d0200 0 0x200>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 128>;
+ power-domains = <&sysc R8A7796_PD_A2VC0>;
+ resets = <&cpg 128>;
+ renesas,#ch = <2>;
+ renesas,#fcp_ch = <1>;
+ };
+
+ vcplf: vcp4@fe910000 {
+ compatible = "renesas,vcp4-vcplf";
+ reg = <0 0xfe910000 0 0x200>, <0 0xfe910200 0 0x200>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 130>;
+ power-domains = <&sysc R8A7796_PD_A2VC1>;
+ resets = <&cpg 130>;
+ renesas,#ch = <0>;
+ renesas,#fcp_ch = <0>;
+ };
+
+ vdpb: vcp4@fe900000 {
+ compatible = "renesas,vcp4-vdpb";
+ reg = <0 0xfe900000 0 0x200>, <0 0xfe900200 0 0x200>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A7796_PD_A2VC0>;
+ resets = <&cpg 131>;
+ renesas,#ch = <1>;
+ renesas,#fcp_ch = <0>;
+ };
+
+ fdp0: fdpm@fe940000 {
+ compatible = "renesas,fdpm";
+ reg = <0 0xfe940000 0 0x2400>, <0 0xfe950000 0 0x200>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 119>;
+ clocks = <&cpg CPG_MOD 119>, <&cpg CPG_MOD 615>;
+ clock-names = "fdp", "fcp";
power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 119>;
- renesas,fcp = <&fcpf0>;
- };
-
- fcpf0: fcp@fe950000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe950000 0 0x200>;
- clocks = <&cpg CPG_MOD 615>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 615>;
- };
-
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 607>;
- };
-
- fcpvi0: fcp@fe9af000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9af000 0 0x200>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 611>;
- iommus = <&ipmmu_vc0 19>;
+ resets = <&cpg 119>, <&cpg 615>;
+ reset-names = "fdp", "fcp";
+ renesas,#ch = <0>;
};
fcpvd0: fcp@fea27000 {
@@ -2178,7 +2903,6 @@
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 603>;
- iommus = <&ipmmu_vi0 8>;
};
fcpvd1: fcp@fea2f000 {
@@ -2187,7 +2911,6 @@
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 602>;
- iommus = <&ipmmu_vi0 9>;
};
fcpvd2: fcp@fea37000 {
@@ -2196,23 +2919,45 @@
clocks = <&cpg CPG_MOD 601>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 601>;
- iommus = <&ipmmu_vi0 10>;
};
- vspb: vsp@fe960000 {
- compatible = "renesas,vsp2";
+ vsp@fe960000 {
+ compatible = "renesas,vspm-vsp2";
reg = <0 0xfe960000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 626>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 626>;
+ renesas,has-bru;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hgo;
+ renesas,#rpf = <5>;
+ renesas,#uds = <0>;
+ renesas,#wpf = <1>;
+ };
- renesas,fcp = <&fcpvb0>;
+ vspb: vspm@fe960000 {
+ compatible = "renesas,vspm";
+ reg = <0 0xfe960000 0 0x8000>, <0 0xfe96f000 0 0x200>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 626>, <&cpg CPG_MOD 607>;
+ clock-names = "vsp", "fcp";
+ renesas,#ch = <3>;
+ renesas,#rpf = <31>;
+ renesas,#rpf_clut = <6>;
+ renesas,#wpf_rot = <0>;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-bru;
+ renesas,has-hgo;
+ renesas,#read_outstanding = <0>;
+ renesas,#start_reservation = <1>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 626>, <&cpg 607>;
+ reset-names = "vsp", "fcp";
+ status = "disabled";
};
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x8000>;
+ reg = <0 0xfea20000 0 0x5000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -2223,7 +2968,7 @@
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x8000>;
+ reg = <0 0xfea28000 0 0x5000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -2234,7 +2979,7 @@
vspd2: vsp@fea30000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea30000 0 0x8000>;
+ reg = <0 0xfea30000 0 0x5000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -2243,15 +2988,43 @@
renesas,fcp = <&fcpvd2>;
};
- vspi0: vsp@fe9a0000 {
- compatible = "renesas,vsp2";
+ vsp@fe9a0000 {
+ compatible = "renesas,vspm-vsp2";
reg = <0 0xfe9a0000 0 0x8000>;
- interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 631>;
- power-domains = <&sysc R8A7796_PD_A3VC>;
- resets = <&cpg 631>;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hgo;
+ renesas,has-hgt;
+ renesas,#rpf = <1>;
+ renesas,#uds = <1>;
+ renesas,#wpf = <1>;
+ };
- renesas,fcp = <&fcpvi0>;
+ vspi0: vspm@fe9a0000 {
+ compatible = "renesas,vspm";
+ reg = <0 0xfe9a0000 0 0x8000>, <0 0xfe9af000 0 0x200>;
+ interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 631>, <&cpg CPG_MOD 611>;
+ clock-names = "vsp", "fcp";
+ renesas,#ch = <0>;
+ renesas,#rpf = <1>;
+ renesas,#rpf_clut = <1>;
+ renesas,#wpf_rot = <1>;
+ renesas,has-sru;
+ renesas,has-uds;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hst;
+ renesas,has-hsi;
+ renesas,has-hgo;
+ renesas,has-hgt;
+ renesas,has-shp;
+ renesas,#read_outstanding = <2>;
+ renesas,#start_reservation = <1>;
+ power-domains = <&sysc R8A7796_PD_A3VC>;
+ resets = <&cpg 631>, <&cpg 611>;
+ reset-names = "vsp", "fcp";
+ status = "disabled";
};
csi20: csi2@fea80000 {
@@ -2396,17 +3169,18 @@
du: display@feb00000 {
compatible = "renesas,du-r8a7796";
- reg = <0 0xfeb00000 0 0x70000>,
- <0 0xfeb90000 0 0x14>;
- reg-names = "du", "lvds.0";
+ reg = <0 0xfeb00000 0 0x70000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>,
- <&cpg CPG_MOD 727>;
- clock-names = "du.0", "du.1", "du.2", "lvds.0";
+ <&cpg CPG_MOD 722>;
+ clock-names = "du.0", "du.1", "du.2";
+ resets = <&cpg 724>,
+ <&cpg 724>,
+ <&cpg 722>;
+ reset-names = "du.0", "du.1", "du.2";
status = "disabled";
vsps = <&vspd0 &vspd1 &vspd2>;
@@ -2429,6 +3203,33 @@
port@2 {
reg = <2>;
du_out_lvds0: endpoint {
+ remote-endpoint = <&lvds0_in>;
+ };
+ };
+ };
+ };
+
+ lvds0: lvds@feb90000 {
+ compatible = "renesas,r8a7796-lvds";
+ reg = <0 0xfeb90000 0 0x14>;
+ clocks = <&cpg CPG_MOD 727>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 727>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
};
};
};
@@ -2441,80 +3242,83 @@
};
thermal-zones {
+ emergency {
+ polling-delay = <1000>;
+ on-temperature = <110000>;
+ off-temperature = <95000>;
+ target_cpus = <&a57_1>,
+ <&a53_0>,
+ <&a53_1>,
+ <&a53_2>,
+ <&a53_3>;
+ status = "disabled";
+ };
+
sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+ polling-delay = <0>;
thermal-sensors = <&tsc 0>;
+ sustainable-power = <3874>;
trips {
- sensor1_passive: sensor1-passive {
- temperature = <95000>;
- hysteresis = <1000>;
- type = "passive";
- };
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&sensor1_passive>;
- cooling-device = <&a57_0 5 5>;
- };
- };
};
sensor_thermal2: sensor-thermal2 {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+ polling-delay = <0>;
thermal-sensors = <&tsc 1>;
+ sustainable-power = <3874>;
trips {
- sensor2_passive: sensor2-passive {
- temperature = <95000>;
- hysteresis = <1000>;
- type = "passive";
- };
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
-
- cooling-maps {
- map0 {
- trip = <&sensor2_passive>;
- cooling-device = <&a57_0 5 5>;
- };
- };
};
sensor_thermal3: sensor-thermal3 {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+ polling-delay = <0>;
thermal-sensors = <&tsc 2>;
+ sustainable-power = <3874>;
trips {
- sensor3_passive: sensor3-passive {
- temperature = <95000>;
+ threshold: trip-point0 {
+ temperature = <90000>;
hysteresis = <1000>;
type = "passive";
};
+
+ target: trip-point1 {
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
-
cooling-maps {
map0 {
- trip = <&sensor3_passive>;
- cooling-device = <&a57_0 5 5>;
+ trip = <&target>;
+ cooling-device = <&a57_0 0 2>;
+ contribution = <1024>;
+ };
+ map1 {
+ trip = <&target>;
+ cooling-device = <&a53_0 0 2>;
+ contribution = <1024>;
};
};
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
index 340a3c7..d9fb0df 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
@@ -18,6 +18,58 @@
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress@54000000 {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+
+ /* For Audio DSP */
+ adsp_reserved: linux,adsp@57000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x01000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x58000000 0x0 0x18000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia@70000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x70000000 0x0 0x10000000>;
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+};
+
+&adsp {
+ status = "okay";
+ memory-region = <&adsp_reserved>;
};
&du {
@@ -47,3 +99,21 @@
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
+
+&lvds0 {
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+ };
+};
+
+&vspb {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
index 9de4e3d..d645612 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
@@ -18,6 +18,58 @@
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress@54000000 {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+
+ /* For Audio DSP */
+ adsp_reserved: linux,adsp@57000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x01000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x58000000 0x0 0x18000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia@70000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x70000000 0x0 0x10000000>;
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+};
+
+&adsp {
+ status = "okay";
+ memory-region = <&adsp_reserved>;
};
&du {
@@ -47,3 +99,21 @@
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
+
+&lvds0 {
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+ };
+};
+
+&vspb {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 486aeca..454a67b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the r8a77965 SoC
+ * Device Tree Source for the R-Car M3-N (R8A77965) SoC
*
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
*
@@ -12,7 +12,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77965-sysc.h>
-#define CPG_AUDIO_CLK_I 10
+#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4
/ {
compatible = "renesas,r8a77965";
@@ -28,6 +28,10 @@
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
+ spi0 = &msiof0;
+ spi1 = &msiof1;
+ spi2 = &msiof2;
+ spi3 = &msiof3;
};
/*
@@ -60,6 +64,46 @@
clock-frequency = <0>;
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <960000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -71,6 +115,13 @@
power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <854>;
+ cooling-min-level = <0>;
+ cooling-max-level = <2>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
};
a57_1: cpu@1 {
@@ -80,6 +131,9 @@
power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
};
L2_CA57: cache-controller-0 {
@@ -88,6 +142,20 @@
cache-unified;
cache-level = <2>;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <400>;
+ exit-latency-us = <500>;
+ min-residency-us = <4000>;
+ status = "okay";
+ };
+ };
};
extal_clk: extal {
@@ -104,6 +172,41 @@
clock-frequency = <0>;
};
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ gsx_opp_table: gsx_opp_table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <830000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <830000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <830000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <830000>;
+ };
+ };
+
+ /* MSIOF reference clock - to be overridden by boards that provide it */
+ msiof_ref_clk: msiof-ref-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
@@ -138,9 +241,29 @@
#size-cells = <2>;
ranges;
- wdt0: watchdog@e6020000 {
+ mfis: mfis@e6260000 {
+ compatible = "renesas,mfis-lock-r8a77965",
+ "renesas,mfis-lock";
+ reg = <0 0xe6260000 0 0x1000>;
+ #hwlock-cells = <1>;
+
+ mfis_as: mfis-as {
+ compatible = "renesas,mfis-as-r8a77965",
+ "renesas,mfis-as";
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eicr0";
+ renesas,mfis-ch = <0>;
+ };
+ };
+
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a77965-wdt",
+ "renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
- /* placeholder */
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
};
gpio0: gpio@e6050000 {
@@ -315,9 +438,7 @@
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 407>;
};
i2c0: i2c@e6500000 {
@@ -451,12 +572,100 @@
status = "disabled";
};
+ hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a77965",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6540000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE R8A77965_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 520>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a77965",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6550000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 519>,
+ <&cpg CPG_CORE R8A77965_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 519>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e6560000 {
+ compatible = "renesas,hscif-r8a77965",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6560000 0 0x60>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 518>,
+ <&cpg CPG_CORE R8A77965_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 518>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a77965",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66a0000 0 0x60>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE R8A77965_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
+ hscif4: serial@e66b0000 {
+ compatible = "renesas,hscif-r8a77965",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66b0000 0 0x60>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 516>,
+ <&cpg CPG_CORE R8A77965_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 516>;
+ status = "disabled";
+ };
+
hsusb: usb@e6590000 {
- compatible = "renesas,usbhs-r8a7796",
+ compatible = "renesas,usbhs-r8a77965",
"renesas,rcar-gen3-usbhs";
- reg = <0 0xe6590000 0 0x100>;
+ reg = <0 0xe6590000 0 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 704>;
+ clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
@@ -464,7 +673,7 @@
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 704>;
+ resets = <&cpg 704>, <&cpg 703>;
status = "disabled";
};
@@ -541,6 +750,14 @@
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <16>;
+ iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+ <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+ <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+ <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+ <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+ <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+ <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+ <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
};
dmac1: dma-controller@e7300000 {
@@ -575,6 +792,14 @@
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <16>;
+ iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+ <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+ <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+ <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
+ <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
+ <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
+ <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
+ <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
};
dmac2: dma-controller@e7310000 {
@@ -609,6 +834,110 @@
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <16>;
+ iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+ <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+ <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+ <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
+ <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
+ <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
+ <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
+ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
+ };
+
+ ipmmu_mm: mmu@e67b0000 {
+ compatible = "renesas,ipmmu-r8a77965";
+ reg = <0 0xe67b0000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_ds0: mmu@e6740000 {
+ compatible = "renesas,ipmmu-r8a77965";
+ reg = <0 0xe6740000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 0>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_ds1: mmu@e7740000 {
+ compatible = "renesas,ipmmu-r8a77965";
+ reg = <0 0xe7740000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 1>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_hc: mmu@e6570000 {
+ compatible = "renesas,ipmmu-r8a77965";
+ reg = <0 0xe6570000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 2>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mp: mmu@ec670000 {
+ compatible = "renesas,ipmmu-r8a77965";
+ reg = <0 0xec670000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 4>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_pv0: mmu@fd800000 {
+ compatible = "renesas,ipmmu-r8a77965";
+ reg = <0 0xfd800000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 6>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_rt: mmu@ffc80000 {
+ compatible = "renesas,ipmmu-r8a77965";
+ reg = <0 0xffc80000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 10>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_vc0: mmu@fe6b0000 {
+ compatible = "renesas,ipmmu-mmu-r8a77965";
+ reg = <0 0xfe6b0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 12>;
+ power-domains = <&sysc R8A77965_PD_A3VC>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_vi0: mmu@febd0000 {
+ compatible = "renesas,ipmmu-r8a77965";
+ reg = <0 0xfebd0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 14>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_vp0: mmu@fe990000 {
+ compatible = "renesas,ipmmu-mmu-r8a77965";
+ reg = <0 0xfe990000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 16>;
+ power-domains = <&sysc R8A77965_PD_A3VP>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ qos@e67e0000 {
+ compatible = "renesas,qos";
+ reg = <0 0xe67e0000 0 0x10090>;
};
avb: ethernet@e6800000 {
@@ -656,6 +985,63 @@
status = "disabled";
};
+ can0: can@e6c30000 {
+ compatible = "renesas,can-r8a77965",
+ "renesas,rcar-gen3-can";
+ reg = <0 0xe6c30000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>,
+ <&cpg CPG_CORE R8A77965_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ status = "disabled";
+ };
+
+ can1: can@e6c38000 {
+ compatible = "renesas,can-r8a77965",
+ "renesas,rcar-gen3-can";
+ reg = <0 0xe6c38000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 915>,
+ <&cpg CPG_CORE R8A77965_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 915>;
+ status = "disabled";
+ };
+
+ canfd: can@e66c0000 {
+ compatible = "renesas,r8a77965-canfd",
+ "renesas,rcar-gen3-canfd";
+ reg = <0 0xe66c0000 0 0x8000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 914>,
+ <&cpg CPG_CORE R8A77965_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 914>;
+ status = "disabled";
+
+ channel0 {
+ status = "disabled";
+ };
+
+ channel1 {
+ status = "disabled";
+ };
+ };
+
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 8>;
@@ -732,7 +1118,7 @@
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 207>,
- <&cpg CPG_CORE 20>,
+ <&cpg CPG_CORE R8A77965_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
@@ -749,7 +1135,7 @@
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 206>,
- <&cpg CPG_CORE 20>,
+ <&cpg CPG_CORE R8A77965_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
@@ -766,7 +1152,7 @@
reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>,
- <&cpg CPG_CORE 20>,
+ <&cpg CPG_CORE R8A77965_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@@ -780,7 +1166,7 @@
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 204>,
- <&cpg CPG_CORE 20>,
+ <&cpg CPG_CORE R8A77965_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
@@ -796,7 +1182,7 @@
reg = <0 0xe6c40000 0 64>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 203>,
- <&cpg CPG_CORE 20>,
+ <&cpg CPG_CORE R8A77965_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
@@ -812,7 +1198,7 @@
reg = <0 0xe6f30000 0 64>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 202>,
- <&cpg CPG_CORE 20>,
+ <&cpg CPG_CORE R8A77965_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
@@ -828,7 +1214,8 @@
"renesas,rcar-gen3-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 211>;
+ clocks = <&cpg CPG_MOD 211>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
dma-names = "tx", "rx", "tx", "rx";
@@ -844,7 +1231,8 @@
"renesas,rcar-gen3-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 210>;
+ clocks = <&cpg CPG_MOD 210>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
@@ -860,7 +1248,8 @@
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 209>;
+ clocks = <&cpg CPG_MOD 209>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@@ -875,7 +1264,8 @@
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 208>;
+ clocks = <&cpg CPG_MOD 208>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@@ -907,11 +1297,11 @@
vin0csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin0>;
+ remote-endpoint = <&csi20vin0>;
};
vin0csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin0>;
+ remote-endpoint = <&csi40vin0>;
};
};
};
@@ -939,11 +1329,11 @@
vin1csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin1>;
+ remote-endpoint = <&csi20vin1>;
};
vin1csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin1>;
+ remote-endpoint = <&csi40vin1>;
};
};
};
@@ -971,11 +1361,11 @@
vin2csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin2>;
+ remote-endpoint = <&csi20vin2>;
};
vin2csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin2>;
+ remote-endpoint = <&csi40vin2>;
};
};
};
@@ -1003,11 +1393,11 @@
vin3csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin3>;
+ remote-endpoint = <&csi20vin3>;
};
vin3csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin3>;
+ remote-endpoint = <&csi40vin3>;
};
};
};
@@ -1035,11 +1425,11 @@
vin4csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin4>;
+ remote-endpoint = <&csi20vin4>;
};
vin4csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin4>;
+ remote-endpoint = <&csi40vin4>;
};
};
};
@@ -1067,11 +1457,11 @@
vin5csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin5>;
+ remote-endpoint = <&csi20vin5>;
};
vin5csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin5>;
+ remote-endpoint = <&csi40vin5>;
};
};
};
@@ -1099,11 +1489,11 @@
vin6csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin6>;
+ remote-endpoint = <&csi20vin6>;
};
vin6csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin6>;
+ remote-endpoint = <&csi40vin6>;
};
};
};
@@ -1131,52 +1521,353 @@
vin7csi20: endpoint@0 {
reg = <0>;
- remote-endpoint= <&csi20vin7>;
+ remote-endpoint = <&csi20vin7>;
};
vin7csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin7>;
+ remote-endpoint = <&csi40vin7>;
};
};
};
};
rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ /*
+ * #clock-cells is required for audio_clkout0/1/2/3
+ *
+ * clkout : #clock-cells = <0>; <&rcar_sound>;
+ * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3";
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
- /* placeholder */
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE R8A77965_CLK_S0D4>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+ status = "disabled";
rcar_sound,dvc {
dvc0: dvc-0 {
+ dmas = <&audma1 0xbc>;
+ dma-names = "tx";
};
dvc1: dvc-1 {
+ dmas = <&audma1 0xbe>;
+ dma-names = "tx";
};
};
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
rcar_sound,src {
src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma1 0x9a>;
+ dma-names = "rx", "tx";
};
src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma1 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma1 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma1 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma1 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma1 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma1 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma1 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma1 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma1 0xba>;
+ dma-names = "rx", "tx";
};
};
rcar_sound,ssi {
ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
};
};
+ };
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- };
- };
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a77965",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
+ <&ipmmu_mp 2>, <&ipmmu_mp 3>,
+ <&ipmmu_mp 4>, <&ipmmu_mp 5>,
+ <&ipmmu_mp 6>, <&ipmmu_mp 7>,
+ <&ipmmu_mp 8>, <&ipmmu_mp 9>,
+ <&ipmmu_mp 10>, <&ipmmu_mp 11>,
+ <&ipmmu_mp 12>, <&ipmmu_mp 13>,
+ <&ipmmu_mp 14>, <&ipmmu_mp 15>;
+ };
+
+ audma1: dma-controller@ec720000 {
+ compatible = "renesas,dmac-r8a77965",
+ "renesas,rcar-dmac";
+ reg = <0 0xec720000 0 0x10000>;
+ interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 501>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 501>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
+ <&ipmmu_mp 18>, <&ipmmu_mp 19>,
+ <&ipmmu_mp 20>, <&ipmmu_mp 21>,
+ <&ipmmu_mp 22>, <&ipmmu_mp 23>,
+ <&ipmmu_mp 24>, <&ipmmu_mp 25>,
+ <&ipmmu_mp 26>, <&ipmmu_mp 27>,
+ <&ipmmu_mp 28>, <&ipmmu_mp 29>,
+ <&ipmmu_mp 30>, <&ipmmu_mp 31>;
+ };
+
+ adsp: adsp@ec800000 {
+ compatible = "renesas,r8a77965-adsp",
+ "renesas,rcar-gen3-adsp";
+ reg = <0 0xec800000 0 0x80fc>,
+ <0 0xece60000 0 0x10000>,
+ <0 0xece78000 0 0x8000>,
+ <0 0xece80000 0 0x10000>,
+ <0 0xece90000 0 0x10000>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 506>,
+ <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&cpg CPG_MOD 501>, <&cpg CPG_MOD 502>,
+ <&cpg CPG_MOD 922>;
+ clock-names = "adsp",
+ "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "audmac.1", "audmac.0",
+ "adg";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 506>,
+ <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>,
+ <&cpg 501>, <&cpg 502>,
+ <&cpg 922>;
+ reset-names = "adsp",
+ "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "audmac.1", "audmac.0",
+ "adg";
+ status = "disabled";
};
xhci0: usb@ee000000 {
@@ -1205,11 +1896,11 @@
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 703>, <&cpg 704>;
status = "disabled";
};
@@ -1229,12 +1920,12 @@
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>;
phy-names = "usb";
companion = <&ohci0>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 703>, <&cpg 704>;
status = "disabled";
};
@@ -1256,9 +1947,9 @@
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 703>, <&cpg 704>;
#phy-cells = <0>;
status = "disabled";
};
@@ -1267,9 +1958,9 @@
compatible = "renesas,usb2-phy-r8a77965",
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee0a0200 0 0x700>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 702>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 702>;
#phy-cells = <0>;
status = "disabled";
};
@@ -1322,6 +2013,17 @@
status = "disabled";
};
+ sata: sata@ee300000 {
+ compatible = "renesas,sata-r8a77965",
+ "renesas,rcar-gen3-sata";
+ reg = <0 0xee300000 0 0x200000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -1333,77 +2035,116 @@
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 408>;
+ };
+
+ gsx: gsx@fd000000 {
+ compatible = "renesas,gsx";
+ reg = <0 0xfd000000 0 0x40000>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 112>;
+ operating-points-v2 = <&gsx_opp_table>;
+ power-domains = <&sysc R8A77965_PD_3DG_B>;
+ resets = <&cpg 112>;
};
pciec0: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a77965",
+ "renesas,pcie-rcar-gen3";
reg = <0 0xfe000000 0 0x80000>;
- /* placeholder */
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
};
pciec1: pcie@ee800000 {
+ compatible = "renesas,pcie-r8a77965",
+ "renesas,pcie-rcar-gen3";
reg = <0 0xee800000 0 0x80000>;
- /* placeholder */
- };
-
- fcpf0: fcp@fe950000 {
- compatible = "renesas,fcpf";
- reg = <0 0xfe950000 0 0x200>;
- clocks = <&cpg CPG_MOD 615>;
- power-domains = <&sysc R8A77965_PD_A3VP>;
- resets = <&cpg 615>;
- };
-
- vspb: vsp@fe960000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe960000 0 0x8000>;
- interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 626>;
- power-domains = <&sysc R8A77965_PD_A3VP>;
- resets = <&cpg 626>;
-
- renesas,fcp = <&fcpvb0>;
- };
-
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A77965_PD_A3VP>;
- resets = <&cpg 607>;
- };
-
- vspi0: vsp@fe9a0000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfe9a0000 0 0x8000>;
- interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 631>;
- power-domains = <&sysc R8A77965_PD_A3VP>;
- resets = <&cpg 631>;
-
- renesas,fcp = <&fcpvi0>;
- };
-
- fcpvi0: fcp@fe9af000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe9af000 0 0x200>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A77965_PD_A3VP>;
- resets = <&cpg 611>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x8000>;
- interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
+ 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
+ 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
+ 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
+ resets = <&cpg 318>;
+ status = "disabled";
+ };
- renesas,fcp = <&fcpvd0>;
+ fcpcs: vcp4@fe90f000 {
+ compatible = "renesas,vcp4-fcpcs";
+ reg = <0 0xfe90f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 619>;
+ power-domains = <&sysc R8A77965_PD_A3VC>;
+ resets = <&cpg 619>;
+ renesas,#ch = <0>;
+ };
+
+ vcplf: vcp4@fe910000 {
+ compatible = "renesas,vcp4-vcplf";
+ reg = <0 0xfe910000 0 0x200>, <0 0xfe910200 0 0x200>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 130>;
+ power-domains = <&sysc R8A77965_PD_A2VC1>;
+ resets = <&cpg 130>;
+ renesas,#ch = <0>;
+ renesas,#fcp_ch = <0>;
+ };
+
+ vdpb: vcp4@fe900000 {
+ compatible = "renesas,vcp4-vdpb";
+ reg = <0 0xfe900000 0 0x200>, <0 0xfe900200 0 0x200>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A77965_PD_A2VC1>;
+ resets = <&cpg 131>;
+ renesas,#ch = <1>;
+ renesas,#fcp_ch = <0>;
+ };
+
+ fdp0: fdpm@fe940000 {
+ compatible = "renesas,fdpm";
+ reg = <0 0xfe940000 0 0x2400>, <0 0xfe950000 0 0x200>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 119>, <&cpg CPG_MOD 615>;
+ clock-names = "fdp", "fcp";
+ power-domains = <&sysc R8A77965_PD_A3VP>;
+ resets = <&cpg 119>, <&cpg 615>;
+ reset-names = "fdp", "fcp";
+ renesas,#ch = <0>;
};
fcpvd0: fcp@fea27000 {
@@ -1414,9 +2155,63 @@
resets = <&cpg 603>;
};
+ fcpvd1: fcp@fea2f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea2f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 602>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 602>;
+ };
+
+ vsp@fe960000 {
+ compatible = "renesas,vspm-vsp2";
+ reg = <0 0xfe960000 0 0x8000>;
+ renesas,has-bru;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hgo;
+ renesas,#rpf = <5>;
+ renesas,#uds = <0>;
+ renesas,#wpf = <1>;
+ };
+
+ vspb: vspm@fe960000 {
+ compatible = "renesas,vspm";
+ reg = <0 0xfe960000 0 0x8000>, <0 0xfe96f000 0 0x200>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 626>, <&cpg CPG_MOD 607>;
+ clock-names = "vsp", "fcp";
+ renesas,#ch = <3>;
+ renesas,#rpf = <31>;
+ renesas,#rpf_clut = <6>;
+ renesas,#wpf_rot = <0>;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-bru;
+ renesas,has-hgo;
+ renesas,#read_outstanding = <0>;
+ renesas,#start_reservation = <2>;
+ power-domains = <&sysc R8A77965_PD_A3VP>;
+ resets = <&cpg 626>, <&cpg 607>;
+ reset-names = "vsp", "fcp";
+ status = "disabled";
+ };
+
+ vspd0: vsp@fea20000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea20000 0 0x5000>;
+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 623>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 623>;
+
+ renesas,#brs = <2>;
+ renesas,fcp = <&fcpvd0>;
+ };
+
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x8000>;
+ reg = <0 0xfea28000 0 0x5000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
@@ -1425,12 +2220,43 @@
renesas,fcp = <&fcpvd1>;
};
- fcpvd1: fcp@fea2f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfea2f000 0 0x200>;
- clocks = <&cpg CPG_MOD 602>;
- power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
- resets = <&cpg 602>;
+ vsp@fe9a0000 {
+ compatible = "renesas,vspm-vsp2";
+ reg = <0 0xfe9a0000 0 0x8000>;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hgo;
+ renesas,has-hgt;
+ renesas,#rpf = <1>;
+ renesas,#uds = <1>;
+ renesas,#wpf = <1>;
+ };
+
+ vspi0: vspm@fe9a0000 {
+ compatible = "renesas,vspm";
+ reg = <0 0xfe9a0000 0 0x8000>, <0 0xfe9af000 0 0x200>;
+ interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 631>, <&cpg CPG_MOD 611>;
+ clock-names = "vsp", "fcp";
+ renesas,#ch = <0>;
+ renesas,#rpf = <1>;
+ renesas,#rpf_clut = <1>;
+ renesas,#wpf_rot = <1>;
+ renesas,has-sru;
+ renesas,has-uds;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hst;
+ renesas,has-hsi;
+ renesas,has-hgo;
+ renesas,has-hgt;
+ renesas,has-shp;
+ renesas,#read_outstanding = <2>;
+ renesas,#start_reservation = <2>;
+ power-domains = <&sysc R8A77965_PD_A3VP>;
+ resets = <&cpg 631>, <&cpg 611>;
+ reset-names = "vsp", "fcp";
+ status = "disabled";
};
csi20: csi2@fea80000 {
@@ -1573,7 +2399,6 @@
du: display@feb00000 {
compatible = "renesas,du-r8a77965";
reg = <0 0xfeb00000 0 0x80000>;
- reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
@@ -1581,6 +2406,10 @@
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>;
clock-names = "du.0", "du.1", "du.3";
+ resets = <&cpg 724>,
+ <&cpg 724>,
+ <&cpg 722>;
+ reset-names = "du.0", "du.1", "du.3";
status = "disabled";
vsps = <&vspd0 0 &vspd1 0 &vspd0 1>;
@@ -1603,6 +2432,33 @@
port@2 {
reg = <2>;
du_out_lvds0: endpoint {
+ remote-endpoint = <&lvds0_in>;
+ };
+ };
+ };
+ };
+
+ lvds0: lvds@feb90000 {
+ compatible = "renesas,r8a77965-lvds";
+ reg = <0 0xfeb90000 0 0x14>;
+ clocks = <&cpg CPG_MOD 727>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 727>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
};
};
};
@@ -1614,19 +2470,20 @@
};
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
thermal-zones {
+ emergency {
+ polling-delay = <1000>;
+ on-temperature = <110000>;
+ off-temperature = <95000>;
+ target_cpus = <&a57_1>;
+ status = "disabled";
+ };
+
sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+ polling-delay = <0>;
thermal-sensors = <&tsc 0>;
+ sustainable-power = <2439>;
trips {
sensor1_crit: sensor1-crit {
@@ -1639,8 +2496,9 @@
sensor_thermal2: sensor-thermal2 {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+ polling-delay = <0>;
thermal-sensors = <&tsc 1>;
+ sustainable-power = <2439>;
trips {
sensor2_crit: sensor2-crit {
@@ -1653,19 +2511,50 @@
sensor_thermal3: sensor-thermal3 {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+ polling-delay = <0>;
thermal-sensors = <&tsc 2>;
+ sustainable-power = <2439>;
trips {
+ threshold: trip-point0 {
+ /* miliCelsius */
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ target: trip-point1 {
+ /* miliCelsius */
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&a57_0 0 2>;
+ contribution = <1024>;
+ };
+ };
};
};
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
/* External USB clocks - can be overridden by the board */
usb3s0_clk: usb3s0 {
compatible = "fixed-clock";
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
index 21f9cf5..b6d5332 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Eagle board
*
* Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
index 9fce031..8eac8ca 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the V3M Starter Kit board
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
/dts-v1/;
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 98a2317..3dc30a7 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the r8a77970 SoC
+ * Device Tree Source for the R-Car V3M (R8A77970) SoC
*
* Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
@@ -570,7 +567,7 @@
vin0csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin0>;
+ remote-endpoint = <&csi40vin0>;
};
};
};
@@ -598,7 +595,7 @@
vin1csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin1>;
+ remote-endpoint = <&csi40vin1>;
};
};
};
@@ -626,7 +623,7 @@
vin2csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin2>;
+ remote-endpoint = <&csi40vin2>;
};
};
};
@@ -654,7 +651,7 @@
vin3csi40: endpoint@2 {
reg = <2>;
- remote-endpoint= <&csi40vin3>;
+ remote-endpoint = <&csi40vin3>;
};
};
};
@@ -776,7 +773,7 @@
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x8000>;
+ reg = <0 0xfea20000 0 0x5000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 4c40f9f..8ecda23 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the r8a77980 SoC
+ * Device Tree Source for the R-Car V3H (R8A77980) SoC
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
@@ -202,6 +202,69 @@
};
};
+ ipmmu_ds1: mmu@e7740000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe7740000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 0>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vip0: mmu@e7b00000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe7b00000 0 0x1000>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vip1: mmu@e7960000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe7960000 0 0x1000>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_ir: mmu@ff8b0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xff8b0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 3>;
+ power-domains = <&sysc R8A77980_PD_A3IR>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_mm: mmu@e67b0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe67b0000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_rt: mmu@ffc80000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xffc80000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 10>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vc0: mmu@fe6b0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xfe6b0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 12>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vi0: mmu@febd0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xfebd0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 14>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77980",
"renesas,etheravb-rcar-gen3";
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu-4d.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu-4d.dts
new file mode 100644
index 0000000..1c19504
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu-4d.dts
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device Tree Source for the Ebisu-4D board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a77990-ebisu.dts"
+
+/ {
+ model = "Renesas Ebisu-4D board based on r8a77990";
+ compatible = "renesas,ebisu", "renesas,r8a77990";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ reserved-memory {
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress@54000000 {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+ };
+
+ mmngr {
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+};
+
+&pciec0 {
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 7a09d05..26081a6 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -7,7 +7,9 @@
/dts-v1/;
#include "r8a77990.dtsi"
+#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/power/r8a77990-sysc.h>
/ {
model = "Renesas Ebisu board based on r8a77990";
@@ -28,14 +30,332 @@
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* For Audio DSP */
+ adsp_reserved: linux,adsp@57000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x01000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x58000000 0x0 0x10000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia@68000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x68000000 0x0 0x04000000>;
+ };
+ };
+
+ audio_clkout: audio-clkout {
+ /*
+ * This is same as <&rcar_sound 0>
+ * but needed to avoid cs2000/rcar_sound probe dead-lock
+ */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ avb-mch@ec5a0100 {
+ compatible = "renesas,avb-mch-gen3";
+ reg = <0 0xec5a0100 0 0x100>; /* ADG_AVB */
+ reg-name = "adg_avb";
+
+ clocks = <&cpg CPG_MOD 922>;
+ clock-names = "adg";
+ resets = <&cpg 922>;
+ };
+
+ cvbs-in {
+ compatible = "composite-video-connector";
+ label = "CVBS IN";
+
+ port {
+ cvbs_con: endpoint {
+ remote-endpoint = <&adv7482_ain7>;
+ };
+ };
+ };
+
+ hdmi-in {
+ compatible = "hdmi-connector";
+ label = "HDMI IN";
+ type = "a";
+
+ port {
+ hdmi_in_con: endpoint {
+ remote-endpoint = <&adv7482_hdmi>;
+ };
+ };
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_out: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ lvds-decoder {
+ compatible = "thine,thc63lvd1024";
+ vcc-supply = <®_3p3v>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ thc63lvd1024_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ thc63lvd1024_out: endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ };
+ };
+
+ lvds0 {
+ compatible = "panel-lvds";
+
+ width-mm = <210>;
+ height-mm = <158>;
+
+ data-mapping = "jeida-24";
+
+ panel-timing {
+ /* 1024x768 @60Hz */
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hsync-len = <136>;
+ hfront-porch = <20>;
+ hback-porch = <160>;
+ vfront-porch = <3>;
+ vback-porch = <29>;
+ vsync-len = <6>;
+ };
+
+ port {
+ lvds0_panel_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ };
+
+ lvds1 {
+ compatible = "panel-lvds";
+
+ width-mm = <210>;
+ height-mm = <158>;
+
+ data-mapping = "jeida-24";
+
+ panel-timing {
+ /* 1024x768 @60Hz */
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hsync-len = <136>;
+ hfront-porch = <20>;
+ hback-porch = <160>;
+ vfront-porch = <3>;
+ vback-porch = <29>;
+ vsync-len = <6>;
+ };
+
+ port {
+ lvds1_panel_in: endpoint {
+ remote-endpoint = <&du_out_lvds1>;
+ };
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ reg_1p8v: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sound_card: sound {
+ compatible = "audio-graph-card";
+
+ label = "rcar-sound";
+
+ dais = <&rsnd_port0>;
+ };
+
+ vbus0_usb2: regulator-vbus0-usb2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB20_VBUS_CN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc_sdhi1: regulator-vcc-sdhi1 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ no-use-ddc;
+
+ width = <1024>;
+ height = <768>;
+ max-pixelclock = <75000>;
+
+ port {
+ vga_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+ };
+
+ vga-encoder {
+ compatible = "adi,adv7123";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7123_in: endpoint {
+ remote-endpoint = <&lvds1_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ adv7123_out: endpoint {
+ remote-endpoint = <&vga_in>;
+ };
+ };
+ };
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+
+ x12_clk: x12 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ x13_clk: x13 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+};
+
+&adsp {
+ status = "okay";
+ memory-region = <&adsp_reserved>;
+};
+
+&audio_clk_a {
+ clock-frequency = <22579200>;
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
- renesas,no-ether-link;
phy-handle = <&phy0>;
- phy-mode = "rgmii-txid";
+ phy-mode = "rgmii";
status = "okay";
phy0: ethernet-phy@0 {
@@ -47,10 +367,226 @@
};
};
+&csi40 {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+
+ csi40_in: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&adv7482_txa>;
+ };
+ };
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&x13_clk>;
+ clock-names = "du.0", "du.1", "dclkin.0";
+};
+
+&ehci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&extal_clk {
clock-frequency = <48000000>;
};
+&hsusb {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ hdmi-encoder@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&thc63lvd1024_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ video-receiver@70 {
+ compatible = "adi,adv7482";
+ reg = <0x70>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupt-names = "intrq1", "intrq2";
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
+ <17 IRQ_TYPE_LEVEL_LOW>;
+
+ port@7 {
+ reg = <7>;
+
+ adv7482_ain7: endpoint {
+ remote-endpoint = <&cvbs_con>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+
+ adv7482_hdmi: endpoint {
+ remote-endpoint = <&hdmi_in_con>;
+ };
+ };
+
+ port@a {
+ reg = <10>;
+
+ adv7482_txa: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&csi40_in>;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+
+ ak4613: codec@10 {
+ compatible = "asahi-kasei,ak4613";
+ #sound-dai-cells = <0>;
+ reg = <0x10>;
+ clocks = <&rcar_sound 3>;
+
+ asahi-kasei,in1-single-end;
+ asahi-kasei,in2-single-end;
+ asahi-kasei,out1-single-end;
+ asahi-kasei,out2-single-end;
+ asahi-kasei,out3-single-end;
+ asahi-kasei,out4-single-end;
+ asahi-kasei,out5-single-end;
+ asahi-kasei,out6-single-end;
+
+ port {
+ ak4613_endpoint: endpoint {
+ remote-endpoint = <&rsnd_endpoint0>;
+ };
+ };
+ };
+
+ cs2000: clk-multiplier@4f {
+ #clock-cells = <0>;
+ compatible = "cirrus,cs2000-cp";
+ reg = <0x4f>;
+ clocks = <&audio_clkout>, <&x12_clk>;
+ clock-names = "clk_in", "ref_clk";
+
+ assigned-clocks = <&cs2000>;
+ assigned-clock-rates = <24576000>; /* 1/1 divide */
+ };
+};
+
+
+&i2c_dvfs {
+ status = "okay";
+
+ clock-frequency = <400000>;
+
+ pmic: pmic@30 {
+ pinctrl-0 = <&irq0_pins>;
+ pinctrl-names = "default";
+
+ compatible = "rohm,bd9571mwv";
+ reg = <0x30>;
+ interrupt-parent = <&intc_ex>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&lvds0 {
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 727>,
+ <&x13_clk>,
+ <&extal_clk>;
+ clock-names = "fck", "dclkin.0", "extal";
+
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&thc63lvd1024_in>;
+ };
+ };
+ };
+};
+
+&lvds1 {
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 727>,
+ <&extal_clk>;
+ clock-names = "fck", "extal";
+
+ ports {
+ port@1 {
+ lvds1_out: endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ };
+};
+
+&ohci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pciec0 {
+ status = "okay";
+};
+
&pfc {
avb_pins: avb {
mux {
@@ -58,8 +594,248 @@
function = "avb";
};
};
+
+ du_pins: du {
+ groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+ function = "du";
+ };
+
+ i2c3_pins: i2c3 {
+ groups = "i2c3";
+ function = "i2c3";
+ };
+
+ irq0_pins: irq0 {
+ groups = "intc_ex_irq0";
+ function = "intc_ex";
+ };
+
+ pwm3_pins: pwm3 {
+ groups = "pwm3_b";
+ function = "pwm3";
+ };
+
+ pwm5_pins: pwm5 {
+ groups = "pwm5_a";
+ function = "pwm5";
+ };
+
+ scif2_pins: scif2 {
+ groups = "scif2_data_a";
+ function = "scif2";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
+
+ sdhi1_pins: sd1 {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
+ };
+
+ sdhi3_pins: sd3 {
+ groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
+ function = "sdhi3";
+ power-source = <3300>;
+ };
+
+ sdhi3_pins_uhs: sd3_uhs {
+ groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
+ function = "sdhi3";
+ power-source = <1800>;
+ };
+
+ sound_pins: sound {
+ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
+ function = "ssi";
+ };
+
+ sound_clk_pins: sound_clk {
+ groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
+ "audio_clkout_a", "audio_clkout1_a";
+ function = "audio_clk";
+ };
+
+ usb0_pins: usb {
+ groups = "usb0_b", "usb0_id";
+ function = "usb0";
+ };
+
+ usb30_pins: usb30 {
+ groups = "usb30";
+ function = "usb30";
+ };
+};
+
+&pwm3 {
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pwm5 {
+ pinctrl-0 = <&pwm5_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-names = "default";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ /* audio_clkout0/1/2/3 */
+ #clock-cells = <1>;
+ clock-frequency = <12288000 11289600>;
+ clkout-lr-synchronous;
+
+ status = "okay";
+
+ /* update <audio_clk_b> to <cs2000> */
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
+ <&cpg CPG_CORE R8A77990_CLK_ZA2>;
+
+ ports {
+ rsnd_port0: port@0 {
+ rsnd_endpoint0: endpoint {
+ remote-endpoint = <&ak4613_endpoint>;
+
+ dai-format = "left_j";
+ bitclock-master = <&rsnd_endpoint0>;
+ frame-master = <&rsnd_endpoint0>;
+
+ playback = <&ssi0 &src0 &dvc0>;
+ capture = <&ssi1 &src1 &dvc1>;
+ };
+ };
+ };
};
&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi3 {
+ /* used for on-board 8bit eMMC */
+ pinctrl-0 = <&sdhi3_pins>;
+ pinctrl-1 = <&sdhi3_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&ssi1 {
+ shared-pin;
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ vbus-supply = <&vbus0_usb2>;
+ status = "okay";
+};
+
+&usb3_peri0 {
+ status = "okay";
+};
+
+&vin4 {
+ status = "okay";
+};
+
+&vin5 {
+ status = "okay";
+};
+
+&vspb {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
+
+&xhci0 {
+ pinctrl-0 = <&usb30_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-es10-ebisu-4d.dts b/arch/arm64/boot/dts/renesas/r8a77990-es10-ebisu-4d.dts
new file mode 100644
index 0000000..dff31f1
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77990-es10-ebisu-4d.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Ebisu-4D board with R-Car E3 ES1.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a77990-es10-ebisu.dts"
+
+/ {
+ model = "Renesas Ebisu-4D board based on r8a77990 ES1.0";
+ compatible = "renesas,ebisu", "renesas,r8a77990";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+
+ reserved-memory {
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress@54000000 {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+ };
+
+ mmngr {
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+};
+
+&pciec0 {
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-es10-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-es10-ebisu.dts
new file mode 100644
index 0000000..087d553
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77990-es10-ebisu.dts
@@ -0,0 +1,841 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the ebisu board with R-Car E3 ES1.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a77990-es10.dtsi"
+#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/power/r8a77990-sysc.h>
+
+/ {
+ model = "Renesas Ebisu board based on r8a77990 ES1.0";
+ compatible = "renesas,ebisu", "renesas,r8a77990";
+
+ aliases {
+ serial0 = &scif2;
+ ethernet0 = &avb;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x38000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* For Audio DSP */
+ adsp_reserved: linux,adsp@57000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x01000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma@58000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x58000000 0x0 0x10000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia@68000000 {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x68000000 0x0 0x04000000>;
+ };
+ };
+
+ audio_clkout: audio-clkout {
+ /*
+ * This is same as <&rcar_sound 0>
+ * but needed to avoid cs2000/rcar_sound probe dead-lock
+ */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ avb-mch@ec5a0100 {
+ compatible = "renesas,avb-mch-gen3";
+ reg = <0 0xec5a0100 0 0x100>; /* ADG_AVB */
+ reg-name = "adg_avb";
+
+ clocks = <&cpg CPG_MOD 922>;
+ clock-names = "adg";
+ resets = <&cpg 922>;
+ };
+
+ cvbs-in {
+ compatible = "composite-video-connector";
+ label = "CVBS IN";
+
+ port {
+ cvbs_con: endpoint {
+ remote-endpoint = <&adv7482_ain7>;
+ };
+ };
+ };
+
+ hdmi-in {
+ compatible = "hdmi-connector";
+ label = "HDMI IN";
+ type = "a";
+
+ port {
+ hdmi_in_con: endpoint {
+ remote-endpoint = <&adv7482_hdmi>;
+ };
+ };
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_out: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ lvds-decoder {
+ compatible = "thine,thc63lvd1024";
+ vcc-supply = <®_3p3v>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ thc63lvd1024_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ thc63lvd1024_out: endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ };
+ };
+
+ lvds0 {
+ compatible = "panel-lvds";
+
+ width-mm = <210>;
+ height-mm = <158>;
+
+ data-mapping = "jeida-24";
+
+ panel-timing {
+ /* 1024x768 @60Hz */
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hsync-len = <136>;
+ hfront-porch = <20>;
+ hback-porch = <160>;
+ vfront-porch = <3>;
+ vback-porch = <29>;
+ vsync-len = <6>;
+ };
+
+ port {
+ lvds0_panel_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ };
+
+ lvds1 {
+ compatible = "panel-lvds";
+
+ width-mm = <210>;
+ height-mm = <158>;
+
+ data-mapping = "jeida-24";
+
+ panel-timing {
+ /* 1024x768 @60Hz */
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hsync-len = <136>;
+ hfront-porch = <20>;
+ hback-porch = <160>;
+ vfront-porch = <3>;
+ vback-porch = <29>;
+ vsync-len = <6>;
+ };
+
+ port {
+ lvds1_panel_in: endpoint {
+ remote-endpoint = <&du_out_lvds1>;
+ };
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ reg_1p8v: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sound_card: sound {
+ compatible = "audio-graph-card";
+
+ label = "rcar-sound";
+
+ dais = <&rsnd_port0>;
+ };
+
+ vbus0_usb2: regulator-vbus0-usb2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB20_VBUS_CN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc_sdhi1: regulator-vcc-sdhi1 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vccq_sdhi1: regulator-vccq-sdhi1 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ no-use-ddc;
+
+ width = <1024>;
+ height = <768>;
+ max-pixelclock = <75000>;
+
+ port {
+ vga_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+ };
+
+ vga-encoder {
+ compatible = "adi,adv7123";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7123_in: endpoint {
+ remote-endpoint = <&lvds1_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ adv7123_out: endpoint {
+ remote-endpoint = <&vga_in>;
+ };
+ };
+ };
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+
+ x12_clk: x12 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ x13_clk: x13 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+};
+
+&adsp {
+ status = "okay";
+ memory-region = <&adsp_reserved>;
+};
+
+&audio_clk_a {
+ clock-frequency = <22579200>;
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii";
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&csi40 {
+ status = "okay";
+
+ ports {
+ port@0 {
+ reg = <0>;
+
+ csi40_in: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&adv7482_txa>;
+ };
+ };
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&x13_clk>;
+ clock-names = "du.0", "du.1", "dclkin.0";
+};
+
+&ehci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&extal_clk {
+ clock-frequency = <48000000>;
+};
+
+&hsusb {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ hdmi-encoder@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&thc63lvd1024_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ video-receiver@70 {
+ compatible = "adi,adv7482";
+ reg = <0x70>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&gpio0>;
+ interrupt-names = "intrq1", "intrq2";
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
+ <17 IRQ_TYPE_LEVEL_LOW>;
+
+ port@7 {
+ reg = <7>;
+
+ adv7482_ain7: endpoint {
+ remote-endpoint = <&cvbs_con>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+
+ adv7482_hdmi: endpoint {
+ remote-endpoint = <&hdmi_in_con>;
+ };
+ };
+
+ port@a {
+ reg = <10>;
+
+ adv7482_txa: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ remote-endpoint = <&csi40_in>;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ status = "okay";
+
+ ak4613: codec@10 {
+ compatible = "asahi-kasei,ak4613";
+ #sound-dai-cells = <0>;
+ reg = <0x10>;
+ clocks = <&rcar_sound 3>;
+
+ asahi-kasei,in1-single-end;
+ asahi-kasei,in2-single-end;
+ asahi-kasei,out1-single-end;
+ asahi-kasei,out2-single-end;
+ asahi-kasei,out3-single-end;
+ asahi-kasei,out4-single-end;
+ asahi-kasei,out5-single-end;
+ asahi-kasei,out6-single-end;
+
+ port {
+ ak4613_endpoint: endpoint {
+ remote-endpoint = <&rsnd_endpoint0>;
+ };
+ };
+ };
+
+ cs2000: clk-multiplier@4f {
+ #clock-cells = <0>;
+ compatible = "cirrus,cs2000-cp";
+ reg = <0x4f>;
+ clocks = <&audio_clkout>, <&x12_clk>;
+ clock-names = "clk_in", "ref_clk";
+
+ assigned-clocks = <&cs2000>;
+ assigned-clock-rates = <24576000>; /* 1/1 divide */
+ };
+};
+
+
+&i2c_dvfs {
+ status = "okay";
+
+ clock-frequency = <400000>;
+
+ pmic: pmic@30 {
+ pinctrl-0 = <&irq0_pins>;
+ pinctrl-names = "default";
+
+ compatible = "rohm,bd9571mwv";
+ reg = <0x30>;
+ interrupt-parent = <&intc_ex>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&lvds0 {
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 727>,
+ <&x13_clk>,
+ <&extal_clk>;
+ clock-names = "fck", "dclkin.0", "extal";
+
+ ports {
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&thc63lvd1024_in>;
+ };
+ };
+ };
+};
+
+&lvds1 {
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 727>,
+ <&extal_clk>;
+ clock-names = "fck", "extal";
+
+ ports {
+ port@1 {
+ lvds1_out: endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ };
+};
+
+&ohci0 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pciec0 {
+ status = "okay";
+};
+
+&pfc {
+ avb_pins: avb {
+ mux {
+ groups = "avb_link", "avb_mii";
+ function = "avb";
+ };
+ };
+
+ du_pins: du {
+ groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
+ function = "du";
+ };
+
+ i2c3_pins: i2c3 {
+ groups = "i2c3";
+ function = "i2c3";
+ };
+
+ irq0_pins: irq0 {
+ groups = "intc_ex_irq0";
+ function = "intc_ex";
+ };
+
+ pwm3_pins: pwm3 {
+ groups = "pwm3_b";
+ function = "pwm3";
+ };
+
+ pwm5_pins: pwm5 {
+ groups = "pwm5_a";
+ function = "pwm5";
+ };
+
+ scif2_pins: scif2 {
+ groups = "scif2_data_a";
+ function = "scif2";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
+
+ sdhi1_pins: sd1 {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
+ };
+
+ sdhi3_pins: sd3 {
+ groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
+ function = "sdhi3";
+ power-source = <3300>;
+ };
+
+ sdhi3_pins_uhs: sd3_uhs {
+ groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
+ function = "sdhi3";
+ power-source = <1800>;
+ };
+
+ sound_pins: sound {
+ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
+ function = "ssi";
+ };
+
+ sound_clk_pins: sound_clk {
+ groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
+ "audio_clkout_a", "audio_clkout1_a";
+ function = "audio_clk";
+ };
+
+ usb0_pins: usb {
+ groups = "usb0_b", "usb0_id";
+ function = "usb0";
+ };
+
+ usb30_pins: usb30 {
+ groups = "usb30";
+ function = "usb30";
+ };
+};
+
+&pwm3 {
+ pinctrl-0 = <&pwm3_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&pwm5 {
+ pinctrl-0 = <&pwm5_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-names = "default";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ /* audio_clkout0/1/2/3 */
+ #clock-cells = <1>;
+ clock-frequency = <12288000 11289600>;
+ clkout-lr-synchronous;
+
+ status = "okay";
+
+ /* update <audio_clk_b> to <cs2000> */
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
+ <&cpg CPG_CORE R8A77990_CLK_ZA2>;
+
+ ports {
+ rsnd_port0: port@0 {
+ rsnd_endpoint0: endpoint {
+ remote-endpoint = <&ak4613_endpoint>;
+
+ dai-format = "left_j";
+ bitclock-master = <&rsnd_endpoint0>;
+ frame-master = <&rsnd_endpoint0>;
+
+ playback = <&ssi0 &src0 &dvc0>;
+ capture = <&ssi1 &src1 &dvc1>;
+ };
+ };
+ };
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi1 {
+ pinctrl-0 = <&sdhi1_pins>;
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi1>;
+ vqmmc-supply = <&vccq_sdhi1>;
+ cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi3 {
+ /* used for on-board 8bit eMMC */
+ pinctrl-0 = <&sdhi3_pins>;
+ pinctrl-1 = <&sdhi3_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&ssi1 {
+ shared-pin;
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ vbus-supply = <&vbus0_usb2>;
+ status = "okay";
+};
+
+&usb3_peri0 {
+ status = "okay";
+};
+
+&vin4 {
+ status = "okay";
+};
+
+&vin5 {
+ status = "okay";
+};
+
+&vspb {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
+
+&xhci0 {
+ pinctrl-0 = <&usb30_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-es10.dtsi b/arch/arm64/boot/dts/renesas/r8a77990-es10.dtsi
new file mode 100644
index 0000000..7b067ff
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77990-es10.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the R-Car E3 (R8A77990) ES1.0 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include "r8a77990.dtsi"
+
+&gsx {
+ power-domains = <&sysc R8A77990_PD_3DG_A>;
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index be4f519..bd4d71e 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -1,38 +1,131 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Device Tree Source for the r8a77990 SoC
+ * Device Tree Source for the R-Car E3 (R8A77990) SoC
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
-#include <dt-bindings/clock/renesas-cpg-mssr.h>
+#include <dt-bindings/clock/r8a77990-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a77990-sysc.h>
/ {
compatible = "renesas,r8a77990";
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c_dvfs;
+ i2c8 = &i2c7;
+ spi0 = &msiof0;
+ spi1 = &msiof1;
+ spi2 = &msiof2;
+ spi3 = &msiof3;
+ };
+
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ cluster1_opp: opp_table10 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
- /* 1 core only at this point */
a53_0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0>;
+ reg = <0>;
device_type = "cpu";
- power-domains = <&sysc 5>;
+ power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <277>;
+ cooling-min-level = <0>;
+ cooling-max-level = <2>;
+ cpu-idle-states = <&CPU_SLEEP_1>;
+ clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
+ };
+
+ a53_1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <1>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_1>;
+ clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
L2_CA53: cache-controller-0 {
compatible = "cache";
- power-domains = <&sysc 21>;
+ power-domains = <&sysc R8A77990_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_1: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <700>;
+ exit-latency-us = <700>;
+ min-residency-us = <5000>;
+ status = "okay";
+ };
+ };
};
extal_clk: extal {
@@ -42,10 +135,45 @@
clock-frequency = <0>;
};
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ gsx_opp_table: gsx_opp_table {
+ compatible = "operating-points-v2";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <820000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <820000>;
+ };
+ };
+
+ /* MSIOF reference clock - to be overridden by boards that provide it */
+ msiof_ref_clk: msiof-ref-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
- interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&a53_0>;
+ interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>, <&a53_1>;
};
psci {
@@ -53,6 +181,13 @@
method = "smc";
};
+ /* External SCIF clock - to be overridden by boards that provide it */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -60,6 +195,31 @@
#size-cells = <2>;
ranges;
+ mfis: mfis@e6260000 {
+ compatible = "renesas,mfis-lock-r8a77990",
+ "renesas,mfis-lock";
+ reg = <0 0xe6260000 0 0x1000>;
+ #hwlock-cells = <1>;
+
+ mfis_as: mfis-as {
+ compatible = "renesas,mfis-as-r8a77990",
+ "renesas,mfis-as";
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eicr0";
+ renesas,mfis-ch = <0>;
+ };
+ };
+
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a77990-wdt",
+ "renesas,rcar-gen3-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77990",
"renesas,rcar-gen3-gpio";
@@ -71,7 +231,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 912>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 912>;
};
@@ -86,7 +246,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 911>;
};
@@ -101,7 +261,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 910>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 910>;
};
@@ -116,7 +276,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 909>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 909>;
};
@@ -131,7 +291,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 908>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 908>;
};
@@ -146,7 +306,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 907>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 907>;
};
@@ -161,7 +321,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 906>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 906>;
};
@@ -191,10 +351,537 @@
#power-domain-cells = <1>;
};
+ tsc: thermal@e6190000 {
+ compatible = "renesas,r8a77990-thermal";
+ reg = <0 0xe6190000 0 0x138>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <1>;
+ status = "okay";
+ };
+
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ };
+
+ i2c0: i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77990",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6500000 0 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+ <&dmac2 0x91>, <&dmac2 0x90>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77990",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6508000 0 0x40>;
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+ <&dmac2 0x93>, <&dmac2 0x92>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@e6510000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77990",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6510000 0 0x40>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+ <&dmac2 0x95>, <&dmac2 0x94>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@e66d0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77990",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d0000 0 0x40>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+ dma-names = "tx", "rx";
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@e66d8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77990",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66d8000 0 0x40>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ dmas = <&dmac0 0x99>, <&dmac0 0x98>;
+ dma-names = "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@e66e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77990",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66e0000 0 0x40>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 919>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 919>;
+ dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
+ dma-names = "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@e66e8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77990",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe66e8000 0 0x40>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 918>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 918>;
+ dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
+ dma-names = "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@e6690000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77990",
+ "renesas,rcar-gen3-i2c";
+ reg = <0 0xe6690000 0 0x40>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1003>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 1003>;
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
+ };
+
+ i2c_dvfs: i2c@e60b0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-r8a77990",
+ "renesas,rcar-gen3-iic",
+ "renesas,rmobile-iic";
+ reg = <0 0xe60b0000 0 0x34>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 926>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 926>;
+ dmas = <&dmac0 0x11>, <&dmac0 0x10>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a77990",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6540000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 520>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a77990",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6550000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 519>,
+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>,
+ <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 519>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e6560000 {
+ compatible = "renesas,hscif-r8a77990",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6560000 0 0x60>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 518>,
+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x35>, <&dmac1 0x34>,
+ <&dmac2 0x35>, <&dmac2 0x34>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 518>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a77990",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66a0000 0 0x60>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
+ hscif4: serial@e66b0000 {
+ compatible = "renesas,hscif-r8a77990",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66b0000 0 0x60>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 516>,
+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x38>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 516>;
+ status = "disabled";
+ };
+
+ hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a77990",
+ "renesas,rcar-gen3-usbhs";
+ reg = <0 0xe6590000 0 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ renesas,buswait = <11>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 704>, <&cpg 703>;
+ status = "disabled";
+ };
+
+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,r8a77990-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 330>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,r8a77990-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a77990",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x10000>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+ <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+ <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+ <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+ <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+ <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+ <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+ <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
+ };
+
+ dmac1: dma-controller@e7300000 {
+ compatible = "renesas,dmac-r8a77990",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7300000 0 0x10000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
+ <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
+ <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
+ <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
+ <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
+ <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
+ <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
+ <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
+ };
+
+ dmac2: dma-controller@e7310000 {
+ compatible = "renesas,dmac-r8a77990",
+ "renesas,rcar-dmac";
+ reg = <0 0xe7310000 0 0x10000>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 217>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 217>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
+ <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
+ <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
+ <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
+ <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
+ <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
+ <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
+ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
+ };
+
+ ipmmu_mm: mmu@e67b0000 {
+ compatible = "renesas,ipmmu-r8a77990";
+ reg = <0 0xe67b0000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_ds0: mmu@e6740000 {
+ compatible = "renesas,ipmmu-r8a77990";
+ reg = <0 0xe6740000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 0>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_ds1: mmu@e7740000 {
+ compatible = "renesas,ipmmu-r8a77990";
+ reg = <0 0xe7740000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 1>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_hc: mmu@e6570000 {
+ compatible = "renesas,ipmmu-r8a77990";
+ reg = <0 0xe6570000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 2>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_mp: mmu@ec670000 {
+ compatible = "renesas,ipmmu-r8a77990";
+ reg = <0 0xec670000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 4>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_pv0: mmu@fd800000 {
+ compatible = "renesas,ipmmu-r8a77990";
+ reg = <0 0xfd800000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 6>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_rt: mmu@ffc80000 {
+ compatible = "renesas,ipmmu-r8a77990";
+ reg = <0 0xffc80000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 10>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_vc0: mmu@fe6b0000 {
+ compatible = "renesas,ipmmu-mmu-r8a77990";
+ reg = <0 0xfe6b0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 12>;
+ power-domains = <&sysc R8A77990_PD_A3VC>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_vi0: mmu@febd0000 {
+ compatible = "renesas,ipmmu-r8a77990";
+ reg = <0 0xfebd0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 14>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ ipmmu_vp0: mmu@fe990000 {
+ compatible = "renesas,ipmmu-mmu-r8a77990";
+ reg = <0 0xfe990000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 16>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ qos@e67e0000 {
+ compatible = "renesas,qos";
+ reg = <0 0xe67e0000 0 0x10090>;
+ };
+
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77990",
"renesas,etheravb-rcar-gen3";
- reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+ reg = <0 0xe6800000 0 0x800>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@@ -228,7 +915,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
- power-domains = <&sysc 32>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
#address-cells = <1>;
@@ -236,18 +923,704 @@
status = "disabled";
};
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x8>;
+ clocks = <&cpg CPG_MOD 523>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a77990",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x51>, <&dmac1 0x50>,
+ <&dmac2 0x51>, <&dmac2 0x50>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a77990",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x53>, <&dmac1 0x52>,
+ <&dmac2 0x53>, <&dmac2 0x52>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a77990",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 310>;
- clock-names = "fck";
- power-domains = <&sysc 32>;
+ clocks = <&cpg CPG_MOD 310>,
+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
};
+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a77990",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x57>, <&dmac0 0x56>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a77990",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x59>, <&dmac0 0x58>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6f30000 {
+ compatible = "renesas,scif-r8a77990",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6f30000 0 64>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>,
+ <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
+ <&dmac2 0x5b>, <&dmac2 0x5a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
+
+ msiof0: spi@e6e90000 {
+ compatible = "renesas,msiof-r8a77990",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6e90000 0 0x0064>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 211>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
+ dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+ <&dmac2 0x41>, <&dmac2 0x40>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 211>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof1: spi@e6ea0000 {
+ compatible = "renesas,msiof-r8a77990",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6ea0000 0 0x0064>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 210>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
+ dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+ <&dmac2 0x43>, <&dmac2 0x42>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 210>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof2: spi@e6c00000 {
+ compatible = "renesas,msiof-r8a77990",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c00000 0 0x0064>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 209>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
+ dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 209>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ msiof3: spi@e6c10000 {
+ compatible = "renesas,msiof-r8a77990",
+ "renesas,rcar-gen3-msiof";
+ reg = <0 0xe6c10000 0 0x0064>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 208>, <&msiof_ref_clk>;
+ clock-names = "msiof_clk", "msiof_ref_clk";
+ dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 208>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ vin4: video@e6ef4000 {
+ compatible = "renesas,vin-r8a77990";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ renesas,id = <4>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video@e6ef5000 {
+ compatible = "renesas,vin-r8a77990";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ renesas,id = <5>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin5>;
+ };
+ };
+ };
+ };
+
+ rcar_sound: sound@ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ /*
+ * #clock-cells is required for audio_clkout0/1/2/3
+ *
+ * clkout : #clock-cells = <0>; <&rcar_sound>;
+ * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&audio_clk_b>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE R8A77990_CLK_ZA2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma0 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma0 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src0: src-0 {
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x85>, <&audma0 0x9a>;
+ dma-names = "rx", "tx";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma0 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma0 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma0 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma0 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma0 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma0 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ src7: src-7 {
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x93>, <&audma0 0xb6>;
+ dma-names = "rx", "tx";
+ };
+ src8: src-8 {
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x95>, <&audma0 0xb8>;
+ dma-names = "rx", "tx";
+ };
+ src9: src-9 {
+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x97>, <&audma0 0xba>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma0 0x02>,
+ <&audma0 0x15>, <&audma0 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma0 0x04>,
+ <&audma0 0x49>, <&audma0 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma0 0x06>,
+ <&audma0 0x63>, <&audma0 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma0 0x08>,
+ <&audma0 0x6f>, <&audma0 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma0 0x0a>,
+ <&audma0 0x71>, <&audma0 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma0 0x0c>,
+ <&audma0 0x73>, <&audma0 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma0 0x0e>,
+ <&audma0 0x75>, <&audma0 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma0 0x10>,
+ <&audma0 0x79>, <&audma0 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma0 0x12>,
+ <&audma0 0x7b>, <&audma0 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma0 0x14>,
+ <&audma0 0x7d>, <&audma0 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ };
+ };
+ };
+
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a77990",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
+ <&ipmmu_mp 2>, <&ipmmu_mp 3>,
+ <&ipmmu_mp 4>, <&ipmmu_mp 5>,
+ <&ipmmu_mp 6>, <&ipmmu_mp 7>,
+ <&ipmmu_mp 8>, <&ipmmu_mp 9>,
+ <&ipmmu_mp 10>, <&ipmmu_mp 11>,
+ <&ipmmu_mp 12>, <&ipmmu_mp 13>,
+ <&ipmmu_mp 14>, <&ipmmu_mp 15>;
+ };
+
+ adsp: adsp@ec800000 {
+ compatible = "renesas,r8a77990-adsp",
+ "renesas,rcar-gen3-adsp";
+ reg = <0 0xec800000 0 0x80fc>,
+ <0 0xece60000 0 0x10000>,
+ <0 0xece80000 0 0x10000>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 506>,
+ <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&cpg CPG_MOD 502>,
+ <&cpg CPG_MOD 922>;
+ clock-names = "adsp",
+ "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "audmac.0",
+ "adg";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 506>,
+ <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>,
+ <&cpg 1008>, <&cpg 1009>,
+ <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>,
+ <&cpg 1014>, <&cpg 1015>,
+ <&cpg 502>,
+ <&cpg 922>;
+ reset-names = "adsp",
+ "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "audmac.0",
+ "adg";
+ status = "disabled";
+ };
+
+ xhci0: usb@ee000000 {
+ compatible = "renesas,xhci-r8a77990",
+ "renesas,rcar-gen3-xhci";
+ reg = <0 0xee000000 0 0xc00>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
+ status = "disabled";
+ };
+
+ usb3_peri0: usb@ee020000 {
+ compatible = "renesas,r8a77990-usb3-peri",
+ "renesas,rcar-gen3-usb3-peri";
+ reg = <0 0xee020000 0 0x400>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 328>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 328>;
+ status = "disabled";
+ };
+
+ ohci0: usb@ee080000 {
+ compatible = "generic-ohci";
+ reg = <0 0xee080000 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 703>, <&cpg 704>;
+ status = "disabled";
+ };
+
+ ehci0: usb@ee080100 {
+ compatible = "generic-ehci";
+ reg = <0 0xee080100 0 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 703>, <&cpg 704>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@ee080200 {
+ compatible = "renesas,usb2-phy-r8a77990",
+ "renesas,rcar-gen3-usb2-phy";
+ reg = <0 0xee080200 0 0x700>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 703>, <&cpg 704>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a77990",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0 0xee100000 0 0x2000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ max-frequency = <200000000>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
+
+ sdhi1: sd@ee120000 {
+ compatible = "renesas,sdhi-r8a77990",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0 0xee120000 0 0x2000>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 313>;
+ max-frequency = <200000000>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 313>;
+ status = "disabled";
+ };
+
+ sdhi3: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a77990",
+ "renesas,rcar-gen3-sdhi";
+ reg = <0 0xee160000 0 0x2000>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ max-frequency = <200000000>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
@@ -258,11 +1631,328 @@
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&cpg CPG_MOD 408>;
- clock-names = "clk";
- power-domains = <&sysc 32>;
- resets = <&cpg 408>;
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ };
+
+ gsx: gsx@fd000000 {
+ compatible = "renesas,gsx";
+ reg = <0 0xfd000000 0 0x40000>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 112>;
+ operating-points-v2 = <&gsx_opp_table>;
+ power-domains = <&sysc R8A77990_PD_3DG_B>;
+ resets = <&cpg 112>;
+ };
+
+ pciec0: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a77990",
+ "renesas,pcie-rcar-gen3";
+ reg = <0 0xfe000000 0 0x80000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
+ };
+
+ fcpcs: vcp4@fe90f000 {
+ compatible = "renesas,vcp4-fcpcs";
+ reg = <0 0xfe90f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 619>;
+ power-domains = <&sysc R8A77990_PD_A3VC>;
+ resets = <&cpg 619>;
+ renesas,#ch = <0>;
+ };
+
+ vcplf: vcp4@fe910000 {
+ compatible = "renesas,vcp4-vcplf";
+ reg = <0 0xfe910000 0 0x200>, <0 0xfe910200 0 0x200>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 130>;
+ power-domains = <&sysc R8A77990_PD_A2VC1>;
+ resets = <&cpg 130>;
+ renesas,#ch = <0>;
+ renesas,#fcp_ch = <0>;
+ };
+
+ vdpb: vcp4@fe900000 {
+ compatible = "renesas,vcp4-vdpb";
+ reg = <0 0xfe900000 0 0x200>, <0 0xfe900200 0 0x200>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 131>;
+ power-domains = <&sysc R8A77990_PD_A2VC1>;
+ resets = <&cpg 131>;
+ renesas,#ch = <1>;
+ renesas,#fcp_ch = <0>;
+ };
+
+ fdp0: fdpm@fe940000 {
+ compatible = "renesas,fdpm";
+ reg = <0 0xfe940000 0 0x2400>, <0 0xfe950000 0 0x200>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 119>, <&cpg CPG_MOD 615>;
+ clock-names = "fdp", "fcp";
+ power-domains = <&sysc R8A77990_PD_A3VC>;
+ resets = <&cpg 119>, <&cpg 615>;
+ reset-names = "fdp", "fcp";
+ renesas,#ch = <0>;
+ };
+
+ fcpvd0: fcp@fea27000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea27000 0 0x200>;
+ clocks = <&cpg CPG_MOD 603>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 603>;
+ };
+
+ fcpvd1: fcp@fea2f000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfea2f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 602>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 602>;
+ };
+
+ vsp@fe960000 {
+ compatible = "renesas,vspm-vsp2";
+ reg = <0 0xfe960000 0 0x8000>;
+ renesas,has-bru;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hgo;
+ renesas,#rpf = <5>;
+ renesas,#uds = <0>;
+ renesas,#wpf = <1>;
+ };
+
+ vspb: vspm@fe960000 {
+ compatible = "renesas,vspm";
+ reg = <0 0xfe960000 0 0x8000>, <0 0xfe96f000 0 0x200>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 626>, <&cpg CPG_MOD 607>;
+ clock-names = "vsp", "fcp";
+ renesas,#ch = <3>;
+ renesas,#rpf = <31>;
+ renesas,#rpf_clut = <6>;
+ renesas,#wpf_rot = <0>;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-bru;
+ renesas,has-hgo;
+ renesas,#read_outstanding = <0>;
+ renesas,#start_reservation = <2>;
+ power-domains = <&sysc R8A77990_PD_A3VC>;
+ resets = <&cpg 626>, <&cpg 607>;
+ reset-names = "vsp", "fcp";
+ status = "disabled";
+ };
+
+ vspd0: vsp@fea20000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea20000 0 0x4000>;
+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 623>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 623>;
+
+ renesas,fcp = <&fcpvd0>;
+ };
+
+ vspd1: vsp@fea28000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea28000 0 0x4000>;
+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 622>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 622>;
+
+ renesas,fcp = <&fcpvd1>;
+ };
+
+ vsp@fe9a0000 {
+ compatible = "renesas,vspm-vsp2";
+ reg = <0 0xfe9a0000 0 0x8000>;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hgo;
+ renesas,has-hgt;
+ renesas,#rpf = <1>;
+ renesas,#uds = <1>;
+ renesas,#wpf = <1>;
+ };
+
+ vspi0: vspm@fe9a0000 {
+ compatible = "renesas,vspm";
+ reg = <0 0xfe9a0000 0 0x8000>, <0 0xfe9af000 0 0x200>;
+ interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 631>, <&cpg CPG_MOD 611>;
+ clock-names = "vsp", "fcp";
+ renesas,#ch = <0>;
+ renesas,#rpf = <1>;
+ renesas,#rpf_clut = <1>;
+ renesas,#wpf_rot = <1>;
+ renesas,has-sru;
+ renesas,has-uds;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hst;
+ renesas,has-hsi;
+ renesas,has-hgo;
+ renesas,has-hgt;
+ renesas,has-shp;
+ renesas,#read_outstanding = <2>;
+ renesas,#start_reservation = <2>;
+ power-domains = <&sysc R8A77990_PD_A3VC>;
+ resets = <&cpg 631>, <&cpg 611>;
+ reset-names = "vsp", "fcp";
+ status = "disabled";
+ };
+
+ csi40: csi2@feaa0000 {
+ compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin4: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin4csi40>;
+ };
+ csi40vin5: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin5csi40>;
+ };
+ };
+ };
+ };
+
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a77990";
+ reg = <0 0xfeb00000 0 0x40000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>;
+ clock-names = "du.0", "du.1";
+ resets = <&cpg 724>,
+ <&cpg 724>;
+ reset-names = "du.0", "du.1";
+ vsps = <&vspd0 0 &vspd1 0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du_out_rgb: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ du_out_lvds0: endpoint {
+ remote-endpoint = <&lvds0_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ du_out_lvds1: endpoint {
+ remote-endpoint = <&lvds1_in>;
+ };
+ };
+ };
+ };
+
+ lvds0: lvds-encoder@feb90000 {
+ compatible = "renesas,r8a77990-lvds";
+ reg = <0 0xfeb90000 0 0x20>;
+ clocks = <&cpg CPG_MOD 727>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 727>;
+ status = "disabled";
+ renesas,id = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ lvds1: lvds-encoder@feb90100 {
+ compatible = "renesas,r8a77990-lvds";
+ reg = <0 0xfeb90100 0 0x20>;
+ clocks = <&cpg CPG_MOD 727>;
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 726>;
+ status = "disabled";
+ renesas,id = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds1_in: endpoint {
+ remote-endpoint = <&du_out_lvds1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lvds1_out: endpoint {
+ };
+ };
+ };
};
prr: chipid@fff00044 {
@@ -271,11 +1961,55 @@
};
};
+ thermal-zones {
+ emergency {
+ polling-delay = <1000>;
+ on-temperature = <110000>;
+ off-temperature = <95000>;
+ target_cpus = <&a53_1>;
+ status = "disabled";
+ };
+
+ sensor_thermal1: sensor-thermal1 {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsc 0>;
+ sustainable-power = <717>;
+
+ trips {
+ threshold: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ target: trip-point1 {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ sensor1_crit: sensor1-crit {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&a53_0 0 2>;
+ contribution = <1024>;
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index 9d73de8..2e01b79 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Draak board
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
/dts-v1/;
@@ -27,9 +24,132 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_out: endpoint {
+ remote-endpoint = <&adv7511_out>;
+ };
+ };
+ };
+
+ lvds0-decoder {
+ compatible = "thine,thc63lvd1024";
+ vcc-supply = <®_3p3v>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ thc63lvd1024_in0: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ thc63lvd1024_out0: endpoint {
+ remote-endpoint = <&adv7511_in>;
+ };
+ };
+ };
+ };
+
+ lvds1-decoder {
+ compatible = "thine,thc63lvd1024";
+ vcc-supply = <®_3p3v>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ thc63lvd1024_in1: endpoint {
+ remote-endpoint = <&lvds1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ thc63lvd1024_out1: endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ };
+ };
+
+ lvds0 {
+ compatible = "panel-lvds";
+
+ width-mm = <210>;
+ height-mm = <158>;
+
+ data-mapping = "jeida-24";
+ enable-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>;
+
+ panel-timing {
+ /* 1024x768 @60Hz */
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hsync-len = <136>;
+ hfront-porch = <20>;
+ hback-porch = <160>;
+ vfront-porch = <3>;
+ vback-porch = <29>;
+ vsync-len = <6>;
+ };
+
+ port {
+ lvds0_panel_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ };
+
+ lvds1 {
+ compatible = "panel-lvds";
+
+ width-mm = <210>;
+ height-mm = <158>;
+
+ data-mapping = "jeida-24";
+ enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+
+ panel-timing {
+ /* 1024x768 @60Hz */
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hsync-len = <136>;
+ hfront-porch = <20>;
+ hback-porch = <160>;
+ vfront-porch = <3>;
+ vback-porch = <29>;
+ vsync-len = <6>;
+ };
+
+ port {
+ lvds1_panel_in: endpoint {
+ remote-endpoint = <&du_out_lvds1>;
+ };
+ };
+ };
+
vga {
compatible = "vga-connector";
+ no-use-ddc;
+
+ width = <800>;
+ height = <600>;
+ max-pixelclock = <50000>;
+
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
@@ -82,6 +202,12 @@
regulator-boot-on;
regulator-always-on;
};
+
+ x12_clk: x12 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
};
&extal_clk {
@@ -144,11 +270,83 @@
};
};
+&hsusb {
+ dr_mode = "host";
+ status = "okay";
+};
+
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
+ hdmi-encoder@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&thc63lvd1024_out0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con_out>;
+ };
+ };
+ };
+ };
+
+ adv7180@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
+ remote = <&vin4>;
+
+ port {
+ cvbs_in: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin4ep0>;
+ };
+ };
+ };
+
+ adv7612: adv7612@4c {
+ compatible = "adi,adv7612";
+ reg = <0x4c>;
+ remote = <&vin4>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ default-input = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+ port@1 {
+ reg = <1>;
+ hdmi_in: endpoint {
+ remote-endpoint = <&vin4ep0>;
+ };
+
+ };
+ };
+
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
@@ -162,25 +360,57 @@
status = "okay";
};
-&du {
- pinctrl-0 = <&du_pins>;
- pinctrl-names = "default";
+&lvds0 {
status = "okay";
+ clocks = <&cpg CPG_MOD 727>,
+ <&x12_clk>,
+ <&extal_clk>;
+ clock-names = "fck", "dclkin.0", "extal";
+
ports {
- port@0 {
- endpoint {
- remote-endpoint = <&adv7123_in>;
+ port@1 {
+ lvds0_out: endpoint {
+ remote-endpoint = <&thc63lvd1024_in0>;
};
};
};
};
+&lvds1 {
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 727>,
+ <&extal_clk>;
+ clock-names = "fck", "extal";
+
+ ports {
+ port@1 {
+ lvds1_out: endpoint {
+ remote-endpoint = <&thc63lvd1024_in1>;
+ };
+ };
+ };
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&x12_clk>;
+ clock-names = "du.0", "du.1", "dclkin.0";
+};
+
&ehci0 {
+ dr_mode = "host";
status = "okay";
};
&ohci0 {
+ dr_mode = "host";
status = "okay";
};
@@ -189,7 +419,7 @@
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
- phy-mode = "rgmii-txid";
+ phy-mode = "rgmii";
status = "okay";
phy0: ethernet-phy@0 {
@@ -225,6 +455,7 @@
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
+ renesas,no-otg-pins;
status = "okay";
};
@@ -246,3 +477,23 @@
timeout-sec = <60>;
status = "okay";
};
+
+&vin4 {
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin4ep0: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ bus-width = <8>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ };
+ };
+};
+
+&vspbs {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 2506f46..f0a8585 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Device Tree Source for the r8a77995 SoC
+ * Device Tree Source for the R-Car D3 (R8A77995) SoC
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
@@ -307,6 +304,51 @@
status = "disabled";
};
+ hsusb: usb@e6590000 {
+ compatible = "renesas,usbhs-r8a77995",
+ "renesas,rcar-gen3-usbhs";
+ reg = <0 0xe6590000 0 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
+ dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
+ <&usb_dmac1 0>, <&usb_dmac1 1>;
+ dma-names = "ch0", "ch1", "ch2", "ch3";
+ renesas,buswait = <11>;
+ phys = <&usb2_phy0>;
+ phy-names = "usb";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 704>, <&cpg 703>;
+ status = "disabled";
+ };
+
+ usb_dmac0: dma-controller@e65a0000 {
+ compatible = "renesas,r8a77995-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65a0000 0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 330>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 330>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
+ usb_dmac1: dma-controller@e65b0000 {
+ compatible = "renesas,r8a77995-usb-dmac",
+ "renesas,usb-dmac";
+ reg = <0 0xe65b0000 0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1";
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ #dma-cells = <1>;
+ dma-channels = <2>;
+ };
+
canfd: can@e66c0000 {
compatible = "renesas,r8a77995-canfd",
"renesas,rcar-gen3-canfd";
@@ -621,15 +663,49 @@
status = "disabled";
};
+ audma0: dma-controller@ec700000 {
+ compatible = "renesas,dmac-r8a77995",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
ohci0: usb@ee080000 {
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 703>, <&cpg 704>;
status = "disabled";
};
@@ -637,12 +713,12 @@
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
phys = <&usb2_phy0>;
phy-names = "usb";
companion = <&ohci0>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 703>, <&cpg 704>;
status = "disabled";
};
@@ -651,9 +727,9 @@
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 703>;
+ resets = <&cpg 703>, <&cpg 704>;
#phy-cells = <0>;
status = "disabled";
};
@@ -687,19 +763,42 @@
resets = <&cpg 408>;
};
- vspbs: vsp@fe960000 {
- compatible = "renesas,vsp2";
+ qos@e67e0000 {
+ compatible = "renesas,qos";
+ reg = <0 0xe67e0000 0 0x10090>;
+ };
+
+ vsp@fe960000 {
+ compatible = "renesas,vspm-vsp2";
reg = <0 0xfe960000 0 0x8000>;
+ renesas,has-brs;
+ renesas,#rpf = <2>;
+ renesas,#uds = <0>;
+ renesas,#wpf = <1>;
+ };
+
+ vspbs: vspm@fe960000 {
+ compatible = "renesas,vspm";
+ reg = <0 0xfe960000 0 0x8000>, <0 0xfe96f000 0 0x200>;
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 627>;
+ clocks = <&cpg CPG_MOD 627>, <&cpg CPG_MOD 607>;
+ clock-names = "vsp", "fcp";
+ renesas,#ch = <3>;
+ renesas,#rpf = <3>;
+ renesas,#rpf_clut = <3>;
+ renesas,#wpf_rot = <0>;
+ renesas,has-brs;
+ renesas,#read_outstanding = <0>;
+ renesas,#start_reservation = <2>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 627>;
- renesas,fcp = <&fcpvb0>;
+ resets = <&cpg 627>, <&cpg 607>;
+ reset-names = "vsp", "fcp";
+ status = "disabled";
};
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x8000>;
+ reg = <0 0xfea20000 0 0x5000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
@@ -709,7 +808,7 @@
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x8000>;
+ reg = <0 0xfea28000 0 0x5000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
@@ -717,15 +816,6 @@
renesas,fcp = <&fcpvd1>;
};
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
- power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
- resets = <&cpg 607>;
- iommus = <&ipmmu_vp0 5>;
- };
-
fcpvd0: fcp@fea27000 {
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
@@ -746,12 +836,15 @@
du: display@feb00000 {
compatible = "renesas,du-r8a77995";
- reg = <0 0xfeb00000 0 0x80000>;
+ reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
+ resets = <&cpg 724>,
+ <&cpg 724>;
+ reset-names = "du.0", "du.1";
vsps = <&vspd0 0 &vspd1 0>;
status = "disabled";
@@ -768,12 +861,70 @@
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
+ remote-endpoint = <&lvds0_in>;
};
};
port@2 {
reg = <2>;
du_out_lvds1: endpoint {
+ remote-endpoint = <&lvds1_in>;
+ };
+ };
+ };
+ };
+
+ lvds0: lvds-encoder@feb90000 {
+ compatible = "renesas,r8a77995-lvds";
+ reg = <0 0xfeb90000 0 0x20>;
+ clocks = <&cpg CPG_MOD 727>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 727>;
+ status = "disabled";
+ renesas,id = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ lvds1: lvds-encoder@feb90100 {
+ compatible = "renesas,r8a77995-lvds";
+ reg = <0 0xfeb90100 0 0x20>;
+ clocks = <&cpg CPG_MOD 727>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 726>;
+ status = "disabled";
+ renesas,id = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds1_in: endpoint {
+ remote-endpoint = <&du_out_lvds1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lvds1_out: endpoint {
};
};
};
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 9256fba..922b9cc 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for common parts of Salvator-X board variants
*
- * Copyright (C) 2015-2016 Renesas Electronics Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
+ * Copyright (C) 2015-2017 Renesas Electronics Corp.
*/
/*
@@ -55,6 +52,16 @@
clock-frequency = <12288000>;
};
+ avb-mch@ec5a0100 {
+ compatible = "renesas,avb-mch-gen3";
+ reg = <0 0xec5a0100 0 0x100>; /* ADG_AVB */
+ reg-name = "adg_avb";
+
+ clocks = <&cpg CPG_MOD 922>;
+ clock-names = "adg";
+ resets = <&cpg 922>;
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000>;
@@ -89,6 +96,35 @@
};
};
+ lvds {
+ compatible = "panel-lvds";
+
+ width-mm = <210>;
+ height-mm = <158>;
+
+ data-mapping = "jeida-24";
+ enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+
+ panel-timing {
+ /* 1024x768 @60Hz */
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hsync-len = <136>;
+ hfront-porch = <20>;
+ hback-porch = <160>;
+ vfront-porch = <3>;
+ vback-porch = <29>;
+ vsync-len = <6>;
+ };
+
+ port {
+ lvds_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@@ -207,6 +243,8 @@
vga {
compatible = "vga-connector";
+ no-use-ddc;
+ max-pixelclock = <100000>;
port {
vga_in: endpoint {
@@ -263,6 +301,10 @@
};
};
+&a57_0 {
+ cpu-supply = <&dvfs>;
+};
+
&audio_clk_a {
clock-frequency = <22579200>;
};
@@ -341,6 +383,14 @@
clock-frequency = <32768>;
};
+&hscif1 {
+ pinctrl-0 = <&hscif1_pins>;
+ pinctrl-names = "default";
+
+ /* Please use exclusively to the scif1 node */
+ /* status = "okay"; */
+};
+
&hsusb {
dr_mode = "otg";
status = "okay";
@@ -440,7 +490,7 @@
};
};
- port@10 {
+ port@a {
reg = <10>;
adv7482_txa: endpoint {
@@ -450,7 +500,7 @@
};
};
- port@11 {
+ port@b {
reg = <11>;
adv7482_txb: endpoint {
@@ -465,6 +515,8 @@
&i2c_dvfs {
status = "okay";
+ clock-frequency = <400000>;
+
pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
@@ -498,6 +550,10 @@
};
};
+&lvds0 {
+ status = "okay";
+};
+
&ohci0 {
dr_mode = "otg";
status = "okay";
@@ -546,6 +602,11 @@
function = "du";
};
+ hscif1_pins: hscif1 {
+ groups = "hscif1_data_a", "hscif1_ctrl_a";
+ function = "hscif1";
+ };
+
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
@@ -561,6 +622,11 @@
function = "pwm1";
};
+ pwm2_pins: pwm2 {
+ groups = "pwm2_a";
+ function = "pwm2";
+ };
+
scif1_pins: scif1 {
groups = "scif1_data_a", "scif1_ctrl";
function = "scif1";
@@ -589,13 +655,13 @@
};
sdhi2_pins: sd2 {
- groups = "sdhi2_data8", "sdhi2_ctrl";
+ groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
- groups = "sdhi2_data8", "sdhi2_ctrl";
+ groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
function = "sdhi2";
power-source = <1800>;
};
@@ -658,6 +724,13 @@
status = "okay";
};
+&pwm2 {
+ pinctrl-0 = <&pwm2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
@@ -691,7 +764,10 @@
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
rsnd_port0: port@0 {
+ reg = <0>;
rsnd_endpoint0: endpoint {
remote-endpoint = <&ak4613_endpoint>;
@@ -706,11 +782,17 @@
};
};
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
+ /* Please use exclusively to the hscif1 node */
status = "okay";
};
@@ -736,6 +818,7 @@
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
@@ -749,6 +832,7 @@
vqmmc-supply = <®_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
@@ -765,6 +849,7 @@
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
bus-width = <4>;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
@@ -838,11 +923,6 @@
status = "okay";
};
-&wdt0 {
- timeout-sec = <60>;
- status = "okay";
-};
-
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/salvator-x.dtsi b/arch/arm64/boot/dts/renesas/salvator-x.dtsi
index 468868c..ddee50e 100644
--- a/arch/arm64/boot/dts/renesas/salvator-x.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-x.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X board
*
* Copyright (C) 2015-2016 Renesas Electronics Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include "salvator-common.dtsi"
@@ -20,6 +17,8 @@
};
&i2c4 {
+ clock-frequency = <400000>;
+
versaclock5: clock-generator@6a {
compatible = "idt,5p49v5923";
reg = <0x6a>;
diff --git a/arch/arm64/boot/dts/renesas/salvator-xs.dtsi b/arch/arm64/boot/dts/renesas/salvator-xs.dtsi
index bf4d200..717d427 100644
--- a/arch/arm64/boot/dts/renesas/salvator-xs.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-xs.dtsi
@@ -1,11 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Salvator-X 2nd version board
*
* Copyright (C) 2015-2017 Renesas Electronics Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include "salvator-common.dtsi"
@@ -20,6 +17,8 @@
};
&i2c4 {
+ clock-frequency = <400000>;
+
versaclock6: clock-generator@6a {
compatible = "idt,5p49v6901";
reg = <0x6a>;
diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index a4e715c..1b316d79 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Kingfisher (ULCB extension) board
*
* Copyright (C) 2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
/ {
@@ -130,7 +127,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
- reset-gpios= <&gpio3 15 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 0edb16e..b60fd45 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the R-Car Gen3 ULCB board
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2016 Cogent Embedded, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
*/
#include <dt-bindings/gpio/gpio.h>
@@ -21,6 +18,7 @@
};
chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
@@ -34,6 +32,17 @@
clock-frequency = <12288000>;
};
+ avb-mch@ec5a0100 {
+ compatible = "renesas,avb-mch-gen3";
+ reg = <0 0xec5a0100 0 0x100>; /* ADG_AVB */
+ reg-name = "adg_avb";
+
+ clocks = <&cpg CPG_MOD 922>;
+ clock-names = "adg";
+ resets = <&cpg 922>;
+ reset-names = "adg";
+ };
+
hdmi0-out {
compatible = "hdmi-connector";
type = "a";
@@ -85,20 +94,12 @@
regulator-always-on;
};
- rsnd_ak4613: sound {
- compatible = "simple-audio-card";
+ sound_card: sound {
+ compatible = "audio-graph-card";
- simple-audio-card,format = "left_j";
- simple-audio-card,bitclock-master = <&sndcpu>;
- simple-audio-card,frame-master = <&sndcpu>;
+ label = "rcar-sound";
- sndcpu: simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
-
- sndcodec: simple-audio-card,codec {
- sound-dai = <&ak4613>;
- };
+ dais = <&rsnd_port0>;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
@@ -158,6 +159,10 @@
};
};
+&a57_0 {
+ cpu-supply = <&dvfs>;
+};
+
&du {
status = "okay";
};
@@ -213,6 +218,12 @@
asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end;
+
+ port {
+ ak4613_endpoint: endpoint {
+ remote-endpoint = <&rsnd_endpoint0>;
+ };
+ };
};
cs2000: clk-multiplier@4f {
@@ -244,6 +255,8 @@
&i2c_dvfs {
status = "okay";
+ clock-frequency = <400000>;
+
pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
@@ -330,13 +343,13 @@
};
sdhi2_pins: sd2 {
- groups = "sdhi2_data8", "sdhi2_ctrl";
+ groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
- groups = "sdhi2_data8", "sdhi2_ctrl";
+ groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
function = "sdhi2";
power-source = <1800>;
};
@@ -390,14 +403,30 @@
<&audio_clk_c>,
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
- rcar_sound,dai {
- dai0 {
- playback = <&ssi0 &src0 &dvc0>;
- capture = <&ssi1 &src1 &dvc1>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ rsnd_port0: port@0 {
+ reg = <0>;
+ rsnd_endpoint0: endpoint {
+ remote-endpoint = <&ak4613_endpoint>;
+
+ dai-format = "left_j";
+ bitclock-master = <&rsnd_endpoint0>;
+ frame-master = <&rsnd_endpoint0>;
+
+ playback = <&ssi0 &src0 &dvc0>;
+ capture = <&ssi1 &src1 &dvc1>;
+ };
};
};
};
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
@@ -419,6 +448,7 @@
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
@@ -432,6 +462,7 @@
vqmmc-supply = <®_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
non-removable;
status = "okay";
};
@@ -446,8 +477,3 @@
status = "okay";
};
-
-&wdt0 {
- timeout-sec = <60>;
- status = "okay";
-};