drivers/thermal/rcar_gen3_thermal.c

/*
 *  R-Car Gen3 THS thermal sensor driver
 *  Based on rcar_thermal.c and work from Hien Dang and Khiem Nguyen.
 *
 * Copyright (C) 2016 Renesas Electronics Corporation.
 * Copyright (C) 2016 Sang Engineering
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; version 2 of the License.
 *
 *  This program is distributed in the hope that it will be useful, but
 *  WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  General Public License for more details.
 *
 */
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
#include <linux/sys_soc.h>
#include <linux/thermal.h>
#include <linux/of.h>

#include "thermal_core.h"

/* Register offsets */
#define REG_GEN3_IRQSTR		0x04
#define REG_GEN3_IRQMSK		0x08
#define REG_GEN3_IRQCTL		0x0C
#define REG_GEN3_IRQEN		0x10
#define REG_GEN3_IRQTEMP1	0x14
#define REG_GEN3_IRQTEMP2	0x18
#define REG_GEN3_IRQTEMP3	0x1C
#define REG_GEN3_CTSR		0x20
#define REG_GEN3_THCTR		0x20
#define REG_GEN3_TEMP		0x28
#define REG_GEN3_THCODE1	0x50
#define REG_GEN3_THCODE2	0x54
#define REG_GEN3_THCODE3	0x58

/* FUSE register base and offsets */
#define PTAT_BASE               0xE6198000
#define REG_GEN3_PTAT1          0x5C
#define REG_GEN3_PTAT2          0x60
#define REG_GEN3_PTAT3          0x64
#define REG_GEN3_THSCP          0x68
#define REG_GEN3_MAX_SIZE       (REG_GEN3_THSCP + 0x4)

/* IRQ{STR,MSK,EN} bits */
#define IRQ_TEMP1		BIT(0)
#define IRQ_TEMP2		BIT(1)
#define IRQ_TEMP3		BIT(2)
#define IRQ_TEMPD1		BIT(3)
#define IRQ_TEMPD2		BIT(4)
#define IRQ_TEMPD3		BIT(5)

/* THSCP bit */
#define COR_PARA_VLD            (0x3 << 14)

/* CTSR bits */
#define CTSR_PONM	BIT(8)
#define CTSR_AOUT	BIT(7)
#define CTSR_THBGR	BIT(5)
#define CTSR_VMEN	BIT(4)
#define CTSR_VMST	BIT(1)
#define CTSR_THSST	BIT(0)

/* THCTR bits */
#define THCTR_PONM	BIT(6)
#define THCTR_THSST	BIT(0)

#define CTEMP_MASK	0xFFF

#define MCELSIUS(temp)	((temp) * 1000)
#define GEN3_FUSE_MASK	0xFFF

#define TSC_MAX_NUM	3

/** [ -------- Definition for thermal type b (Chapter B) **/
/* Define thermal device type */
#define RCAR_GEN3_THS_TYPE_A	1
#define RCAR_GEN3_THS_TYPE_B	0

#define is_ths_typeA	(ths_type == RCAR_GEN3_THS_TYPE_A)

/* Define registers and values for thermal device type B */
#define REG_GEN3_B_STR		0x000
#define REG_GEN3_B_ENR		0x004
#define REG_GEN3_B_INT_MASK	0x00C
#define REG_GEN3_B_POSNEG	0x120
#define REG_GEN3_B_THSCR	0x12C
#define REG_GEN3_B_THSSR	0x130
#define REG_GEN3_B_INTCTRL	0x134

/* ENR */
#define ENR_Tj00		BIT(0)
#define ENR_Tj01		BIT(1)

/* THSCR */
#define THSCR_CPCTL		BIT(12)

/* THSSR */
#define CTEMP_B_MASK	GENMASK(5, 0)

/* INTCTRL */
#define CTEMP0_B_MASK	GENMASK(5, 0)
#define CTEMP1_B_MASK	GENMASK(13, 8)

/* -------------------------------------------------------]*/
static unsigned int ths_type;
static int ths_tj;
static int tj_2;

/* default THCODE values if FUSEs are missing */
static int thcode[TSC_MAX_NUM][3] = {
	{ 3397, 2800, 2221 },
	{ 3393, 2795, 2216 },
	{ 3389, 2805, 2237 },
};

/* Structure for thermal temperature calculation */
struct equation_coefs {
	int a1;
	int b1;
	int a2;
	int b2;
};

struct rcar_gen3_thermal_tsc {
	void __iomem *base;
	struct thermal_zone_device *zone;
	struct equation_coefs coef;
	bool irq_cap;
	int id; /* thermal channel id */
};

struct rcar_gen3_thermal_priv {
	struct rcar_gen3_thermal_tsc *tscs[TSC_MAX_NUM];
	unsigned int num_tscs;
	spinlock_t lock; /* Protect interrupts on and off */
	void (*thermal_init)(struct rcar_gen3_thermal_tsc *tsc);
};

static inline u32 rcar_gen3_thermal_read(struct rcar_gen3_thermal_tsc *tsc,
					 u32 reg)
{
	return ioread32(tsc->base + reg);
}

static inline void rcar_gen3_thermal_write(struct rcar_gen3_thermal_tsc *tsc,
					   u32 reg, u32 data)
{
	iowrite32(data, tsc->base + reg);
}

/*
 * Linear approximation for temperature
 *
 * [reg] = [temp] * a + b => [temp] = ([reg] - b) / a
 *
 * The constants a and b are calculated using two triplets of int values PTAT
 * and THCODE. PTAT and THCODE can either be read from hardware or use hard
 * coded values from driver. The formula to calculate a and b are taken from
 * BSP and sparsely documented and understood.
 *
 * Examining the linear formula and the formula used to calculate constants a
 * and b while knowing that the span for PTAT and THCODE values are between
 * 0x000 and 0xfff the largest integer possible is 0xfff * 0xfff == 0xffe001.
 * Integer also needs to be signed so that leaves 7 bits for binary
 * fixed point scaling.
 */

#define FIXPT_SHIFT 7
#define FIXPT_INT(_x) ((_x) << FIXPT_SHIFT)
#define INT_FIXPT(_x) ((_x) >> FIXPT_SHIFT)
#define FIXPT_DIV(_a, _b) DIV_ROUND_CLOSEST(((_a) << FIXPT_SHIFT), (_b))
#define FIXPT_TO_MCELSIUS(_x) ((_x) * 1000 >> FIXPT_SHIFT)

#define RCAR3_THERMAL_GRAN 500 /* mili Celsius */

/* no idea where these constants come from */
#define THS_TJ_1	126 /* Use for H3 and M3N */
#define THS_TJ_1_M3	116 /* Use for M3 */

#define TJ_1 (ths_tj)		/* Tj_H: Contain THS_TJ_1 or THS_TJ_1_M3 */
#define TJ_2 (INT_FIXPT(tj_2))	/* Tj_T */
#define TJ_3 -41		/* Tj_L */

static void rcar_gen3_thermal_calc_coefs(struct equation_coefs *coef,
					 int *ptat, int *thcode)
{
	/* TODO: Find documentation and document constant calculation formula */

	/*
	 * Division is not scaled in BSP and if scaled it might overflow
	 * the dividend (4095 * 4095 << 14 > INT_MAX) so keep it unscaled
	 */
	tj_2 = (FIXPT_INT((ptat[1] - ptat[2]) * (TJ_1 - TJ_3))
		/ (ptat[0] - ptat[2])) + FIXPT_INT(TJ_3);

	coef->a1 = FIXPT_DIV(FIXPT_INT(thcode[1] - thcode[2]),
			     tj_2 - FIXPT_INT(TJ_3));
	coef->b1 = FIXPT_INT(thcode[2]) - coef->a1 * TJ_3;

	coef->a2 = FIXPT_DIV(FIXPT_INT(thcode[1] - thcode[0]),
			     tj_2 - FIXPT_INT(TJ_1));
	coef->b2 = FIXPT_INT(thcode[0]) - coef->a2 * TJ_1;
}

static int rcar_gen3_thermal_round(int temp)
{
	int result, round_offs;

	round_offs = temp >= 0 ? RCAR3_THERMAL_GRAN / 2 :
		-RCAR3_THERMAL_GRAN / 2;
	result = (temp + round_offs) / RCAR3_THERMAL_GRAN;
	return result * RCAR3_THERMAL_GRAN;
}

static int rcar_gen3_thermal_convert_temp(struct rcar_gen3_thermal_tsc *tsc)
{
	int mcelsius = 0, val;
	long reg;

	if (is_ths_typeA) {
		/* Read register and convert to mili Celsius */

		/* Read register and convert value to signed variable type */
		reg = rcar_gen3_thermal_read(tsc, REG_GEN3_TEMP) & CTEMP_MASK;

		if (reg <= thcode[tsc->id][1])
			val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b1,
					tsc->coef.a1);
		else
			val = FIXPT_DIV(FIXPT_INT(reg) - tsc->coef.b2,
					tsc->coef.a2);

		mcelsius = rcar_gen3_thermal_round(FIXPT_TO_MCELSIUS(val));

	} else {
		int i;
		u32 old, new;

		reg = 0;
		old = ~0;
		for (i = 0; i < 128; i++) {
			/*
			 * As hardware description, it needs to wait 300us after
			 * changing comparator offset to get stable temperature.
			 */
			usleep_range(300, 350);
			new = rcar_gen3_thermal_read(tsc, REG_GEN3_B_THSSR)
						& CTEMP_B_MASK;

			if (new == old) {
				reg = new;
				break;
			}
			old = new;
		}
		/*
		 * As hardware description, there are 2 formulas to
		 * calculate temperature on E3 when CTEMP[5:0] is less than
		 * and greater or equal to 24.
		 */
		if (reg < 24)
			mcelsius = MCELSIUS(((reg * 55) - 720) / 10);
			/*
			 * Equal to mcelsius = MCELSIUS((reg * 5.5) - 72)
			 * to avoid mismatch between float and integer
			 */
		else
			mcelsius = MCELSIUS((reg * 5) - 60);
	}

	return mcelsius;
}

static int rcar_gen3_thermal_get_temp(void *devdata, int *temp)
{
	struct rcar_gen3_thermal_tsc *tsc = devdata;
	int mcelsius;

	mcelsius = rcar_gen3_thermal_convert_temp(tsc);

	/* Make sure we are inside specifications */
	if ((mcelsius < MCELSIUS(-40)) || (mcelsius > MCELSIUS(125)))
		return -EIO;

	*temp = mcelsius;

	return 0;
}

static int rcar_gen3_thermal_mcelsius_to_temp(struct rcar_gen3_thermal_tsc *tsc,
					      int mcelsius)
{
	int celsius, val;
	int ctemp = 0;

	celsius = DIV_ROUND_CLOSEST(mcelsius, 1000);
	if (is_ths_typeA) {
		if (celsius <= TJ_2)
			val = celsius * tsc->coef.a1 + tsc->coef.b1;
		else
			val = celsius * tsc->coef.a2 + tsc->coef.b2;

		ctemp = INT_FIXPT(val);
	} else {
		/*
		 * Similarly, to calculate register CTEMP[5:0] for E3
		 * there are 2 formulas to measure CTEMP[5:0] which is
		 * depending on temperature changes from less than
		 * to greater or equal to 60 degrees celsius.
		 */
		if (celsius < 60)
			ctemp = (celsius + 72) * 10  / 55;
			/*
			 * Equal to ctemp = (celsius + 72) / 5.5
			 * to avoid mismatch between float and integer
			 */
		else
			ctemp = (celsius + 60) / 5;
	}

	return ctemp;
}

static int rcar_gen3_thermal_set_irq_temp(struct rcar_gen3_thermal_tsc *tsc)
{
	int mcelsius, low, high;

	if (!tsc->irq_cap)
		return 0;

	mcelsius = rcar_gen3_thermal_convert_temp(tsc);

	low = mcelsius - MCELSIUS(1);
	high = mcelsius + MCELSIUS(1);

	if (is_ths_typeA) {
		rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP1,
			rcar_gen3_thermal_mcelsius_to_temp(tsc, low));

		rcar_gen3_thermal_write(tsc, REG_GEN3_IRQTEMP2,
			rcar_gen3_thermal_mcelsius_to_temp(tsc, high));
	} else {
		u32 reg;

		low = rcar_gen3_thermal_mcelsius_to_temp(tsc, low);
		high = rcar_gen3_thermal_mcelsius_to_temp(tsc, high);
		reg = rcar_gen3_thermal_read(tsc, REG_GEN3_B_INTCTRL);
		reg &= (~CTEMP1_B_MASK & ~CTEMP0_B_MASK);
		reg |= (high << __bf_shf(CTEMP1_B_MASK)
		    | low << __bf_shf(CTEMP0_B_MASK));
		rcar_gen3_thermal_write(tsc, REG_GEN3_B_INTCTRL, reg);
	}

	return 0;
}

static const struct thermal_zone_of_device_ops rcar_gen3_tz_of_ops = {
	.get_temp	= rcar_gen3_thermal_get_temp,
};

static void rcar_thermal_irq_set(struct rcar_gen3_thermal_priv *priv, bool on)
{
	unsigned int i;
	u32 val;

	if (is_ths_typeA) {
		for (i = 0; i < priv->num_tscs; i++) {
			val = (on && priv->tscs[i]->irq_cap) ?
			       IRQ_TEMPD1 | IRQ_TEMP2 : 0;
			rcar_gen3_thermal_write(priv->tscs[i],
				REG_GEN3_IRQMSK, val);
		}
	} else {
		for (i = 0; i < priv->num_tscs; i++) {
			val = (on && priv->tscs[i]->irq_cap) ?
				ENR_Tj00 | ENR_Tj01 : 0;
			rcar_gen3_thermal_write(priv->tscs[i],
				REG_GEN3_B_ENR, val);
		}
	}
}

static irqreturn_t rcar_gen3_thermal_irq(int irq, void *data)
{
	struct rcar_gen3_thermal_priv *priv = data;
	u32 status;
	int i, ret = IRQ_HANDLED;

	spin_lock(&priv->lock);

	if (is_ths_typeA) {
		for (i = 0; i < priv->num_tscs; i++) {
			status = rcar_gen3_thermal_read(priv->tscs[i],
							REG_GEN3_IRQSTR);
			rcar_gen3_thermal_write(priv->tscs[i],
						REG_GEN3_IRQSTR, 0);
			if (status)
				ret = IRQ_WAKE_THREAD;
		}
	} else {
		for (i = 0; i < priv->num_tscs; i++) {
			status = rcar_gen3_thermal_read(priv->tscs[i],
							REG_GEN3_B_STR);
			rcar_gen3_thermal_write(priv->tscs[i],
						REG_GEN3_B_STR, 0);
			if (status)
				ret = IRQ_WAKE_THREAD;
		}
	}

	if (ret == IRQ_WAKE_THREAD)
		rcar_thermal_irq_set(priv, false);

	spin_unlock(&priv->lock);

	return ret;
}

static irqreturn_t rcar_gen3_thermal_irq_thread(int irq, void *data)
{
	struct rcar_gen3_thermal_priv *priv = data;
	unsigned long flags;
	int i;

	for (i = 0; i < priv->num_tscs; i++) {
		rcar_gen3_thermal_set_irq_temp(priv->tscs[i]);
		thermal_zone_device_update(priv->tscs[i]->zone,
					   THERMAL_EVENT_UNSPECIFIED);
	}

	spin_lock_irqsave(&priv->lock, flags);
	rcar_thermal_irq_set(priv, true);
	spin_unlock_irqrestore(&priv->lock, flags);

	return IRQ_HANDLED;
}

static void rcar_gen3_thermal_init_r8a77990(struct rcar_gen3_thermal_tsc *tsc)
{
	/* Using 2 interrupts: Tj00 falling, Tj01 rising */
	rcar_gen3_thermal_write(tsc, REG_GEN3_B_POSNEG, 0x1);

	rcar_gen3_thermal_write(tsc, REG_GEN3_B_THSCR, THSCR_CPCTL |
		rcar_gen3_thermal_read(tsc, REG_GEN3_B_THSCR));

	usleep_range(300, 350);
	rcar_gen3_thermal_write(tsc, REG_GEN3_B_INT_MASK, 0x4 |
		(~0x7 & rcar_gen3_thermal_read(tsc, REG_GEN3_B_INT_MASK)));
}

static const struct soc_device_attribute r8a7795es1[] = {
	{ .soc_id = "r8a7795", .revision = "ES1.*" },
	{ /* sentinel */ }
};

static void rcar_gen3_thermal_init_r8a7795es1(struct rcar_gen3_thermal_tsc *tsc)
{
	rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR,  CTSR_THBGR);
	rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR,  0x0);

	usleep_range(1000, 2000);

	rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR, CTSR_PONM);

	rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F);
	rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0);
	rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, IRQ_TEMPD1 | IRQ_TEMP2);

	rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR,
				CTSR_PONM | CTSR_AOUT | CTSR_THBGR | CTSR_VMEN);

	usleep_range(100, 200);

	rcar_gen3_thermal_write(tsc, REG_GEN3_CTSR,
				CTSR_PONM | CTSR_AOUT | CTSR_THBGR | CTSR_VMEN |
				CTSR_VMST | CTSR_THSST);

	usleep_range(1000, 2000);
}

static void rcar_gen3_thermal_init(struct rcar_gen3_thermal_tsc *tsc)
{
	u32 reg_val;

	reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR);
	reg_val &= ~THCTR_PONM;
	rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val);

	usleep_range(1000, 2000);

	rcar_gen3_thermal_write(tsc, REG_GEN3_IRQCTL, 0x3F);
	rcar_gen3_thermal_write(tsc, REG_GEN3_IRQMSK, 0);
	rcar_gen3_thermal_write(tsc, REG_GEN3_IRQEN, IRQ_TEMPD1 | IRQ_TEMP2);

	reg_val = rcar_gen3_thermal_read(tsc, REG_GEN3_THCTR);
	reg_val |= THCTR_THSST;
	rcar_gen3_thermal_write(tsc, REG_GEN3_THCTR, reg_val);

	usleep_range(1000, 2000);
}

static const struct of_device_id rcar_gen3_thermal_dt_ids[] = {
	{ .compatible = "renesas,r8a7795-thermal", },
	{ .compatible = "renesas,r8a7796-thermal", },
	{ .compatible = "renesas,r8a77965-thermal", },
	{ .compatible = "renesas,r8a77990-thermal", },
	{ /*sentinel*/ },
};
MODULE_DEVICE_TABLE(of, rcar_gen3_thermal_dt_ids);

static int rcar_gen3_thermal_remove(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;

	pm_runtime_put(dev);
	pm_runtime_disable(dev);

	return 0;
}

static int rcar_gen3_thermal_probe(struct platform_device *pdev)
{
	struct rcar_gen3_thermal_priv *priv;
	struct device *dev = &pdev->dev;
	struct resource *res;
	struct thermal_zone_device *zone;
	int ret, irq, i;
	char *irqname;
	void __iomem *ptat_base;
	unsigned int cor_para_value = 0;
	struct device_node *tz_nd;

	/* default values if FUSEs are missing */
	int ptat[3] = { 2631, 1509, 435 };

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->thermal_init = rcar_gen3_thermal_init;
	if (soc_device_match(r8a7795es1))
		priv->thermal_init = rcar_gen3_thermal_init_r8a7795es1;

	if (!of_device_is_compatible(pdev->dev.of_node,
				"renesas,r8a77990-thermal")) {
		ths_type = RCAR_GEN3_THS_TYPE_A;

		if (!of_device_is_compatible(pdev->dev.of_node,
				"renesas,r8a7796-thermal"))
			ths_tj = THS_TJ_1;
		else
			ths_tj = THS_TJ_1_M3;
	} else {
		ths_type = RCAR_GEN3_THS_TYPE_B;
		priv->thermal_init = rcar_gen3_thermal_init_r8a77990;
	}

	if (is_ths_typeA) {
		/* Use FUSE default values if they are missing.
		 * If not, fetch them from registers.
		 */
		ptat_base = ioremap_nocache(PTAT_BASE, REG_GEN3_MAX_SIZE);
		if (!ptat_base) {
			dev_err(dev, "Cannot map FUSE register\n");
			return -ENOMEM;
		}

		cor_para_value = ioread32(ptat_base + REG_GEN3_THSCP)
					& COR_PARA_VLD;

		if (cor_para_value != COR_PARA_VLD) {
			dev_info(dev, "is using pseudo fixed FUSE values\n");
		} else {
			dev_info(dev, "is using FUSE values\n");
			ptat[0] = ioread32(ptat_base + REG_GEN3_PTAT1)
					& GEN3_FUSE_MASK;
			ptat[1] = ioread32(ptat_base + REG_GEN3_PTAT2)
					& GEN3_FUSE_MASK;
			ptat[2] = ioread32(ptat_base + REG_GEN3_PTAT3)
					& GEN3_FUSE_MASK;
		}

		iounmap(ptat_base);
	}

	spin_lock_init(&priv->lock);

	platform_set_drvdata(pdev, priv);

	/*
	 * Request 2 (of the 3 possible) IRQs, the driver only needs to
	 * to trigger on the low and high trip points of the current
	 * temp window at this point.
	 */
	for (i = 0; i < 2; i++) {
		irq = platform_get_irq(pdev, i);
		if (irq < 0)
			return irq;

		irqname = devm_kasprintf(dev, GFP_KERNEL, "%s:ch%d",
					 dev_name(dev), i);
		if (!irqname)
			return -ENOMEM;

		ret = devm_request_threaded_irq(dev, irq, rcar_gen3_thermal_irq,
						rcar_gen3_thermal_irq_thread,
						IRQF_SHARED, irqname, priv);
		if (ret)
			return ret;
	}

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);

	for (i = 0; i < TSC_MAX_NUM; i++) {
		struct rcar_gen3_thermal_tsc *tsc;

		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
		if (!res)
			break;

		tsc = devm_kzalloc(dev, sizeof(*tsc), GFP_KERNEL);
		if (!tsc) {
			ret = -ENOMEM;
			goto error_unregister;
		}

		tsc->base = devm_ioremap_resource(dev, res);
		if (IS_ERR(tsc->base)) {
			ret = PTR_ERR(tsc->base);
			goto error_unregister;
		}
		tsc->id = i;

		priv->tscs[i] = tsc;

		priv->thermal_init(tsc);

		if (is_ths_typeA) {
			if (cor_para_value == COR_PARA_VLD) {
				thcode[i][0] = rcar_gen3_thermal_read(tsc,
					REG_GEN3_THCODE1) & GEN3_FUSE_MASK;
				thcode[i][1] = rcar_gen3_thermal_read(tsc,
					REG_GEN3_THCODE2) & GEN3_FUSE_MASK;
				thcode[i][2] = rcar_gen3_thermal_read(tsc,
					REG_GEN3_THCODE3) & GEN3_FUSE_MASK;
			}

			rcar_gen3_thermal_calc_coefs(&tsc->coef,
					ptat, thcode[i]);
		}

		for_each_node_with_property(tz_nd, "polling-delay") {
			u32 zone_id, idle;

			if (of_parse_phandle(tz_nd, "thermal-sensors", 0)) {
				of_property_read_u32_index(tz_nd,
							   "thermal-sensors",
							   1, &zone_id);
				if (zone_id == i) {
					of_property_read_u32(tz_nd,
							     "polling-delay",
							     &idle);
					tsc->irq_cap = idle ? 0 : 1;
				}
			}
		}

		rcar_gen3_thermal_set_irq_temp(tsc);

		zone = devm_thermal_zone_of_sensor_register(dev, i, tsc,
							    &rcar_gen3_tz_of_ops);
		if (IS_ERR(zone)) {
			dev_err(dev, "Can't register thermal zone\n");
			ret = PTR_ERR(zone);
			goto error_unregister;
		}
		tsc->zone = zone;

		ret = of_thermal_get_ntrips(tsc->zone);
		if (ret < 0)
			goto error_unregister;

		dev_info(dev, "TSC%d: Loaded %d trip points\n", i, ret);
	}

	priv->num_tscs = i;

	if (!priv->num_tscs) {
		ret = -ENODEV;
		goto error_unregister;
	}

	rcar_thermal_irq_set(priv, true);

	return 0;

error_unregister:
	rcar_gen3_thermal_remove(pdev);

	return ret;
}

static int __maybe_unused rcar_gen3_thermal_suspend(struct device *dev)
{
	struct rcar_gen3_thermal_priv *priv = dev_get_drvdata(dev);

	rcar_thermal_irq_set(priv, false);

	return 0;
}

static int __maybe_unused rcar_gen3_thermal_resume(struct device *dev)
{
	struct rcar_gen3_thermal_priv *priv = dev_get_drvdata(dev);
	unsigned int i;

	for (i = 0; i < priv->num_tscs; i++) {
		struct rcar_gen3_thermal_tsc *tsc = priv->tscs[i];

		priv->thermal_init(tsc);
		rcar_gen3_thermal_set_irq_temp(tsc);
	}

	rcar_thermal_irq_set(priv, true);

	return 0;
}

static SIMPLE_DEV_PM_OPS(rcar_gen3_thermal_pm_ops, rcar_gen3_thermal_suspend,
			 rcar_gen3_thermal_resume);

static struct platform_driver rcar_gen3_thermal_driver = {
	.driver	= {
		.name	= "rcar_gen3_thermal",
		.pm = &rcar_gen3_thermal_pm_ops,
		.of_match_table = rcar_gen3_thermal_dt_ids,
	},
	.probe		= rcar_gen3_thermal_probe,
	.remove		= rcar_gen3_thermal_remove,
};
module_platform_driver(rcar_gen3_thermal_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("R-Car Gen3 THS thermal sensor driver");
MODULE_AUTHOR("Wolfram Sang <wsa+renesas@sang-engineering.com>");