tag 0d6a42d7820943579a840b0b2585afdf02d2b651
tagger Ryo Kataoka <ryo.kataoka.wt@renesas.com> Tue Sep 25 13:54:44 2018 +0900
object a259daf4b67ac3cee55ef4df7686128a108612f3

Sep. 25, 2018

commit a259daf4b67ac3cee55ef4df7686128a108612f3
author Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Wed Aug 22 21:28:01 2018 +0300
committer Ryo Kataoka <ryo.kataoka.wt@renesas.com> Tue Sep 25 13:52:46 2018 +0900
tree 664b91d64eee76e8e743e7db57fd152193047402
parent 65f0921ab7bc98b0b733902b2a2a5b8f31daa2b4

mmc: renesas_sdhi_internal_dmac: fix #define RST_RESERVED_BITS

The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 9faf870e559a710c44e747ba20383ea82d8ac5d2)
Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com>