)]}' { "log": [ { "commit": "1d76a004d3a19367669b861559c1fbbf546b3065", "tree": "2866db6fdd4b14f8a22207462788b32f55be4e63", "parents": [ "85722b9814d554c968dbf61e2b358941ced4d0b1", "49a5ffccf5c1dae09b52f71126a5bb4950fd38dd" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:16 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:16 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.4/dts-rcar-gen3.rc1\u0027 into v4.14.75-ltsi/rcar-3.9.6\n\n* rcar-3.9.4/dts-rcar-gen3.rc1:\n arm64: dts: r8a7796-salvator-xs-2x4g: Disable HS400\n" }, { "commit": "49a5ffccf5c1dae09b52f71126a5bb4950fd38dd", "tree": "2866db6fdd4b14f8a22207462788b32f55be4e63", "parents": [ "85722b9814d554c968dbf61e2b358941ced4d0b1" ], "author": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Thu Jul 11 20:49:39 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:15 2019 +0900" }, "message": "arm64: dts: r8a7796-salvator-xs-2x4g: Disable HS400\n\nIn R-Car M3 Ver.3.0, SDHI has HW restrictions on HS400 mode.\nTherefore, delete the \u0027mmc-hs400-1_8v\u0027 property and disable HS400 mode.\n\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "85722b9814d554c968dbf61e2b358941ced4d0b1", "tree": "c1ee604e06f6fcecbe389d6b78ecee66266bad31", "parents": [ "ce83585d886fe9e329492839bcff4fd06045634c", "6b92f96d09762a9fe172468ed302290cc4046318" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:14 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:14 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.4/thermal.rc1\u0027 into v4.14.75-ltsi/rcar-3.9.6\n\n* rcar-3.9.4/thermal.rc1:\n thermal: rcar_gen3_thermal: fix interrupt type\n thermal: rcar_gen3_thermal: Fix init value of IRQCTL register\n thermal: rcar_gen3_thermal: disable interrupt in .remove\n" }, { "commit": "6b92f96d09762a9fe172468ed302290cc4046318", "tree": "c1ee604e06f6fcecbe389d6b78ecee66266bad31", "parents": [ "39eee119052a1bb826bab60dcc5531ec34e3b4cf" ], "author": { "name": "Jiada Wang", "email": "jiada_wang@mentor.com", "time": "Wed Apr 24 14:11:44 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:14 2019 +0900" }, "message": "thermal: rcar_gen3_thermal: fix interrupt type\n\nCurrently IRQF_SHARED type interrupt line is allocated, but it\nis not appropriate, as the interrupt line isn\u0027t shared between\ndifferent devices, instead IRQF_ONESHOT is the proper type.\n\nBy changing interrupt type to IRQF_ONESHOT, now irq handler is\nno longer needed, as clear of interrupt status can be done in\nthreaded interrupt context.\n\nBecause IRQF_ONESHOT type interrupt line is kept disabled until\nthe threaded handler has been run, so there is no need to protect\nread/write of REG_GEN3_IRQSTR with lock.\n\nFixes: 7d4b269776ec6 (\"enable hardware interrupts for trip points\")\nSigned-off-by: Jiada Wang \u003cjiada_wang@mentor.com\u003e\nReviewed-by: Simon Horman \u003chorms+renesas@verge.net.au\u003e\nTested-by: Simon Horman \u003chorms+renesas@verge.net.au\u003e\nReviewed-by: Daniel Lezcano \u003cdaniel.lezcano@linaro.org\u003e\nSigned-off-by: Eduardo Valentin \u003cedubezval@gmail.com\u003e\n(cherry picked from commit 2c0928c9e004589dc9e7672c40a38d6c4ca12701)\nSigned-off-by: The Kinh Nguyen \u003cthe.nguyen.vx@renesas.com\u003e\n" }, { "commit": "39eee119052a1bb826bab60dcc5531ec34e3b4cf", "tree": "9aabfa6e801d8412625ec2c2fe43d8d6641e9d77", "parents": [ "1a76e02667ece64de603e392713215acc1c47ed4" ], "author": { "name": "Hoan Nguyen An", "email": "na-hoan@jinso.co.jp", "time": "Wed Mar 27 18:03:18 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:14 2019 +0900" }, "message": "thermal: rcar_gen3_thermal: Fix init value of IRQCTL register\n\nFix setting value for IRQCTL register. We are setting the last 6 bits\nof (IRQCTL) to be 1 (0x3f), this is only suitable for H3ES1.*, according\nto Hardware manual values 1 are \"setting prohibited\" for Gen3.\n\nSigned-off-by: Hoan Nguyen An \u003cna-hoan@jinso.co.jp\u003e\nAcked-by: Wolfram Sang \u003cwsa+renesas@sang-engineering.com\u003e\nReviewed-by: Geert Uytterhoeven \u003cgeert+renesas@glider.be\u003e\nSigned-off-by: Eduardo Valentin \u003cedubezval@gmail.com\u003e\n(cherry picked from commit ed1b1ac1425b3d4399553411f305ce12fb3a6c54)\nSigned-off-by: The Kinh Nguyen \u003cthe.nguyen.vx@renesas.com\u003e\n" }, { "commit": "1a76e02667ece64de603e392713215acc1c47ed4", "tree": "aee3b916f3ad1fadd09b04503b9f7e79e462fda3", "parents": [ "ce83585d886fe9e329492839bcff4fd06045634c" ], "author": { "name": "Jiada Wang", "email": "jiada_wang@mentor.com", "time": "Wed Apr 24 14:11:45 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:14 2019 +0900" }, "message": "thermal: rcar_gen3_thermal: disable interrupt in .remove\n\nCurrently IRQ remains enabled after .remove, later if device is probed,\nIRQ is requested before .thermal_init, this may cause IRQ function be\ncalled before device is initialized.\n\nthis patch disables interrupt in .remove, to ensure irq function\nonly be called after device is fully initialized.\n\nSigned-off-by: Jiada Wang \u003cjiada_wang@mentor.com\u003e\nReviewed-by: Simon Horman \u003chorms+renesas@verge.net.au\u003e\nReviewed-by: Daniel Lezcano \u003cdaniel.lezcano@linaro.org\u003e\nSigned-off-by: Eduardo Valentin \u003cedubezval@gmail.com\u003e\n(cherry picked from commit 63f55fcea50c25ae5ad45af92d08dae3b84534c2)\nSigned-off-by: The Kinh Nguyen \u003cthe.nguyen.vx@renesas.com\u003e\n" }, { "commit": "ce83585d886fe9e329492839bcff4fd06045634c", "tree": "aae082a6bb185b384f342e21aa478eae4ab40d1a", "parents": [ "45ba0548f01974501c695238a664ee9e555cf2bf", "0879b952e2d32b44af82362bb5433b018cec60de" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:12 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:12 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.4/ehci_ohci.rc1\u0027 into v4.14.75-ltsi/rcar-3.9.6\n\n* rcar-3.9.4/ehci_ohci.rc1:\n phy: rcar-gen3-usb2: Correct VBUS behavior at over-current\n" }, { "commit": "0879b952e2d32b44af82362bb5433b018cec60de", "tree": "aae082a6bb185b384f342e21aa478eae4ab40d1a", "parents": [ "45ba0548f01974501c695238a664ee9e555cf2bf" ], "author": { "name": "Kazuya Mizuguchi", "email": "kazuya.mizuguchi.ks@renesas.com", "time": "Wed May 22 09:54:53 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:12 2019 +0900" }, "message": "phy: rcar-gen3-usb2: Correct VBUS behavior at over-current\n\nWhen VBCTRL.OCCLREN is set, VBCTRL.VBOUT and ADPCTRL.DRVVBUS\nare automatically cleared when an over-current occurs.\nOn OTG channels, clearing these bits will turn off VBUS\nso device will appear to be disconnected on the bus.\nClearing VBCTRL.OCCLREN will resolve this issue by retaining VBUS status.\nUSB port is able to be recovered automatically and the device can be\nconnected again.\n\nSigned-off-by: Kazuya Mizuguchi \u003ckazuya.mizuguchi.ks@renesas.com\u003e\nSigned-off-by: Tho Vu \u003ctho.vu.wh@renesas.com\u003e\n" }, { "commit": "45ba0548f01974501c695238a664ee9e555cf2bf", "tree": "98157546907372a1840f3b02ec4f6ca9e6b9819b", "parents": [ "4498fec78778c999f9f0fb51085353541c1c0804", "e206eb5b81a60e64c35fbc3a999b1a0db2b98044" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:11 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:11 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.4/iommu-ipmmu-vmsa.rc2\u0027 into v4.14.75-ltsi/rcar-3.9.6\n\n* rcar-3.9.4/iommu-ipmmu-vmsa.rc2:\n iommu/ipmmu-vmsa: Remove cache snoop transaction for page table walk request\n" }, { "commit": "e206eb5b81a60e64c35fbc3a999b1a0db2b98044", "tree": "98157546907372a1840f3b02ec4f6ca9e6b9819b", "parents": [ "4498fec78778c999f9f0fb51085353541c1c0804" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri May 03 10:49:28 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:11 2019 +0900" }, "message": "iommu/ipmmu-vmsa: Remove cache snoop transaction for page table walk request\n\nAccording to Hardware Manual Errata on Apr. 10, 2019, cache snoop\ntransaction for page table walk request is not supported on R-Car Gen3.\n\nHence, this patch removes these fields since setting them up in IMTTBCR\nregister will have no effect.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "4498fec78778c999f9f0fb51085353541c1c0804", "tree": "aa41812c72d784f5d43959fbf00f2c9944530c02", "parents": [ "bf95bdcff0583d769cbb9e25fdba4664c20396de", "ad38f53513fa668f560d03d9486116cb7db965c4" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:09 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:09 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.4/sd_mmc.rc4\u0027 into v4.14.75-ltsi/rcar-3.9.6\n\n* rcar-3.9.4/sd_mmc.rc4:\n mmc: tmio: fix SCC error handling to avoid false positive CRC error\n" }, { "commit": "ad38f53513fa668f560d03d9486116cb7db965c4", "tree": "aa41812c72d784f5d43959fbf00f2c9944530c02", "parents": [ "bf95bdcff0583d769cbb9e25fdba4664c20396de" ], "author": { "name": "Takeshi Saito", "email": "takeshi.saito.xv@renesas.com", "time": "Wed May 15 20:23:46 2019 +0200" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:17:09 2019 +0900" }, "message": "mmc: tmio: fix SCC error handling to avoid false positive CRC error\n\nIf an SCC error occurs during a read/write command execution, a false\npositive CRC error message is output.\n\nmmcblk0: response CRC error sending r/w cmd command, card status 0x900\n\ncheck_scc_error() checks SCC_RVSREQ.RVSERR bit. RVSERR detects a\ncorrection error in the next (up or down) delay tap position. However,\nsince the command is successful, only retuning needs to be executed.\nThis has been confirmed by HW engineers.\n\nThus, on SCC error, set retuning flag instead of setting an error code.\n\nFixes: b85fb0a1c8ae (\"mmc: tmio: Fix SCC error detection\")\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\n[wsa: updated comment and commit message, removed some braces]\nSigned-off-by: Wolfram Sang \u003cwsa+renesas@sang-engineering.com\u003e\nReviewed-by: Simon Horman \u003chorms+renesas@verge.net.au\u003e\nReviewed-by: Yoshihiro Shimoda \u003cyoshihiro.shimoda.uh@renesas.com\u003e\nCc: stable@vger.kernel.org\nSigned-off-by: Ulf Hansson \u003culf.hansson@linaro.org\u003e\n(cherry picked from commit 51b72656bb39fdcb8f3174f4007bcc83ad1d275f)\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\n" }, { "commit": "bf95bdcff0583d769cbb9e25fdba4664c20396de", "tree": "09d3ab3bd83b945474b138ee3511998f486bb5c4", "parents": [ "9aa6649bb252b987708de0d2eba078ad3ef7aff4", "789115b49be1b6529a27d55c06e37aed45192dc4" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:15:18 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:15:18 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.4/dmae.rc1\u0027 into v4.14.75-ltsi/rcar-3.9.6\n\n* rcar-3.9.4/dmae.rc1:\n dmaengine: sh: rcar-dmac: With cyclic DMA residue 0 is valid\n Revert \"dmaengine: sh: rcar-dmac: With cyclic DMA residue 0 is valid\"\n" }, { "commit": "789115b49be1b6529a27d55c06e37aed45192dc4", "tree": "09d3ab3bd83b945474b138ee3511998f486bb5c4", "parents": [ "c5606c6416b587e3e5299e8140443369fa182116" ], "author": { "name": "Dirk Behme", "email": "dirk.behme@de.bosch.com", "time": "Fri Apr 12 07:29:13 2019 +0200" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:15:18 2019 +0900" }, "message": "dmaengine: sh: rcar-dmac: With cyclic DMA residue 0 is valid\n\nHaving a cyclic DMA, a residue 0 is not an indication of a completed\nDMA. In case of cyclic DMA make sure that dma_set_residue() is called\nand with this a residue of 0 is forwarded correctly to the caller.\n\nFixes: 3544d2878817 (\"dmaengine: rcar-dmac: use result of updated get_residue in tx_status\")\nSigned-off-by: Dirk Behme \u003cdirk.behme@de.bosch.com\u003e\nSigned-off-by: Achim Dahlhoff \u003cAchim.Dahlhoff@de.bosch.com\u003e\nSigned-off-by: Hiroyuki Yokoyama \u003chiroyuki.yokoyama.vx@renesas.com\u003e\nSigned-off-by: Yao Lihua \u003cylhuajnu@outlook.com\u003e\nReviewed-by: Yoshihiro Shimoda \u003cyoshihiro.shimoda.uh@renesas.com\u003e\nReviewed-by: Laurent Pinchart \u003claurent.pinchart@ideasonboard.com\u003e\nCc: \u003cstable@vger.kernel.org\u003e # v4.8+\nSigned-off-by: Vinod Koul \u003cvkoul@kernel.org\u003e\n(cherry picked from commit 907bd68a2edc491849e2fdcfe52c4596627bca94)\nSigned-off-by: Hiroyuki Yokoyama \u003chiroyuki.yokoyama.vx@renesas.com\u003e\n" }, { "commit": "c5606c6416b587e3e5299e8140443369fa182116", "tree": "052c13964cffeb1ca888b1d0d3e75d9201a81f4a", "parents": [ "9aa6649bb252b987708de0d2eba078ad3ef7aff4" ], "author": { "name": "Hiroyuki Yokoyama", "email": "hiroyuki.yokoyama.vx@renesas.com", "time": "Fri Apr 19 17:57:24 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:15:18 2019 +0900" }, "message": "Revert \"dmaengine: sh: rcar-dmac: With cyclic DMA residue 0 is valid\"\n\nThis reverts commit 0c7a66e6849d205d4443ee7d8bdd39c43e0e36e1.\nLink: https://patchwork.kernel.org/patch/10839055/\nIt included NULL access problem, therefore revert it.\n\nSigned-off-by: Hiroyuki Yokoyama \u003chiroyuki.yokoyama.vx@renesas.com\u003e\n" }, { "commit": "9aa6649bb252b987708de0d2eba078ad3ef7aff4", "tree": "ef9d0598dc1cfbffad2c58ee3c61d7570e33f82d", "parents": [ "1f12f0466c7782ef7f44481ecf08db5e77448c7f", "54721f5956546419922e9d910e0afb3cac0a662d" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:15:16 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Thu Jul 11 21:15:16 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.4/audio.rc2\u0027 into v4.14.75-ltsi/rcar-3.9.6\n\n* rcar-3.9.4/audio.rc2:\n ASoC: rsnd: fixup 6ch settings to 8ch\n ASoC: rsnd: src: Avoid a potential deadlock\n" }, { "commit": "54721f5956546419922e9d910e0afb3cac0a662d", "tree": "ef9d0598dc1cfbffad2c58ee3c61d7570e33f82d", "parents": [ "91849f8e8d7151d0ff3e04bac71339b78b77b6e3" ], "author": { "name": "Kuninori Morimoto", "email": "kuninori.morimoto.gx@renesas.com", "time": "Thu Apr 25 15:16:58 2019 +0900" }, "committer": { "name": "Hiroyuki Yokoyama", "email": "hiroyuki.yokoyama.vx@renesas.com", "time": "Fri May 17 13:46:28 2019 +0900" }, "message": "ASoC: rsnd: fixup 6ch settings to 8ch\n\nrsnd need to use 8ch clock settings for 6ch for TDM.\nOtherwise, it can\u0027t work correctly.\nThis patch fixup it.\n\nSigned-off-by: Kuninori Morimoto \u003ckuninori.morimoto.gx@renesas.com\u003e\nSigned-off-by: Mark Brown \u003cbroonie@kernel.org\u003e\n(cherry picked from commit 66287def435315d9d8de740da4c543e37630b897)\nSigned-off-by: Hiroyuki Yokoyama \u003chiroyuki.yokoyama.vx@renesas.com\u003e\n" }, { "commit": "91849f8e8d7151d0ff3e04bac71339b78b77b6e3", "tree": "d2c7a8313eac3712f32ccf1f6d8b120dffe63a73", "parents": [ "1f12f0466c7782ef7f44481ecf08db5e77448c7f" ], "author": { "name": "Jiada Wang", "email": "jiada_wang@mentor.com", "time": "Thu Mar 07 15:15:53 2019 +0900" }, "committer": { "name": "Hiroyuki Yokoyama", "email": "hiroyuki.yokoyama.vx@renesas.com", "time": "Tue May 07 15:43:38 2019 +0900" }, "message": "ASoC: rsnd: src: Avoid a potential deadlock\n\nlockdep warns us that priv-\u003elock and k-\u003ek_lock can cause a\ndeadlock when after acquire of k-\u003ek_lock, process is interrupted\nby src, while in another routine of src .init, k-\u003ek_lock is\nacquired with priv-\u003elock held.\n\nThis patch avoids a potential deadlock by not calling soc_device_match()\nin SRC .init callback, instead it adds new soc fields in priv-\u003eflags to\ndifferentiate SoCs.\n\nFixes: linux-next commit 7674bec4fc09 (\"ASoC: rsnd: update BSDSR/BSDISR handling\")\nSigned-off-by: Jiada Wang \u003cjiada_wang@mentor.com\u003e\nAcked-by: Kuninori Morimoto \u003ckuninori.morimoto.gx@renesas.com\u003e\nSigned-off-by: Mark Brown \u003cbroonie@kernel.org\u003e\n(cherry picked from commit ba164a49f8f7390b036713bf8a70a150a938c670)\nSigned-off-by: Hiroyuki Yokoyama \u003chiroyuki.yokoyama.vx@renesas.com\u003e\n" }, { "commit": "1f12f0466c7782ef7f44481ecf08db5e77448c7f", "tree": "054e7d709527587eb497ca9cc1e5f569897b494a", "parents": [ "2b6b2967bfea76c66819c36dbb78af8e84096ef1" ], "author": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Apr 01 20:01:08 2019 +0900" }, "committer": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Apr 01 20:35:25 2019 +0900" }, "message": "arm64: dts: r8a77990-ebisu{,-es10}: Enable IPMMU of SDHI3\n\nThis patch enables the IPMMU of SDHI3 used as an eMMC port on Ebisu and\nEbisu-4D boards.\n\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "2b6b2967bfea76c66819c36dbb78af8e84096ef1", "tree": "1dcbf389418bc8bcfeb612540424391f98bdf944", "parents": [ "b1aaf0d1ee4f944b58c30191aa8f6b953b8bddda" ], "author": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Apr 01 19:58:01 2019 +0900" }, "committer": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Apr 01 20:35:25 2019 +0900" }, "message": "arm64: dts: salvator-common: Enable IPMMU of SDHI2\n\nThis patch enables the IPMMU of SDHI2 used as an eMMC port on Salvator\nboard.\n\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "b1aaf0d1ee4f944b58c30191aa8f6b953b8bddda", "tree": "f88ce1e628f5f00d0b56088fa153a2e416e5daa5", "parents": [ "03d26176bf2fceb0c28511613a7b901ef4866f58" ], "author": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Apr 01 19:45:34 2019 +0900" }, "committer": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Apr 01 20:35:14 2019 +0900" }, "message": "Revert \"arm64: dts: r8a7795: Connect SDHI to IPMMU-DS1\"\n\nThis reverts commit 4bd36fe168284318c1091e998e7aa8351ff34528.\n\nMultiple IPMMUs can not be operated simultaneously due to H3 Ver.1.x and\nH3 Ver.2.0 hardware restriction.\n\nAs a result, this reverts commit 4bd36fe16828 (\"arm64: dts: r8a7795:\nConnect SDHI to IPMMU-DS1\") to keep IPMMU for SDHI{0..3} is disabled by\ndefault.\n\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "03d26176bf2fceb0c28511613a7b901ef4866f58", "tree": "49c09b478da6a0cb8d32c4cabcf24c00617dc076", "parents": [ "7d702c9baadf7c9578dab25ee5513f96fe7a6f5a" ], "author": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Apr 01 19:45:28 2019 +0900" }, "committer": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Apr 01 20:34:52 2019 +0900" }, "message": "Revert \"arm64: dts: r8a7796: Connect SDHI to IPMMU-DS1\"\n\nThis reverts commit 6ea36b7fb2cbf0b4ab5cf0d743de64a833468886.\n\nMultiple IPMMUs can not be operated simultaneously due to M3 Ver.1.x\nhardware restriction.\n\nAs a result, this reverts commit 6ea36b7fb2cb (\"arm64: dts: r8a7796:\nConnect SDHI to IPMMU-DS1\") to keep IPMMU for SDHI{0..3} is disabled by\ndefault.\n\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "7d702c9baadf7c9578dab25ee5513f96fe7a6f5a", "tree": "731c8bedddb9120d569ec10213321d5316754176", "parents": [ "915233498bcfac9369169af32d4b49625d61db35" ], "author": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Apr 01 19:45:21 2019 +0900" }, "committer": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Apr 01 20:34:40 2019 +0900" }, "message": "Revert \"arm64: dts: r8a77965: Connect SDHI to IPMMU-DS1\"\n\nThis reverts commit 21258b113ddea10592c3c90979f269bd31bd0622.\n\nMultiple IPMMUs can not be operated simultaneously due to H3 Ver.1.x,\nH3 Ver.2.0, M3 Ver.1.x hardware restriction.\n\nM3-N has no similar hardware restriction, but disables IPMMU for SoCs\nthat have hardware restriction.\n\nAs a result, This reverts commit 21258b113dde (\"arm64: dts: r8a77965:\nConnect SDHI to IPMMU-DS1\") to keep IPMMU for SDHI{0..3} is disabled by\ndefault.\n\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "915233498bcfac9369169af32d4b49625d61db35", "tree": "7122ac3cc76bae968d77cf877e9164a8f6e398d9", "parents": [ "de462a6e5630bb3abe28e0eeb13f95e953fca50c" ], "author": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Apr 01 19:45:12 2019 +0900" }, "committer": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Apr 01 20:34:12 2019 +0900" }, "message": "Revert \"arm64: dts: r8a77990: Connect SDHI to IPMMU-DS1\"\n\nThis reverts commit 2cdef56231d3098a413528456fb958d236f82937.\n\nMultiple IPMMUs can not be operated simultaneously due to H3 Ver.1.x,\nH3 Ver.2.0, M3 Ver.1.x hardware restriction.\n\nE3 has no similar hardware restriction, but disables IPMMU for SoCs\nthat have hardware restriction.\n\nAs a result, This reverts commit 2cdef56231d3 (\"arm64: dts: r8a77990:\nConnect SDHI to IPMMU-DS1\") to keep IPMMU for SDHI{0,1,3} is disabled by\ndefault.\n\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "de462a6e5630bb3abe28e0eeb13f95e953fca50c", "tree": "d5cc846a2a9dfd617b60522116d1c6f34619e8c0", "parents": [ "d21be5eb5cfce69bc73e07141904024853b62ca8" ], "author": { "name": "Yoshihiro Shimoda", "email": "yoshihiro.shimoda.uh@renesas.com", "time": "Thu Mar 28 18:20:07 2019 +0900" }, "committer": { "name": "Takeshi Saito", "email": "takeshi.saito.xv@renesas.com", "time": "Mon Apr 01 17:28:08 2019 +0900" }, "message": "mmc: core: retry CMD1 in mmc_send_op_cond() even if the ocr \u003d 0\n\nAccording to eMMC specification, we should issue CMD1 repeatidly in\nthe idle state until the eMMC is ready even if the mmc_attach_mmc()\ncalls this function with ocr \u003d 0. Otherwise some eMMC devices seems\nto enter the inactive mode after mmc_init_card() issued CMD0 when\nthe eMMC device is busy.\n\nSigned-off-by: Yoshihiro Shimoda \u003cyoshihiro.shimoda.uh@renesas.com\u003e\nPatchwork: https://patchwork.kernel.org/patch/10874621/\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\n" }, { "commit": "d21be5eb5cfce69bc73e07141904024853b62ca8", "tree": "59cc63736852b81ad71402078a3b8c2fb879ef9e", "parents": [ "c3cbd3684e52686f65a24baa9ea5803c557c4d67", "f3f36384af2aad6e7a7279b62297ddf618e8296c" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:44 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:44 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.2/dts-rcar-gen3.rc4\u0027 into v4.14.75-ltsi/rcar-3.9.3\n\n* rcar-3.9.2/dts-rcar-gen3.rc4:\n arm64: dts: r8a77990-ebisu{,-es10}: Add no-sdio and no-sd properties to SDHI3\n arm64: dts: salvator-common: Add no-sdio and no-sd properties to SDHI2\n arm64: dts: r8a77990: Enable IPMMU-DS1 and IPMMU-MM\n arm64: dts: r8a77965: Enable IPMMU-DS1 and IPMMU-MM\n arm64: dts: r8a7796: Enable IPMMU-DS1 and IPMMU-MM\n arm64: dts: r8a7795: Enable IPMMU-DS1 and IPMMU-MM\n arm64: dts: r8a77990: Connect SDHI to IPMMU-DS1\n arm64: dts: r8a77965: Connect SDHI to IPMMU-DS1\n arm64: dts: r8a7796: Connect SDHI to IPMMU-DS1\n arm64: dts: r8a7795: Connect SDHI to IPMMU-DS1\n Revert \"arm64: dts: renesas: r8a7795: Tie Audio-DMAC to IPMMU-MP0/1\"\n Revert \"arm64: dts: renesas: r8a7796: Tie Audio-DMAC to IPMMU-MP\"\n Revert \"arm64: dts: renesas: r8a7795: Tie SYS-DMAC to IPMMU-DS0/1\"\n Revert \"arm64: dts: renesas: r8a7796: Tie SYS-DMAC to IPMMU-DS0/1\"\n Revert \"arm64: dts: renesas: r8a77965: Attach the SYS-DMAC to the IPMMU\"\n Revert \"arm64: dts: renesas: r8a77990: Attach the SYS-DMAC to the IPMMU\"\n Revert \"arm64: dts: r8a77965: Tie Audio-DMAC to IPMMU-MP\"\n Revert \"arm64: dts: r8a77990: Tie Audio-DMAC to IPMMU-MP\"\n arm64: dts: r8a7796-m3ulcb: Select the device tree of R-Car M3 ES1.x.\n arm64: dts: r8a77965-m3nulcb: Fix source clock for DU\n arm64: dts: r8a77965-m3nulcb: Add VSPM I/F driver node\n arm64: dts: r8a77965-m3nulcb: Add MMNGRBUF driver node\n arm64: dts: r8a77965-m3nulcb: Add MMNGR support\n arm64: dts: r8a77965-m3nulcb: Add reserved mem for MMNGR\n arm64: dts: renesas: r8a77965: m3nulcb: Initial device tree\n dt-bindings: arm: Document Renesas R-Car M3-N-based ULCB board\n arm64: dts: r8a7796: Add support for R-Car M3 ES3.0\n arm64: dts: r8a77965: Fix power domain for FCPCS\n arm64: dts: r8a77990: Fix SCIF5 DMA channels\n arm64: dts: r8a7795: Fix clock, reset and power domain for iVDP1C\n" }, { "commit": "f3f36384af2aad6e7a7279b62297ddf618e8296c", "tree": "59cc63736852b81ad71402078a3b8c2fb879ef9e", "parents": [ "5c758f337e7f511d9ba92d0885d43fe7bc7d7557" ], "author": { "name": "Takeshi Saito", "email": "takeshi.saito.xv@renesas.com", "time": "Wed Mar 20 18:17:09 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:43 2019 +0900" }, "message": "arm64: dts: r8a77990-ebisu{,-es10}: Add no-sdio and no-sd properties to SDHI3\n\nAdd the \u0027no-sdio\u0027 and \u0027no-sd\u0027 properties to the SDHI3 node used as the\neMMC port on Ebisu and Ebisu-4D boards. It will limits the send sdio and\nsd cmd during mmc initialization.\n\nIn addition, the \u0027no-sdio\u0027 property uses multiple SG entries when SDHI\ninternal DMAC with IOMMU is enabled. This can improve performance.\n\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "5c758f337e7f511d9ba92d0885d43fe7bc7d7557", "tree": "70e345be5569b6723f6e5e810e1b6a67f549b152", "parents": [ "9365521f3c97248b16e4d1eb318bfc8610946b43" ], "author": { "name": "Takeshi Saito", "email": "takeshi.saito.xv@renesas.com", "time": "Wed Mar 20 18:15:13 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:43 2019 +0900" }, "message": "arm64: dts: salvator-common: Add no-sdio and no-sd properties to SDHI2\n\nAdd the \u0027no-sdio\u0027 and \u0027no-sd\u0027 properties to the SDHI2 node used as the\neMMC port on Salvator board. It will limits the send sdio and sd cmd\nduring mmc initialization.\n\nIn addition, the \u0027no-sdio\u0027 property uses multiple SG entries when SDHI\ninternal DMAC with IOMMU is enabled. This can improve performance.\n\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "9365521f3c97248b16e4d1eb318bfc8610946b43", "tree": "529a231c02c18fc532ffa288056ba20db0af5c5c", "parents": [ "91fc9f9707d8e5e9de41c9e81a1e316f48350e38" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 08 20:26:13 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:43 2019 +0900" }, "message": "arm64: dts: r8a77990: Enable IPMMU-DS1 and IPMMU-MM\n\nEnable the r8a77990 device nodes for IPMMU-DS1 and the shared IPMMU-MM\ndevice.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "91fc9f9707d8e5e9de41c9e81a1e316f48350e38", "tree": "d2da48923de622a965311e16f38e8110bf944955", "parents": [ "2fa27d4e5081e3c2955affa959102ef6c3e1d0ef" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 08 20:23:52 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:43 2019 +0900" }, "message": "arm64: dts: r8a77965: Enable IPMMU-DS1 and IPMMU-MM\n\nEnable the r8a77965 device nodes for IPMMU-DS1 and the shared IPMMU-MM\ndevice.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "2fa27d4e5081e3c2955affa959102ef6c3e1d0ef", "tree": "d222a3f538e94188c275f7905ab98ac5d04b6cc3", "parents": [ "993ff95764652b283eee29b25bc9bd633e9100a9" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 08 20:11:53 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:43 2019 +0900" }, "message": "arm64: dts: r8a7796: Enable IPMMU-DS1 and IPMMU-MM\n\nEnable the r8a7796 device nodes for IPMMU-DS1 and the shared IPMMU-MM\ndevice.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "993ff95764652b283eee29b25bc9bd633e9100a9", "tree": "32564dd5b209ceb2427102a28c831ae157fb672e", "parents": [ "2cdef56231d3098a413528456fb958d236f82937" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 08 20:00:39 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:43 2019 +0900" }, "message": "arm64: dts: r8a7795: Enable IPMMU-DS1 and IPMMU-MM\n\nEnable the r8a7795 device nodes for IPMMU-DS1 and the shared IPMMU-MM\ndevice.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "2cdef56231d3098a413528456fb958d236f82937", "tree": "38c3082f704e63172c618e8ae5513db1432ce5ce", "parents": [ "21258b113ddea10592c3c90979f269bd31bd0622" ], "author": { "name": "Phat Pham", "email": "phat.pham.zg@rvc.renesas.com", "time": "Fri Mar 08 14:44:53 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:42 2019 +0900" }, "message": "arm64: dts: r8a77990: Connect SDHI to IPMMU-DS1\n\nAdd IPMMU-DS1 to the SDHI device node.\n\nSigned-off-by: Phat Pham \u003cphat.pham.zg@rvc.renesas.com\u003e\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "21258b113ddea10592c3c90979f269bd31bd0622", "tree": "d2b1b82cbb68e9c56ad412b9356262223cafba2f", "parents": [ "6ea36b7fb2cbf0b4ab5cf0d743de64a833468886" ], "author": { "name": "Phat Pham", "email": "phat.pham.zg@rvc.renesas.com", "time": "Fri Mar 08 14:39:29 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:42 2019 +0900" }, "message": "arm64: dts: r8a77965: Connect SDHI to IPMMU-DS1\n\nAdd IPMMU-DS1 to SDHI device node.\n\nSigned-off-by: Phat Pham \u003cphat.pham.zg@rvc.renesas.com\u003e\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "6ea36b7fb2cbf0b4ab5cf0d743de64a833468886", "tree": "b05d8ab356c04d9346ae124341289bf5f79edd23", "parents": [ "4bd36fe168284318c1091e998e7aa8351ff34528" ], "author": { "name": "Phat Pham", "email": "phat.pham.zg@rvc.renesas.com", "time": "Fri Mar 08 14:37:44 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:42 2019 +0900" }, "message": "arm64: dts: r8a7796: Connect SDHI to IPMMU-DS1\n\nAdd IPMMU-DS1 to the SDHI device node.\n\nSigned-off-by: Phat Pham \u003cphat.pham.zg@rvc.renesas.com\u003e\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "4bd36fe168284318c1091e998e7aa8351ff34528", "tree": "a6d71b60167d245d387e8581a9d7afb3baeee10e", "parents": [ "babaf623b5160704b115631130b79dde80a458bb" ], "author": { "name": "Phat Pham", "email": "phat.pham.zg@rvc.renesas.com", "time": "Fri Mar 08 14:28:44 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:42 2019 +0900" }, "message": "arm64: dts: r8a7795: Connect SDHI to IPMMU-DS1\n\nAdd IPMMU-DS1 to the SDHI device node.\n\nSigned-off-by: Phat Pham \u003cphat.pham.zg@rvc.renesas.com\u003e\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "babaf623b5160704b115631130b79dde80a458bb", "tree": "b71f277ab8e9bc74cdf1dd69a7d43bd709f7f1fe", "parents": [ "ccc9af6e8936a3699638e7d50270985a69392abc" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 08 16:28:58 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:42 2019 +0900" }, "message": "Revert \"arm64: dts: renesas: r8a7795: Tie Audio-DMAC to IPMMU-MP0/1\"\n\nThis reverts commit 2a8ae102ed215806c7ca867e0a4522136d68d40e\nto keep the IPMMU address translation for Audio-DMAC is disabled\nby default.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "ccc9af6e8936a3699638e7d50270985a69392abc", "tree": "a2d2baa859bc9f97d1aabf1d76ae97e81edf1818", "parents": [ "83e7b285d5247100e96cc5139045fc46e30d3f58" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 08 18:01:24 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:42 2019 +0900" }, "message": "Revert \"arm64: dts: renesas: r8a7796: Tie Audio-DMAC to IPMMU-MP\"\n\nThis reverts commit 8f7fa3f36dfb3538f651f3b80830e3f0c1f48c79\nto keep IPMMU address translation for Audio-DMAC is disabled\nby default.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "83e7b285d5247100e96cc5139045fc46e30d3f58", "tree": "7ea71ccfcb67604e5551fe569d2d9f5abd412048", "parents": [ "91145fb6a6c292357f2ccaa4e1acbbb30457bf62" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 08 16:16:19 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:41 2019 +0900" }, "message": "Revert \"arm64: dts: renesas: r8a7795: Tie SYS-DMAC to IPMMU-DS0/1\"\n\nThis reverts commit bfa8f11e3f95f32620edae00277a23197a50c77a\nto keep IPMMU address translation for SYS-DMAC0, SYS-DMAC1 and\nSYS-DMAC2 is disabled by default.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "91145fb6a6c292357f2ccaa4e1acbbb30457bf62", "tree": "89dee8903f5a9568bbdb58181b80e7ed1a0e4012", "parents": [ "32a18bd7115e72735d7db0ff1e33a0042d586765" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 08 16:15:08 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:41 2019 +0900" }, "message": "Revert \"arm64: dts: renesas: r8a7796: Tie SYS-DMAC to IPMMU-DS0/1\"\n\nThis reverts commit 2e7dfb1a9bf06af94f4da60ada829260308e2f1b\nto keep IPMMU address translation for SYS-DMAC0, SYS-DMAC1 and\nSYS-DMAC2 is disabled by default.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "32a18bd7115e72735d7db0ff1e33a0042d586765", "tree": "eda96f381c576159b4c0b72e3829546062100c77", "parents": [ "0e9229ea60ac32cbed06910e8677b66c0e6553a3" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 08 16:12:53 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:41 2019 +0900" }, "message": "Revert \"arm64: dts: renesas: r8a77965: Attach the SYS-DMAC to the IPMMU\"\n\nThis reverts commit fee499aca1b44e5a2f7d6937ab0f42afdee5a8dc\nto keep IPMMU address translation for SYS-DMAC0, SYS-DMAC1 and\nSYS-DMAC2 is disabled by default.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "0e9229ea60ac32cbed06910e8677b66c0e6553a3", "tree": "ee9d511f06144abc0d1eaaae2ee94d4915773ed8", "parents": [ "c3eef50d22ba7f608eac1cee39357c58ce258c46" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 08 15:20:03 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:41 2019 +0900" }, "message": "Revert \"arm64: dts: renesas: r8a77990: Attach the SYS-DMAC to the IPMMU\"\n\nThis reverts commit b7b0f8ae1531ee00528797bb728a6ef93db2ceb3\nto keep IPMMU address translation for SYS-DMAC0, SYS-DMAC1 and\nSYS-DMAC2 is disabled by default.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "c3eef50d22ba7f608eac1cee39357c58ce258c46", "tree": "56fc0fddedef134098377d8732165b4ea083161e", "parents": [ "80359ee925335de7209f23742bbf78aedf3d89fb" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 08 15:28:47 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:41 2019 +0900" }, "message": "Revert \"arm64: dts: r8a77965: Tie Audio-DMAC to IPMMU-MP\"\n\nThis reverts commit 7108e015aabd8d56707622b1b9676ee9ef84e32f\nto keep IPMMU address translation for Audio-DMAC is disabled\nby default.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "80359ee925335de7209f23742bbf78aedf3d89fb", "tree": "6a79028e0a9cc8809a921a4acf1a984e55f3dc15", "parents": [ "f8c354beddcd0fb39fd28d7ee1efbf10b12c6772" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 08 15:26:47 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:41 2019 +0900" }, "message": "Revert \"arm64: dts: r8a77990: Tie Audio-DMAC to IPMMU-MP\"\n\nThis reverts commit eb7141f4463f52e72ebda5513ea8ce1229d3e23c\nto keep IPMMU address translation for Audio-DMAC is disabled\nby default.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "f8c354beddcd0fb39fd28d7ee1efbf10b12c6772", "tree": "8e55cb9bb372812607981d7b2f4d9435c2c42290", "parents": [ "44145606a843a196841d9b4d4b3669f7feae38a8" ], "author": { "name": "Yusuke Goda", "email": "yusuke.goda.sx@renesas.com", "time": "Tue Jan 29 01:58:48 2019 +0000" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:40 2019 +0900" }, "message": "arm64: dts: r8a7796-m3ulcb: Select the device tree of R-Car M3 ES1.x.\n\nThe device tree of R-Car M3 was divided into ES1.x and ES3.0.\nM3ULCB is equipped with ES1.0 SoC.\nSo, this patch selects the device tree of ES1.x.\n\nSigned-off-by: Yusuke Goda \u003cyusuke.goda.sx@renesas.com\u003e\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "44145606a843a196841d9b4d4b3669f7feae38a8", "tree": "21ba49aa1188d7e8c349b2e8f18b1c01a25bf189", "parents": [ "b8d5de71addccb19c14f077625fdd562c52dd389" ], "author": { "name": "Yusuke Goda", "email": "yusuke.goda.sx@renesas.com", "time": "Thu Jan 17 06:04:21 2019 +0000" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:40 2019 +0900" }, "message": "arm64: dts: r8a77965-m3nulcb: Fix source clock for DU\n\nULCB Versaclock default output clock is based on its ROM code,\nand ULCB case is 33HMz.\nBut current DT is missing such information, and Versaclock driver\ncan\u0027t handle it today.\n\nWe need to update Versaclock driver to handle it correctly.\nBut as Quick-Hack, this patch indicates it via versaclock5_out3\ntemporally.\n\nSigned-off-by: Yusuke Goda \u003cyusuke.goda.sx@renesas.com\u003e\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "b8d5de71addccb19c14f077625fdd562c52dd389", "tree": "933c2334d902edd6ee098af0f5d788cb1fca4602", "parents": [ "e98423035c927dd72d7abdd1b32b87d2df7fe94e" ], "author": { "name": "Yusuke Goda", "email": "yusuke.goda.sx@renesas.com", "time": "Thu Jan 17 06:02:14 2019 +0000" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:40 2019 +0900" }, "message": "arm64: dts: r8a77965-m3nulcb: Add VSPM I/F driver node\n\nAdd VSP Manager I/F driver node for M3NULCB board on R8A77965 SoC.\n\nSigned-off-by: Yusuke Goda \u003cyusuke.goda.sx@renesas.com\u003e\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "e98423035c927dd72d7abdd1b32b87d2df7fe94e", "tree": "602b6bce452ca648ab4c91fd7689a551604fdc88", "parents": [ "a2debd5d2b9541203eb9208d5ab875a0dc789235" ], "author": { "name": "Yusuke Goda", "email": "yusuke.goda.sx@renesas.com", "time": "Thu Jan 17 05:59:56 2019 +0000" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:40 2019 +0900" }, "message": "arm64: dts: r8a77965-m3nulcb: Add MMNGRBUF driver node\n\nThis patch adds MMNGRBUF external kernel module for M3NULCB board\non R8A77965 SoC.\n\nSigned-off-by: Yusuke Goda \u003cyusuke.goda.sx@renesas.com\u003e\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "a2debd5d2b9541203eb9208d5ab875a0dc789235", "tree": "e3a9ba04d1d54d43fe7a3f0f81dfd1c7958daa52", "parents": [ "5839ddcf6a87eeebc01783f4cb327ca3a90d3dad" ], "author": { "name": "Yusuke Goda", "email": "yusuke.goda.sx@renesas.com", "time": "Thu Jan 17 05:53:31 2019 +0000" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:40 2019 +0900" }, "message": "arm64: dts: r8a77965-m3nulcb: Add MMNGR support\n\nThis patch adds MMNGR external kernel module for M3NULCB board on\nR8A77965 SoC.\n\nSigned-off-by: Yusuke Goda \u003cyusuke.goda.sx@renesas.com\u003e\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "5839ddcf6a87eeebc01783f4cb327ca3a90d3dad", "tree": "6b384d47e858f5e3b330d715e2e69d965ae249d5", "parents": [ "1c63f8fd27e22a09b1505d7eda61e9fa91aa89c2" ], "author": { "name": "Yusuke Goda", "email": "yusuke.goda.sx@renesas.com", "time": "Thu Jan 17 05:51:05 2019 +0000" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:39 2019 +0900" }, "message": "arm64: dts: r8a77965-m3nulcb: Add reserved mem for MMNGR\n\nThis patch adds reserved memory regions:\n - Lossy Decompression\n\t48 MiB : 0x0054000000 -\u003e 0x0056ffffff\n - Default CMA area\n\t400 MiB : 0x0057000000 -\u003e 0x006fffffff\n - CMA area for MMP\n\t256 MiB : 0x0070000000 -\u003e 0x007fffffff\n\nSigned-off-by: Yusuke Goda \u003cyusuke.goda.sx@renesas.com\u003e\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "1c63f8fd27e22a09b1505d7eda61e9fa91aa89c2", "tree": "dfe7d15b65f833d66e6e3705149fd60a9d689816", "parents": [ "154474856a67fb78fd55a6ecc71c15edfbb44182" ], "author": { "name": "Eugeniu Rosca", "email": "roscaeugeniu@gmail.com", "time": "Sun Aug 12 15:31:46 2018 +0200" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:39 2019 +0900" }, "message": "arm64: dts: renesas: r8a77965: m3nulcb: Initial device tree\n\nAllow the bare M3-N-based ULCB board to boot.\n\nSigned-off-by: Eugeniu Rosca \u003cerosca@de.adit-jv.com\u003e\nReviewed-by: Jacopo Mondi \u003cjacopo+renesas@jmondi.org\u003e\nSigned-off-by: Simon Horman \u003chorms+renesas@verge.net.au\u003e\n(cherry picked from commit 83ff28c74b525aa33f42b829538017d3e8658e69)\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "154474856a67fb78fd55a6ecc71c15edfbb44182", "tree": "4c8f27e588c1c787afa4684aeb1bb026dc319fee", "parents": [ "8ba438fd03d5b78658362401253f7e430cdc8a4f" ], "author": { "name": "Eugeniu Rosca", "email": "roscaeugeniu@gmail.com", "time": "Sun Aug 12 15:31:43 2018 +0200" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:39 2019 +0900" }, "message": "dt-bindings: arm: Document Renesas R-Car M3-N-based ULCB board\n\nIn harmony with ATF and U-Boot outputs [1] and [2], the new board is\nbased on M3-N revision ES1.1 and the amount of memory present on SiP\nis 2GiB, contiguously addressed.\n\nThe amount of RAM is mentioned based on the assumption that it is\nencoded in the board id/string. There is some evidence supporting this\nin form of last-digit-mismatch between two R-Car H3 ES2.0 ULCB board\nids, one with 4GiB and one with 8GiB of RAM (see [3]).\n\n[1] BL2: R-Car Gen3 Initial Program Loader(CA57) Rev.1.0.21\n BL2: PRR is R-Car M3N Ver.1.1\n\n[2] U-Boot 2015.04-00295-*\n CPU: Renesas Electronics R8A77965 rev 1.1\n ---8\u003c----\n DRAM: 1.9 GiB\n Bank #0: 0x048000000 - 0x0bfffffff, 1.9 GiB\n ---8\u003c----\n\n[3] https://patchwork.kernel.org/patch/10555957/#22169325\n\nSigned-off-by: Eugeniu Rosca \u003cerosca@de.adit-jv.com\u003e\nSigned-off-by: Simon Horman \u003chorms+renesas@verge.net.au\u003e\n(cherry picked from commit 43bcac2396f7874338016d3c6d86d0bdad8e63e8)\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "8ba438fd03d5b78658362401253f7e430cdc8a4f", "tree": "2013b581a4a9bbdadcba1844d887796c23db43f5", "parents": [ "a36fcaca239e26101b619b18d80d457c91786ac8" ], "author": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Jan 28 18:24:33 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:39 2019 +0900" }, "message": "arm64: dts: r8a7796: Add support for R-Car M3 ES3.0\n\nUpdate r8a7796.dtsi so it corresponds to R-Car M3 ES3.0 or later:\n - The FCPCI0 module do not exist in ES3.0, the device node is deleted.\n - The FCPCS module power domain is changed from A3VC to A2VC1.\n - The iVDP1C module clock supply and software reset register bits using\n CPG changed from bit28 to bit30.\n - The iVDP1C module power domain is changed from A2VC0 to A2VC1.\n - The VDPB module power domain is changed from A2VC0 to A2VC1.\n\nMove support for ES1.x revision R-Car M3 SoC separate into\nr8a7796-es1.dtsi.\n\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "a36fcaca239e26101b619b18d80d457c91786ac8", "tree": "734e014c4129626d38ef34804e9afb74ae40914f", "parents": [ "63ec9d6fc03d56928d71dc2f573da44718934422" ], "author": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Fri Mar 22 08:30:28 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:39 2019 +0900" }, "message": "arm64: dts: r8a77965: Fix power domain for FCPCS\n\nIn R-Car Gen3 Hardware Manual Rev 1.50, the power domain of FCPCS module\nwas A3VC on R-Car M3N. However, this power domain is A2VC1 correctly.\n\nNOTE: This information will be reflected in the R-Car Gen3 Hardware\n Manual in the future.\n\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "63ec9d6fc03d56928d71dc2f573da44718934422", "tree": "d1130faa3e70ba0641d1ae7b4f5fc01082931a05", "parents": [ "c922c328f1383099b600690844ed029c167e8520" ], "author": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Tue Feb 12 11:07:49 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:38 2019 +0900" }, "message": "arm64: dts: r8a77990: Fix SCIF5 DMA channels\n\nAccording to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of\nFeb 12, 2019, the DMA channels support for SCIF5 is modified from 16..47\nto 0..15 on R-Car E3.\n\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "c922c328f1383099b600690844ed029c167e8520", "tree": "68f2fc33054fc7e04f89af6872e98c169c2b537a", "parents": [ "c3cbd3684e52686f65a24baa9ea5803c557c4d67" ], "author": { "name": "Takeshi Kihara", "email": "takeshi.kihara.df@renesas.com", "time": "Mon Jan 28 18:49:34 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:38 2019 +0900" }, "message": "arm64: dts: r8a7795: Fix clock, reset and power domain for iVDP1C\n\nAccording to the R-Car Gen3 Hardware Manual Rev 1.50, the module clock\nstatus, module clock control, and reset control bit of the iVDP1C module\non R-Car H3 ES2.0 or later was changed from bit28 to bit30. And the power\ndomain of the iVDP1C module was changed from A2VC0 to A2VC1.\n\nSigned-off-by: Takeshi Kihara \u003ctakeshi.kihara.df@renesas.com\u003e\n" }, { "commit": "c3cbd3684e52686f65a24baa9ea5803c557c4d67", "tree": "6c675e590a8ba41e42740560d0fcf6b882b5b25d", "parents": [ "538d41278caaf9b4066db035a11c4ef38f5912f3", "a9181365a599574b10df01cabdfc7c4e1cb222c3" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:37 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:37 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.2/bd9571MWV.rc4\u0027 into v4.14.75-ltsi/rcar-3.9.3\n\n* rcar-3.9.2/bd9571MWV.rc4:\n mfd: bd9571mwv: Clean up the BD9574MWF register mapping\n mfd: bd9571mwv: Enable GPIO support for PMIC BD9574MWF\n mfd: bd9571mwv: fix section mismatch\n mfd: bd9571mwv: Add support for BD9574MWF\n mfd: bd9571mwv: Make the driver more generic\n" }, { "commit": "a9181365a599574b10df01cabdfc7c4e1cb222c3", "tree": "6c675e590a8ba41e42740560d0fcf6b882b5b25d", "parents": [ "b0375b0bb391fabd22b4bd81df7a5aa18055f21a" ], "author": { "name": "Khiem Nguyen", "email": "khiem.nguyen.xt@renesas.com", "time": "Wed Mar 20 13:03:43 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:37 2019 +0900" }, "message": "mfd: bd9571mwv: Clean up the BD9574MWF register mapping\n\nThis patch cleans up the mapped registers which is not used\nduring BD9574MWF PMIC operation.\n\nSigned-off-by: Khiem Nguyen \u003ckhiem.nguyen.xt@renesas.com\u003e\n" }, { "commit": "b0375b0bb391fabd22b4bd81df7a5aa18055f21a", "tree": "38b8cbd59d238164004575a162d079ce52638a71", "parents": [ "af9c7b7ce7b0710af19f4b8c10334892fd0674d6" ], "author": { "name": "Khiem Nguyen", "email": "khiem.nguyen.xt@renesas.com", "time": "Wed Mar 20 12:59:35 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:37 2019 +0900" }, "message": "mfd: bd9571mwv: Enable GPIO support for PMIC BD9574MWF\n\nThe BD9574MWF supports small PMIC GPIO block.\nThis patch enables GPIO control for that block.\n\nSigned-off-by: Khiem Nguyen \u003ckhiem.nguyen.xt@renesas.com\u003e\n" }, { "commit": "af9c7b7ce7b0710af19f4b8c10334892fd0674d6", "tree": "c7efcb215e410f0f56d9c0742b7a69ff97af0c7d", "parents": [ "9fd5e585515b809fac299f6d4b42844d34f8d58c" ], "author": { "name": "Nam Dang", "email": "nam.dang.uw@rvc.renesas.com", "time": "Tue Mar 12 16:57:07 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:36 2019 +0900" }, "message": "mfd: bd9571mwv: fix section mismatch\n\n1. Fix issue build warning \"section mismatch\"\n2. Add some comments to make more clearly\n\nSigned-off-by: Nam Dang \u003cnam.dang.uw@rvc.renesas.com\u003e\n" }, { "commit": "9fd5e585515b809fac299f6d4b42844d34f8d58c", "tree": "b3e040bea86018171fcab6d36621a690377a632f", "parents": [ "bb3b2d661d23fb569ed96b9e5706f980e6ff1466" ], "author": { "name": "Khiem Nguyen", "email": "khiem.nguyen.xt@renesas.com", "time": "Thu Mar 07 19:13:19 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:36 2019 +0900" }, "message": "mfd: bd9571mwv: Add support for BD9574MWF\n\nThe new PMIC BD9574MWF inherits features from BD9571MWV.\nAdd the support of new PMIC to existing bd9571mwv driver.\n\nSigned-off-by: Khiem Nguyen \u003ckhiem.nguyen.xt@renesas.com\u003e\n" }, { "commit": "bb3b2d661d23fb569ed96b9e5706f980e6ff1466", "tree": "30ca9a4854ab82c2d3f104251af62143eadbc998", "parents": [ "538d41278caaf9b4066db035a11c4ef38f5912f3" ], "author": { "name": "Khiem Nguyen", "email": "khiem.nguyen.xt@renesas.com", "time": "Thu Mar 07 18:20:18 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:36 2019 +0900" }, "message": "mfd: bd9571mwv: Make the driver more generic\n\nSince the driver supports BD9571MWV PMIC only,\nthis patch makes the functions and data structure become more generic\nso that it can support other PMIC variants as well.\n\nSigned-off-by: Khiem Nguyen \u003ckhiem.nguyen.xt@renesas.com\u003e\n" }, { "commit": "538d41278caaf9b4066db035a11c4ef38f5912f3", "tree": "73ef298816a80a950bb49fda51145d7e0ecd0a28", "parents": [ "442e4daf2ba7cee3749f0cc6c6f0b3d15f0804ed", "e2acafb18264fe3dd3c69e209ac96ab889277555" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:35 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:35 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.2/iommu-ipmmu-vmsa.rc3\u0027 into v4.14.75-ltsi/rcar-3.9.3\n\n* rcar-3.9.2/iommu-ipmmu-vmsa.rc3:\n driver core: Postpone DMA tear-down until after devres release\n iommu/ipmmu-vmsa: Fix memory leak when adding master device\n iommu/ipmmu-vmsa: Allow PCI Host controller to be a proxy for all connected PCI devices\n iommu/ipmmu-vmsa: Bypass whitelist check for unsupported SoCs\n iommu/ipmmu-vmsa: Support suspend/resume by default\n" }, { "commit": "e2acafb18264fe3dd3c69e209ac96ab889277555", "tree": "73ef298816a80a950bb49fda51145d7e0ecd0a28", "parents": [ "311736f6f2647b4482711f19311403b2e087a55f" ], "author": { "name": "Geert Uytterhoeven", "email": "geert+renesas@glider.be", "time": "Thu Feb 07 20:36:53 2019 +0100" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:35 2019 +0900" }, "message": "driver core: Postpone DMA tear-down until after devres release\n\nFrom upstream commit 376991db4uuu (\u0027driver core: Postpone DMA tear-down\nuntil after devres release\u0027)\n\nWhen unbinding the (IOMMU-enabled) R-Car SATA device on Salvator-XS\n(R-Car H3 ES2.0), in preparation of rebinding against vfio-platform for\ndevice pass-through for virtualization:\n\n    echo ee300000.sata \u003e /sys/bus/platform/drivers/sata_rcar/unbind\n\nthe kernel crashes with:\n\n    Unable to handle kernel paging request at virtual address ffffffbf029ffffc\n    Mem abort info:\n      ESR \u003d 0x96000006\n      Exception class \u003d DABT (current EL), IL \u003d 32 bits\n      SET \u003d 0, FnV \u003d 0\n      EA \u003d 0, S1PTW \u003d 0\n    Data abort info:\n      ISV \u003d 0, ISS \u003d 0x00000006\n      CM \u003d 0, WnR \u003d 0\n    swapper pgtable: 4k pages, 39-bit VAs, pgdp \u003d 000000007e8c586c\n    [ffffffbf029ffffc] pgd\u003d000000073bfc6003, pud\u003d000000073bfc6003, pmd\u003d0000000000000000\n    Internal error: Oops: 96000006 [#1] SMP\n    Modules linked in:\n    CPU: 0 PID: 1098 Comm: bash Not tainted 5.0.0-rc5-salvator-x-00452-g37596f884f4318ef #287\n    Hardware name: Renesas Salvator-X 2nd version board based on r8a7795 ES2.0+ (DT)\n    pstate: 60400005 (nZCv daif +PAN -UAO)\n    pc : __free_pages+0x8/0x58\n    lr : __dma_direct_free_pages+0x50/0x5c\n    sp : ffffff801268baa0\n    x29: ffffff801268baa0 x28: 0000000000000000\n    x27: ffffffc6f9c60bf0 x26: ffffffc6f9c60bf0\n    x25: ffffffc6f9c60810 x24: 0000000000000000\n    x23: 00000000fffff000 x22: ffffff8012145000\n    x21: 0000000000000800 x20: ffffffbf029fffc8\n    x19: 0000000000000000 x18: ffffffc6f86c42c8\n    x17: 0000000000000000 x16: 0000000000000070\n    x15: 0000000000000003 x14: 0000000000000000\n    x13: ffffff801103d7f8 x12: 0000000000000028\n    x11: ffffff8011117604 x10: 0000000000009ad8\n    x9 : ffffff80110126d0 x8 : ffffffc6f7563000\n    x7 : 6b6b6b6b6b6b6b6b x6 : 0000000000000018\n    x5 : ffffff8011cf3cc8 x4 : 0000000000004000\n    x3 : 0000000000080000 x2 : 0000000000000001\n    x1 : 0000000000000000 x0 : ffffffbf029fffc8\n    Process bash (pid: 1098, stack limit \u003d 0x00000000c38e3e32)\n    Call trace:\n     __free_pages+0x8/0x58\n     __dma_direct_free_pages+0x50/0x5c\n     arch_dma_free+0x1c/0x98\n     dma_direct_free+0x14/0x24\n     dma_free_attrs+0x9c/0xdc\n     dmam_release+0x18/0x20\n     release_nodes+0x25c/0x28c\n     devres_release_all+0x48/0x4c\n     device_release_driver_internal+0x184/0x1f0\n     device_release_driver+0x14/0x1c\n     unbind_store+0x70/0xb8\n     drv_attr_store+0x24/0x34\n     sysfs_kf_write+0x4c/0x64\n     kernfs_fop_write+0x154/0x1c4\n     __vfs_write+0x34/0x164\n     vfs_write+0xb4/0x16c\n     ksys_write+0x5c/0xbc\n     __arm64_sys_write+0x14/0x1c\n     el0_svc_common+0x98/0x114\n     el0_svc_handler+0x1c/0x24\n     el0_svc+0x8/0xc\n    Code: d51b4234 17fffffa a9bf7bfd 910003fd (b9403404)\n    ---[ end trace 8c564cdd3a1a840f ]---\n\nWhile I\u0027ve bisected this to commit e8e683ae9a736407 (\"iommu/of: Fix\nprobe-deferral\"), and reverting that commit on post-v5.0-rc4 kernels\ndoes fix the problem, this turned out to be a red herring.\n\nOn arm64, arch_teardown_dma_ops() resets dev-\u003edma_ops to NULL.\nHence if a driver has used a managed DMA allocation API, the allocated\nDMA memory will be freed using the direct DMA ops, while it may have\nbeen allocated using a custom DMA ops (iommu_dma_ops in this case).\n\nFix this by reversing the order of the calls to devres_release_all() and\narch_teardown_dma_ops().\n\nSigned-off-by: Geert Uytterhoeven \u003cgeert+renesas@glider.be\u003e\nAcked-by: Christoph Hellwig \u003chch@lst.de\u003e\nReviewed-by: Rafael J. Wysocki \u003crafael.j.wysocki@intel.com\u003e\nCc: stable \u003cstable@vger.kernel.org\u003e\nReviewed-by: Robin Murphy \u003crobin.murphy@arm.com\u003e\n[rm: backport for 4.12-4.19 - kernels before 5.0 will not see\n the crash above, but may get silent memory corruption instead]\nSigned-off-by: Robin Murphy \u003crobin.murphy@arm.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@linuxfoundation.org\u003e\n(cherry picked from commit 6f166975a72c85094ca5364f85efd46b36f0f86a)\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "311736f6f2647b4482711f19311403b2e087a55f", "tree": "d4fb028888b1e9ad685581d1983077ea9abcfb55", "parents": [ "a176b24aa5a256f74bdf37bf3fffa1cfde838374" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Fri Mar 22 10:46:21 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:34 2019 +0900" }, "message": "iommu/ipmmu-vmsa: Fix memory leak when adding master device\n\nCurrently, utlbs_val and asids_val are located and leaked\nwhen the later master device has same IPMMU cache\n\nSince one IPMMU cache can have multiple masters, utlbs_val and\nasids_val should be managed per master device instead\n\nFix it by:\n- Putting utlbs_val and asids_val to backup struct, where we\nwill backup data for the master device\n- Adding proper error handling\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "a176b24aa5a256f74bdf37bf3fffa1cfde838374", "tree": "1d0dd03e7f23bc370994285c51e45cb906452143", "parents": [ "adc2d8f520e43ae9345d68363087bbd1149f4623" ], "author": { "name": "Phil Edworthy", "email": "phil.edworthy@renesas.com", "time": "Thu Aug 18 16:39:14 2016 +0100" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:34 2019 +0900" }, "message": "iommu/ipmmu-vmsa: Allow PCI Host controller to be a proxy for all connected PCI devices\n\nThe IOMMU can\u0027t distinguish between different PCI Functions.\nUse PCI Host controller as a proxy for all connected PCI devices.\n\nSigned-off-by: Phil Edworthy \u003cphil.edworthy@renesas.com\u003e\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "adc2d8f520e43ae9345d68363087bbd1149f4623", "tree": "41a8efc2102a3c7260b83f4e5232f4295360d851", "parents": [ "53043d1897d2f75cbdb428c40e452df110d9eeba" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Thu Mar 07 13:11:25 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:34 2019 +0900" }, "message": "iommu/ipmmu-vmsa: Bypass whitelist check for unsupported SoCs\n\nWhitelist check is specific for Renesas R-Car Gen3 SoCs only.\nBypass the check for other SoCs.\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "53043d1897d2f75cbdb428c40e452df110d9eeba", "tree": "4aa6397eb0adc664959d07533acb4954bc1f76f5", "parents": [ "442e4daf2ba7cee3749f0cc6c6f0b3d15f0804ed" ], "author": { "name": "Hai Nguyen Pham", "email": "hai.pham.ud@renesas.com", "time": "Thu Mar 07 11:41:52 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:34 2019 +0900" }, "message": "iommu/ipmmu-vmsa: Support suspend/resume by default\n\nRemove unnecessary macro guards to support suspend/resume by default\n\nSigned-off-by: Hai Nguyen Pham \u003chai.pham.ud@renesas.com\u003e\n" }, { "commit": "442e4daf2ba7cee3749f0cc6c6f0b3d15f0804ed", "tree": "ddc7008daf1ee2b20b9c7054fcec7160c75601a7", "parents": [ "1381140743fc2acd5b125b9adefad7717fada71b", "42378b1937bb1b6af914cfc0f3bd79d0cd6125e8" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:33 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:33 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.2/ehci_ohci.rc1\u0027 into v4.14.75-ltsi/rcar-3.9.3\n\n* rcar-3.9.2/ehci_ohci.rc1:\n USB: ohci-hcd.c: Add spinlock when disabling OHCI interrupts in ohci_shutdown\n" }, { "commit": "42378b1937bb1b6af914cfc0f3bd79d0cd6125e8", "tree": "ddc7008daf1ee2b20b9c7054fcec7160c75601a7", "parents": [ "1381140743fc2acd5b125b9adefad7717fada71b" ], "author": { "name": "Tho Vu", "email": "tho.vu.wh@rvc.renesas.com", "time": "Wed Feb 13 19:00:15 2019 +0700" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:32 2019 +0900" }, "message": "USB: ohci-hcd.c: Add spinlock when disabling OHCI interrupts in ohci_shutdown\n\nThis patch is used for fixing \u0027irq nobody care\u0027 issue during reboot\n\nHow to reproduce:\n1)Prepare weston enabled environment\n2)Connect USB mouse\n3)Read input from the mouse and reboot\n$ od -tx /dev/input/event0 \u0026\n$ reboot\n4)Move the mouse while system shutdown\nDon\u0027t need to move the mouse after \"reboot: Restarting system\"\n5)Repeat step 3 and step 4 until below error occurs\n\nError log:\nusb 2-1: USB disconnect, device number 2\nirq 156: nobody cared (try booting with the \"irqpoll\" option)\nWorkqueue: usb_hub_wq hub_event\nCall trace:\n...\nusbhid_disconnect+0x4c/0x78\nusb_unbind_interface+0x6c/0x2a8\ndevice_release_driver_internal+0x174/0x208\ndevice_release_driver+0x14/0x20\nbus_remove_device+0x114/0x128\ndevice_del+0x1ac/0x300\nusb_disable_device+0x8c/0x200\nusb_disconnect+0xb4/0x218\n...\nhandlers:\nusb_hcd_irq\nDisabling IRQ #156\n\nThis issue occurs due to race condition between ohci_irq()\ninterrupt handler and ohci_shutdown()\nAdding spin_lock_irq() to prevent interrupt raising while ohci is shutting\ndown can fix this issue.\n\nWhen host controller dies, lock will be held by io_watchdog_func before\nohci_shutdown, so locking should be skipped in this case to prevent\ndeadlock\n\nSigned-off-by: Tho Vu \u003ctho.vu.wh@rvc.renesas.com\u003e\n" }, { "commit": "1381140743fc2acd5b125b9adefad7717fada71b", "tree": "4fb582392c868dad74ae8708d5e28b140818c3e3", "parents": [ "71bf321b544c72ee6582839f8b7bd36acce577e5", "2fba5e0e94db930a24af406a39cd3a2c0353f15b" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:31 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:31 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.2/adv748x.rc1\u0027 into v4.14.75-ltsi/rcar-3.9.3\n\n* rcar-3.9.2/adv748x.rc1:\n media: i2c: adv748x: Use devm to allocate the device struct\n media: i2c: adv7482: Fix wait procedure usleep_range from msleep\n" }, { "commit": "2fba5e0e94db930a24af406a39cd3a2c0353f15b", "tree": "4fb582392c868dad74ae8708d5e28b140818c3e3", "parents": [ "0786087e9766327cc9f741013a3f54de87783bb3" ], "author": { "name": "Steve Longerbeam", "email": "steve_longerbeam@mentor.com", "time": "Fri Jan 11 16:17:03 2019 +0000" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:31 2019 +0900" }, "message": "media: i2c: adv748x: Use devm to allocate the device struct\n\nSwitch to devm_kzalloc() when allocating the adv748x device struct.\n\nThe sizeof() is updated to determine the correct allocation size from\nthe dereferenced pointer type rather than hardcoding the struct type.\n\nSigned-off-by: Steve Longerbeam \u003csteve_longerbeam@mentor.com\u003e\nReviewed-by: Kieran Bingham \u003ckieran.bingham+renesas@ideasonboard.com\u003e\n[Kieran: Change sizeof() to dereference the pointer type]\nSigned-off-by: Kieran Bingham \u003ckieran.bingham+renesas@ideasonboard.com\u003e\nReviewed-by: Niklas Söderlund \u003cniklas.soderlund+renesas@ragnatech.se\u003e\nLink: https://patchwork.kernel.org/patch/10760277/\n[koji.matsuoka.xm: the part of the patch for kernel v4.14.75\nwas rebased and imported]\nSigned-off-by: Koji Matsuoka \u003ckoji.matsuoka.xm@renesas.com\u003e\n" }, { "commit": "0786087e9766327cc9f741013a3f54de87783bb3", "tree": "ff8ed4c9eff8b2806636c5a978802ccad922b4d2", "parents": [ "71bf321b544c72ee6582839f8b7bd36acce577e5" ], "author": { "name": "Koji Matsuoka", "email": "koji.matsuoka.xm@renesas.com", "time": "Fri Jan 11 15:43:44 2019 +0000" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:31 2019 +0900" }, "message": "media: i2c: adv7482: Fix wait procedure usleep_range from msleep\n\nBy Documentation/timers/timers-howto.txt, when waiting 20ms from 10us,\nit is correct to use usleep_range. this patch corrects it.\n\nSigned-off-by: Koji Matsuoka \u003ckoji.matsuoka.xm@renesas.com\u003e\n(cherry picked from horms/renesas-bsp commit af0cdba377bc\n(\"media: i2c: adv7482: Fix wait procedure usleep_range from msleep\"))\nSigned-off-by: Steve Longerbeam \u003csteve_longerbeam@mentor.com\u003e\nLink: https://patchwork.kernel.org/patch/10758319/\n[koji.matsuoka.xm: the part of the patch for kernel v4.14.75\nwas rebased and imported]\nSigned-off-by: Koji Matsuoka \u003ckoji.matsuoka.xm@renesas.com\u003e\n" }, { "commit": "71bf321b544c72ee6582839f8b7bd36acce577e5", "tree": "93a7566d643ded37f3bf68dcb1e385e83ffc963c", "parents": [ "7165b409091f5c3fe8bc9a602613564f4a330034", "cd9f801c4b89dfac62a75b3e7ed30a0d28884a92" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:30 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:30 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.2/rcar-csi2.rc1\u0027 into v4.14.75-ltsi/rcar-3.9.3\n\n* rcar-3.9.2/rcar-csi2.rc1:\n rcar-vin: rcar-csi2: Fix comment of VCDT/VCDT2 register\n" }, { "commit": "cd9f801c4b89dfac62a75b3e7ed30a0d28884a92", "tree": "93a7566d643ded37f3bf68dcb1e385e83ffc963c", "parents": [ "7165b409091f5c3fe8bc9a602613564f4a330034" ], "author": { "name": "Koji Matsuoka", "email": "koji.matsuoka.xm@renesas.com", "time": "Tue Jan 22 16:29:42 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:29 2019 +0900" }, "message": "rcar-vin: rcar-csi2: Fix comment of VCDT/VCDT2 register\n\nAccording to latest H/W manual v1.50, the description of channel\nnumber in the VCDT/VCDT2 register is decremented by one.\nTherefore, this patch fixes it about comment.\n\nSigned-off-by: Koji Matsuoka \u003ckoji.matsuoka.xm@renesas.com\u003e\n" }, { "commit": "7165b409091f5c3fe8bc9a602613564f4a330034", "tree": "d7d0cf74f00f1255025814cdc1b23b6838f54f49", "parents": [ "505e5f61f280cc4a06942d8f4493d10af4011ee7", "620f3e493e55cf958dfadfa40b728ab921e5ab55" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:28 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:28 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.2/rcar-vin.rc2\u0027 into v4.14.75-ltsi/rcar-3.9.3\n\n* rcar-3.9.2/rcar-vin.rc2:\n media: rcar-vin: Allow independent VIN link enablement\n" }, { "commit": "620f3e493e55cf958dfadfa40b728ab921e5ab55", "tree": "d7d0cf74f00f1255025814cdc1b23b6838f54f49", "parents": [ "505e5f61f280cc4a06942d8f4493d10af4011ee7" ], "author": { "name": "Steve Longerbeam", "email": "slongerbeam@gmail.com", "time": "Mon Jan 14 17:10:19 2019 -0800" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:28 2019 +0900" }, "message": "media: rcar-vin: Allow independent VIN link enablement\n\nThere is a block of code in rvin_group_link_notify() that prevents\nenabling a link to a VIN node if any entity in the media graph is\nin use. This prevents enabling a VIN link even if there is an in-use\nentity somewhere in the graph that is independent of the link\u0027s\npipeline.\n\nFor example, the code block will prevent enabling a link from\nthe first rcar-csi2 receiver to a VIN node even if there is an\nenabled link somewhere far upstream on the second independent\nrcar-csi2 receiver pipeline.\n\nIf this code block is meant to prevent modifying a link if any entity\nin the graph is actively involved in streaming (because modifying\nthe CHSEL register fields can disrupt any/all running streams), then\nthe entities stream counts should be checked rather than the use counts.\n\n(There is already such a check in __media_entity_setup_link() that verifies\nthe stream_count of the link\u0027s source and sink entities are both zero,\nbut that is insufficient, since there should be no running streams in\nthe entire graph).\n\nModify the code block to check the entity stream_count instead of the\nuse_count (and elaborate on the comment). VIN node links can now be\nenabled even if there are other independent in-use entities that are\nnot streaming.\n\nFixes: c0cc5aef31 (\"media: rcar-vin: add link notify for Gen3\")\n\nSigned-off-by: Steve Longerbeam \u003cslongerbeam@gmail.com\u003e\nReviewed-by: Niklas Söderlund \u003cniklas.soderlund+renesas@ragnatech.se\u003e\nLink: https://patchwork.kernel.org/patch/10763675/\n[koji.matsuoka.xm: the part of the patch for kernel v4.14.75\nwas rebased and imported]\nSigned-off-by: Koji Matsuoka \u003ckoji.matsuoka.xm@renesas.com\u003e\n" }, { "commit": "505e5f61f280cc4a06942d8f4493d10af4011ee7", "tree": "180b2425743509889034464bfc7c6d4968787725", "parents": [ "352918e939cd8eb409e1ec70a1f47f322a4ea0d9", "5a5e59b87990d7f3d91a9e19ccaecbec0896cd1f" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:27 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:27 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.2/vsp-du.rc1\u0027 into v4.14.75-ltsi/rcar-3.9.3\n\n* rcar-3.9.2/vsp-du.rc1:\n drm: rcar-du: Fix loop procedure in scatter gather page set\n" }, { "commit": "5a5e59b87990d7f3d91a9e19ccaecbec0896cd1f", "tree": "180b2425743509889034464bfc7c6d4968787725", "parents": [ "352918e939cd8eb409e1ec70a1f47f322a4ea0d9" ], "author": { "name": "Koji Matsuoka", "email": "koji.matsuoka.xm@renesas.com", "time": "Fri Jan 11 12:21:05 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:26 2019 +0900" }, "message": "drm: rcar-du: Fix loop procedure in scatter gather page set\n\nOriginally the variable of \"i\" is used for the loop count of\nthe number of format planes in rcar_du_vsp_plane_prepare_fb\nfunction and should be not used the same \"i\" as the loop count\nof sg_set_page.\n\nIt is affected when the number of format planes is 2 (NV12 format\netc.) and 3 (YUV420 format etc.).\nFor the number of format planes is 1 (RGB565, ARGB888, YUYV etc),\nthis function works fine.\n\nThis patch solves its problem.\n\nFixes: c424cd4724 (\"drm: rcar-du: Allow importing non-contiguous\ndma-buf with VSP\")\n\nReviewed-by: Laurent Pinchart \u003claurent.pinchart@ideasonboard.com\u003e\nSigned-off-by: Koji Matsuoka \u003ckoji.matsuoka.xm@renesas.com\u003e\n" }, { "commit": "352918e939cd8eb409e1ec70a1f47f322a4ea0d9", "tree": "e2023e1b898e5bd43e6b00cc71cf8e32f71aa386", "parents": [ "046cd21658ae8228b58edd8f08fc97b567b1f3e2", "be1a7ed785516c6d694f8451525d9e74deabb816" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:25 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:25 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.2/audio.rc2\u0027 into v4.14.75-ltsi/rcar-3.9.3\n\n* rcar-3.9.2/audio.rc2:\n ASoC: rsnd: fixup MIX kctrl registration\n ASoC: rsnd: tidyup registering method for rsnd_kctrl_new()\n ASoC: rsnd: fixup rsnd_ssi_master_clk_start() user count check\n ASoC: rsnd: update BSDSR/BSDISR handling\n" }, { "commit": "be1a7ed785516c6d694f8451525d9e74deabb816", "tree": "e2023e1b898e5bd43e6b00cc71cf8e32f71aa386", "parents": [ "33b3a4fc667c93bb6605bb06ba9b7528dc1bda38" ], "author": { "name": "Kuninori Morimoto", "email": "kuninori.morimoto.gx@renesas.com", "time": "Fri Feb 01 16:49:30 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:25 2019 +0900" }, "message": "ASoC: rsnd: fixup MIX kctrl registration\n\nRenesas sound device has many IPs and many situations.\nIf platform/board uses MIXer, situation will be more complex.\nTo avoid duplicate DVC kctrl registration when MIXer was used,\nit had original flags.\nBut it was issue when sound card was re-binded, because\nno one can\u0027t cleanup this flags then.\n\nTo solve this issue, commit 9c698e8481a15237a (\"ASoC: rsnd: tidyup\nregistering method for rsnd_kctrl_new()\") checks registered\ncard-\u003econtrols, because if card was re-binded, these were cleanuped\nautomatically. This patch could solve re-binding issue.\nBut, it start to avoid MIX kctrl.\n\nTo solve these issues, we need below.\nTo avoid card re-binding issue: check registered card-\u003econtrols\nTo avoid duplicate DVC registration: check registered rsnd_kctrl_cfg\nTo allow multiple MIX registration: check registered rsnd_kctrl_cfg\nThis patch do it.\n\nFixes: 9c698e8481a15237a (\"ASoC: rsnd: tidyup registering method for rsnd_kctrl_new()\")\nReported-by: Jiada Wang \u003cjiada_wang@mentor.com\u003e\nSigned-off-by: Kuninori Morimoto \u003ckuninori.morimoto.gx@renesas.com\u003e\nTested-by: Jiada Wang \u003cjiada_wang@mentor.com\u003e\nSigned-off-by: Mark Brown \u003cbroonie@kernel.org\u003e\n(cherry picked from commit 7aea8a9d71d54f449f49e20324df06341cc18395)\nSigned-off-by: Hiroyuki Yokoyama \u003chiroyuki.yokoyama.vx@renesas.com\u003e\n" }, { "commit": "33b3a4fc667c93bb6605bb06ba9b7528dc1bda38", "tree": "85874535a15bca880568d6f0202147030e08a4e5", "parents": [ "2cb2d625671681f0ff94614b2029b072cb61fdeb" ], "author": { "name": "Kuninori Morimoto", "email": "kuninori.morimoto.gx@renesas.com", "time": "Tue Nov 27 07:35:34 2018 +0000" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:25 2019 +0900" }, "message": "ASoC: rsnd: tidyup registering method for rsnd_kctrl_new()\n\nCurrent rsnd dvc.c is using flags to avoid duplicating register for\nMIXer case. OTOH, commit e894efef9ac7 (\"ASoC: core: add support to card\nrebind\") allows to rebind sound card without rebinding all drivers.\n\nBecause of above patch and dvc.c flags, it can\u0027t re-register kctrl if\nonly sound card was rebinded, because dvc is keeping old flags.\n(Of course it will be no problem if rsnd driver also be rebinded,\nbut it is not purpose of above patch).\n\nThis patch checks current card registered kctrl when registering.\nIn MIXer case, it can avoid duplicate register if card already has same\nkctrl. In rebind case, it can re-register kctrl because card registered\nkctl had been removed when unbinding.\n\nThis patch is updated version of commit b918f1bc7f1ce (\"ASoC: rsnd: DVC\nkctrl sets once\")\n\nReported-by: Nguyen Viet Dung \u003cdung.nguyen.aj@renesas.com\u003e\nSigned-off-by: Kuninori Morimoto \u003ckuninori.morimoto.gx@renesas.com\u003e\nTested-by: Nguyen Viet Dung \u003cdung.nguyen.aj@renesas.com\u003e\nCc: Hiroyuki Yokoyama \u003chiroyuki.yokoyama.vx@renesas.com\u003e\nSigned-off-by: Mark Brown \u003cbroonie@kernel.org\u003e\n(cherry picked from commit 9c698e8481a15237a5b1db5f8391dd66d59e42a4)\nSigned-off-by: Hiroyuki Yokoyama \u003chiroyuki.yokoyama.vx@renesas.com\u003e\n" }, { "commit": "2cb2d625671681f0ff94614b2029b072cb61fdeb", "tree": "e1d551531995984a4a106ecc96bc2122ea831e17", "parents": [ "04547c504230ee0f90d7d03dcc8c0ce5a4b72dfd" ], "author": { "name": "Kuninori Morimoto", "email": "kuninori.morimoto.gx@renesas.com", "time": "Tue Feb 05 09:46:43 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:25 2019 +0900" }, "message": "ASoC: rsnd: fixup rsnd_ssi_master_clk_start() user count check\n\ncommit 4d230d1271064 (\"ASoC: rsnd: fixup not to call clk_get/set\nunder non-atomic\") added new rsnd_ssi_prepare() and moved\nrsnd_ssi_master_clk_start() to .prepare.\nBut, ssi user count (\u003d ssi-\u003eusrcnt) is incremented at .init\n(\u003d rsnd_ssi_init()).\nBecause of these timing exchange, ssi-\u003eusrcnt check at\nrsnd_ssi_master_clk_start() should be adjusted.\nOtherwise, 2nd master clock setup will be no check.\nThis patch fixup this issue.\n\nFixes: commit 4d230d1271064 (\"ASoC: rsnd: fixup not to call clk_get/set under non-atomic\")\nReported-by: Yusuke Goda \u003cyusuke.goda.sx@renesas.com\u003e\nReported-by: Valentine Barshak \u003cvalentine.barshak@cogentembedded.com\u003e\nSigned-off-by: Kuninori Morimoto \u003ckuninori.morimoto.gx@renesas.com\u003e\nTested-by: Yusuke Goda \u003cyusuke.goda.sx@renesas.com\u003e\nSigned-off-by: Mark Brown \u003cbroonie@kernel.org\u003e\n(cherry picked from commit d9111d36024de07784f2e1ba2ccf70b16035f378)\nSigned-off-by: Hiroyuki Yokoyama \u003chiroyuki.yokoyama.vx@renesas.com\u003e\n" }, { "commit": "04547c504230ee0f90d7d03dcc8c0ce5a4b72dfd", "tree": "6c3119d69ac32ca514854ad54b5a2cc56472e1a3", "parents": [ "046cd21658ae8228b58edd8f08fc97b567b1f3e2" ], "author": { "name": "Kuninori Morimoto", "email": "kuninori.morimoto.gx@renesas.com", "time": "Tue Dec 25 14:05:28 2018 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:24 2019 +0900" }, "message": "ASoC: rsnd: update BSDSR/BSDISR handling\n\nCurrent BSDSR/BSDISR are using temporary/generic settings, but it can\u0027t\nhandle all SRCx/SoC. It needs to handle correctry.\nOtherwise, sampling rate converted sound channel will be broken if it\nwas TDM. One note is that it needs to overwrite settings on E3 case.\n\nSigned-off-by: Kuninori Morimoto \u003ckuninori.morimoto.gx@renesas.com\u003e\nTested-by: chaoliang qin \u003cchaoliang.qin.jg@renesas.com\u003e\nTested-by: Yusuke Goda \u003cyusuke.goda.sx@renesas.com\u003e\nSigned-off-by: Mark Brown \u003cbroonie@kernel.org\u003e\n(cherry picked from commit 7674bec4fc09e85803a8f2bd26a013d0076a80a9)\nSigned-off-by: Hiroyuki Yokoyama \u003chiroyuki.yokoyama.vx@renesas.com\u003e\n" }, { "commit": "046cd21658ae8228b58edd8f08fc97b567b1f3e2", "tree": "9326d95653641f7acf5ada30a2b75c984119d5da", "parents": [ "f65f4b02bb556dd721621a7e0457358aff4f02b1", "ae17a13f2667bdeac406e453a75479a559f5896a" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:23 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:23 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.2/i2c-rcar.rc1\u0027 into v4.14.75-ltsi/rcar-3.9.3\n\n* rcar-3.9.2/i2c-rcar.rc1:\n i2c: Make i2c_unregister_device() NULL-aware\n i2c: dev: mark RDWR buffers as DMA_SAFE\n i2c compat ioctls: move to -\u003ecompat_ioctl()\n Revert \"i2c: dev: mark RDWR buffers as DMA_SAFE\"\n" }, { "commit": "ae17a13f2667bdeac406e453a75479a559f5896a", "tree": "9326d95653641f7acf5ada30a2b75c984119d5da", "parents": [ "0bd03a21d13866cc348c096e5495642ed32b86c3" ], "author": { "name": "Andy Shevchenko", "email": "andriy.shevchenko@linux.intel.com", "time": "Tue Oct 31 16:21:35 2017 +0200" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:23 2019 +0900" }, "message": "i2c: Make i2c_unregister_device() NULL-aware\n\nIt\u0027s a common pattern to be NULL-aware when freeing resources.\n\nSigned-off-by: Andy Shevchenko \u003candriy.shevchenko@linux.intel.com\u003e\nSigned-off-by: Wolfram Sang \u003cwsa@the-dreams.de\u003e\n(cherry picked from commit 7b43dd19c9b13a3f5478b9d88a49a5495399ad29)\nSigned-off-by: Hiromitsu Yamasaki \u003chiromitsu.yamasaki.ym@renesas.com\u003e\n\nConflicts:\n\tdrivers/i2c/i2c-core-base.c\n" }, { "commit": "0bd03a21d13866cc348c096e5495642ed32b86c3", "tree": "195fa48478f2590eb42eb5fe2475399218cc83ed", "parents": [ "0e2bb2442140e9638d2062dd46c57a9fbc63357b" ], "author": { "name": "Wolfram Sang", "email": "wsa+renesas@sang-engineering.com", "time": "Sat Nov 04 21:20:03 2017 +0100" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:23 2019 +0900" }, "message": "i2c: dev: mark RDWR buffers as DMA_SAFE\n\nReviewed-by: Jonathan Cameron \u003cJonathan.Cameron@huawei.com\u003e\nSigned-off-by: Wolfram Sang \u003cwsa+renesas@sang-engineering.com\u003e\nSigned-off-by: Wolfram Sang \u003cwsa@the-dreams.de\u003e\n(cherry picked from commit 978336d48d887d6deb7793e0d20a4673f357fb8e)\nSigned-off-by: Hiromitsu Yamasaki \u003chiromitsu.yamasaki.ym@renesas.com\u003e\n" }, { "commit": "0e2bb2442140e9638d2062dd46c57a9fbc63357b", "tree": "ad79e0b5bb46d350364030c42edae82c59f18818", "parents": [ "4ce8872d7ebf8f5e45d14b35865628f98adb675f" ], "author": { "name": "Al Viro", "email": "viro@zeniv.linux.org.uk", "time": "Wed Sep 20 01:02:27 2017 -0400" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:23 2019 +0900" }, "message": "i2c compat ioctls: move to -\u003ecompat_ioctl()\n\nSigned-off-by: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\n(cherry picked from commit 7d5cb45655f2e9e37ef75d18f50c0072ef14a38b)\nSigned-off-by: Hiromitsu Yamasaki \u003chiromitsu.yamasaki.ym@renesas.com\u003e\n" }, { "commit": "4ce8872d7ebf8f5e45d14b35865628f98adb675f", "tree": "647f0e938c9422864db1d13ab597276f62b1157f", "parents": [ "f65f4b02bb556dd721621a7e0457358aff4f02b1" ], "author": { "name": "Hiromitsu Yamasaki", "email": "hiromitsu.yamasaki.ym@renesas.com", "time": "Thu Feb 14 14:48:14 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:22 2019 +0900" }, "message": "Revert \"i2c: dev: mark RDWR buffers as DMA_SAFE\"\n\nThis reverts commit 7e15a55865897a5ea4c1bbb5f6338b0b75c9d898.\nThe reason is to maintain compatibility with the v4.14.35 kernel.\n\nSigned-off-by: Hiromitsu Yamasaki \u003chiromitsu.yamasaki.ym@renesas.com\u003e\n" }, { "commit": "f65f4b02bb556dd721621a7e0457358aff4f02b1", "tree": "bb3cf4f863dc4da33e6842ff8e8e9c0d88401e6a", "parents": [ "06b0b90a4d223c158cd460d430207f823c1ef8b7", "caabf4e7396a2b9bef48f180d6dd3644b243c8d1" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:21 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:21 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.2/sd_mmc.rc3\u0027 into v4.14.75-ltsi/rcar-3.9.3\n\n* rcar-3.9.2/sd_mmc.rc3:\n mmc: renesas_sdhi: max_segs_on_iommu applies only no-sdio port\n mmc: tmio: No memory size limitation if runs on IOMMU\n mmc: renesas_sdhi: add max_segs_on_iommu to use large max_segs\n mmc: renesas_sdhi: Fix hang up in HS400 timing mode selection\n mmc: tmio: fix access width of Block Count Register\n mmc: renesas_sdhi_internal_dmac: Fix DMA buffer alignment from 8 to 128-bytes\n mmc: renesas_sdhi: Change HS400 manual calibration value for r8a77990\n mmc: renesas_sdhi_internal_dmac: mask DMAC interrupts\n" }, { "commit": "caabf4e7396a2b9bef48f180d6dd3644b243c8d1", "tree": "bb3cf4f863dc4da33e6842ff8e8e9c0d88401e6a", "parents": [ "0533172faca88bd946493f719bca659f9a4cc525" ], "author": { "name": "Takeshi Saito", "email": "takeshi.saito.xv@renesas.com", "time": "Wed Mar 20 18:18:10 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:21 2019 +0900" }, "message": "mmc: renesas_sdhi: max_segs_on_iommu applies only no-sdio port\n\nIn Gen3 IOMMU, SG entries page size expects a multiple of PAGE_SIZE.\nHowever, SG entries are allocated in small segment in SDIO.\nmax_segs_on_iommu applies only \"no-sdio\" port in DeviceTree.\n\nIn Atheros SDIO WiFi, the SDIO firmware crashes during the execution\nof iperf3 command.\n\niperf3 -c \u003cIP address\u003e\n\n[ 53.457669] ath6kl: firmware crashed\n[ 53.473327] ath6kl: crash dump:\n:\n\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\n" }, { "commit": "0533172faca88bd946493f719bca659f9a4cc525", "tree": "422af25290656347005b177e2ed6a75ae3f9c80d", "parents": [ "5c71e29dfff3192e2babf91c48827a7a95663b10" ], "author": { "name": "Yoshihiro Shimoda", "email": "yoshihiro.shimoda.uh@renesas.com", "time": "Wed Feb 20 14:07:48 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:20 2019 +0900" }, "message": "mmc: tmio: No memory size limitation if runs on IOMMU\n\nThis patch adds a condition to avoid memory size limitaion of\nswiotlb if the driver runs on IOMMU.\n\nTested-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\nSigned-off-by: Yoshihiro Shimoda \u003cyoshihiro.shimoda.uh@renesas.com\u003e\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\n" }, { "commit": "5c71e29dfff3192e2babf91c48827a7a95663b10", "tree": "28e04bf6a80a838061f25fd79f4591265ef6d378", "parents": [ "addfe9203290e3c274bca15e64e3f11638649e66" ], "author": { "name": "Yoshihiro Shimoda", "email": "yoshihiro.shimoda.uh@renesas.com", "time": "Wed Feb 20 17:15:55 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:20 2019 +0900" }, "message": "mmc: renesas_sdhi: add max_segs_on_iommu to use large max_segs\n\nThis patch adds a new parameter max_segs_on_iommu into\nrenesas_sdhi_of_data to use large max_segs value If IOMMU is\nenabled. In case of the SDHI internal DMAC with IOMMU is enabled,\nsince it can use multiple segments, such environment may improve\nperformance, especially small sg buffers are used.\n\nTested-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\nSigned-off-by: Yoshihiro Shimoda \u003cyoshihiro.shimoda.uh@renesas.com\u003e\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\n" }, { "commit": "addfe9203290e3c274bca15e64e3f11638649e66", "tree": "170d4105af041f3a3f9a70d9072ec126c6457eb3", "parents": [ "6d483c3415d3e3c7daa3c0a1adfe8e84a401f4a2" ], "author": { "name": "Takeshi Saito", "email": "takeshi.saito.xv@renesas.com", "time": "Fri Mar 01 17:23:46 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:20 2019 +0900" }, "message": "mmc: renesas_sdhi: Fix hang up in HS400 timing mode selection\n\nIn HS400 timing mode selection, SD clock is switched the\nfollowing.\n1) HS200 (200MHz) for tuning\n2) High Speed (\u003c\u003d 52MHz) for select HS400 mode (card)\n3) HS400 (200MHz)\n\nIn R-Car Gen3 SDHI, internal SCC modules uses SDnH clock.\nIt is controlled by SDnCKCR.STPnHCK bit in CPG.\nWhen SD clock is less than High Speed, SDnH clock is stopped.\nAnd SDnH clock is supplied with 100MHz or more in Clock divider\ntable of CPG in R-Car Gen3.\nIt is the recommended setting of H/W.\n\nTherefore, when bus timing is SDR104/HS200/HS400 mode, minimum\nfrequency of SDHI clock is 100MHz.\n\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\n" }, { "commit": "6d483c3415d3e3c7daa3c0a1adfe8e84a401f4a2", "tree": "5f81fdab001b22f9c6503dd3780f4e2d9f2480c0", "parents": [ "6331c5f1c6a6f543ab27d12dfe8112b3959d2edd" ], "author": { "name": "Takeshi Saito", "email": "takeshi.saito.xv@renesas.com", "time": "Thu Feb 21 20:38:05 2019 +0100" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:20 2019 +0900" }, "message": "mmc: tmio: fix access width of Block Count Register\n\nIn R-Car Gen2 or later, the maximum number of transfer blocks are\nchanged from 0xFFFF to 0xFFFFFFFF. Therefore, Block Count Register\nshould use iowrite32().\n\nIf another system (U-boot, Hypervisor OS, etc) uses bit[31:16], this\nvalue will not be cleared. So, SD/MMC card initialization fails.\n\nSo, check for the bigger register and use appropriate write. Also, mark\nthe register as extended on Gen2.\n\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\n[wsa: use max_blk_count in if(), add Gen2, update commit message]\nSigned-off-by: Wolfram Sang \u003cwsa+renesas@sang-engineering.com\u003e\nCc: stable@kernel.org\nReviewed-by: Simon Horman \u003chorms+renesas@verge.net.au\u003e\nPatchwork: https://patchwork.kernel.org/patch/10824707/\n[saito: fixed typo in comment]\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\n" }, { "commit": "6331c5f1c6a6f543ab27d12dfe8112b3959d2edd", "tree": "5c75830236455636baf77db27e70d9a6b97b5f7c", "parents": [ "b2e044a3602f7f9ffe6c61b6655e6b0b283d85c4" ], "author": { "name": "Takeshi Saito", "email": "takeshi.saito.xv@renesas.com", "time": "Fri Jan 18 17:42:36 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:19 2019 +0900" }, "message": "mmc: renesas_sdhi_internal_dmac: Fix DMA buffer alignment from 8 to 128-bytes\n\nThe internal DMAC buffer alignment condition of R-Car Gen3 SDHI\nHW is 128 bytes before. It is correct, but HW manual have had a\nmistake as 8 bytes. The driver is fixed with 128 bytes according\nto the modification of HW manual, this time.\n\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\n" }, { "commit": "b2e044a3602f7f9ffe6c61b6655e6b0b283d85c4", "tree": "080d658f75fcd3c05de6853de6a6a05b264d002c", "parents": [ "de7ed565e22883e71c5610c9ea651ceb1aa696a5" ], "author": { "name": "Takeshi Saito", "email": "takeshi.saito.xv@renesas.com", "time": "Fri Jan 18 08:44:07 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:19 2019 +0900" }, "message": "mmc: renesas_sdhi: Change HS400 manual calibration value for r8a77990\n\nAccording to latest SDHI HW manual, HS400 manual calibration value\nfor r8a77990 is changed.\n\noffset\u003d 0 (not change)\ncalibration code\u003d auto calibration value -4\n\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\n" }, { "commit": "de7ed565e22883e71c5610c9ea651ceb1aa696a5", "tree": "f40ec02394710f7da35279a48e540e85d8a93f5d", "parents": [ "06b0b90a4d223c158cd460d430207f823c1ef8b7" ], "author": { "name": "Sergei Shtylyov", "email": "sergei.shtylyov@cogentembedded.com", "time": "Wed Aug 22 21:22:26 2018 +0300" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:19 2019 +0900" }, "message": "mmc: renesas_sdhi_internal_dmac: mask DMAC interrupts\n\nI have encountered an interrupt storm during the eMMC chip probing (and\nthe chip finally didn\u0027t get detected). It turned out that U-Boot left\nthe SDHI DMA interrupts enabled while the Linux driver didn\u0027t use those.\nMasking those interrupts in renesas_sdhi_internal_dmac_request_dma() gets\nrid of both issues...\n\nSigned-off-by: Sergei Shtylyov \u003csergei.shtylyov@cogentembedded.com\u003e\nReviewed-by: Wolfram Sang \u003cwsa+renesas@sang-engineering.com\u003e\nFixes: 2a68ea7896e3 (\"mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC\")\nCc: stable@vger.kernel.org # v4.14+\nSigned-off-by: Ulf Hansson \u003culf.hansson@linaro.org\u003e\n(cherry picked from commit d2332f887ddfba50fee93b8e1736376517c2df0c)\n[saito: adjust context.]\nSigned-off-by: Takeshi Saito \u003ctakeshi.saito.xv@renesas.com\u003e\n" }, { "commit": "06b0b90a4d223c158cd460d430207f823c1ef8b7", "tree": "79dffe7e06426a18a28735bde2714c6bcb597f8d", "parents": [ "0043eec1e00e4ed5265fca2fb36385c9b184bf75", "083b06046249b84eea2cf19476cd5b8afd7cea4f" ], "author": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:18 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:18 2019 +0900" }, "message": "Merge branch \u0027rcar-3.9.2/dmae.rc1\u0027 into v4.14.75-ltsi/rcar-3.9.3\n\n* rcar-3.9.2/dmae.rc1:\n dmaengine: sh: rcar-dmac: Fix glitch in dmaengine_tx_status\n dmaengine: sh: rcar-dmac: With cyclic DMA residue 0 is valid\n" }, { "commit": "083b06046249b84eea2cf19476cd5b8afd7cea4f", "tree": "79dffe7e06426a18a28735bde2714c6bcb597f8d", "parents": [ "0c7a66e6849d205d4443ee7d8bdd39c43e0e36e1" ], "author": { "name": "Dirk Behme", "email": "dirk.behme@de.bosch.com", "time": "Thu Mar 07 14:26:13 2019 +0900" }, "committer": { "name": "Ryo Kataoka", "email": "ryo.kataoka.wt@renesas.com", "time": "Fri Mar 22 20:50:18 2019 +0900" }, "message": "dmaengine: sh: rcar-dmac: Fix glitch in dmaengine_tx_status\n\nThe tx_status poll in the rcar_dmac driver reads the status register\nwhich indicates which chunk is busy (DMACHCRB). Afterwards the point\ninside the chunk is read from DMATCRB. It is possible that the chunk\nhas changed between the two reads. The result is a non-monotonous\nincrease of the residue. Fix this by introducing a \u0027safe read\u0027 logic.\n\nFixes: 73a47bd0da66 (\"dmaengine: rcar-dmac: use TCRB instead of TCR for residue\")\nSigned-off-by: Achim Dahlhoff \u003cAchim.Dahlhoff@de.bosch.com\u003e\nSigned-off-by: Dirk Behme \u003cdirk.behme@de.bosch.com\u003e\nCc: \u003cstable@vger.kernel.org\u003e # v4.16+\nLink: https://patchwork.kernel.org/patch/10839057/\nSigned-off-by: Hiroyuki Yokoyama \u003chiroyuki.yokoyama.vx@renesas.com\u003e\n" } ], "next": "0c7a66e6849d205d4443ee7d8bdd39c43e0e36e1" }