tag d80a356abf6cde2dc6c7861bd0389952c54e1653
tagger Simon Horman <horms@verge.net.au> Fri Nov 27 10:15:30 2015 +0900
object c8d9fdbe2d648caaa510d45dc13eba2e9957140b

Second Round of Renesas ARM Based SoC DT Updates for v4.5

* sh73a0, r8a7740: Add L2 cache-controller node
* r8a7791, r8a7794: remove deprecated #gpio-range-cells
* r8a7793: Add DU support and enable for VGA port
* r8a7790: switch console back to scif0
* alt: Correct ether and scif2 pinmux
* koelsch: Correct hdmi pinmux
* silk, lager, porter, bockw: Move SPI FLASH partitions to subnode
* bockw: Add schi0 pinmux

commit c8d9fdbe2d648caaa510d45dc13eba2e9957140b
author Geert Uytterhoeven <geert+renesas@glider.be> Mon Nov 23 14:56:00 2015 +0100
committer Simon Horman <horms+renesas@verge.net.au> Wed Nov 25 10:42:38 2015 +0900
tree 5ffdb3d00330f7df26039f04c4155b3f6ba4b69c
parent 374e70075e58acfe922869aad1202b29f8fb76f5

ARM: shmobile: sh73a0 dtsi: Add L2 cache-controller node

Add the missing L2 cache-controller node, and link the CPU nodes to it.
This will allow migration to the generic l2c OF initialization.

The L2 cache is an ARM L2C-310 (r3p1), of size 512 KiB (64 KiB x 8
ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>