tag 268dcae6dbbac97aa2381dad4e5fd8391c155faa
tagger Simon Horman <horms@verge.net.au> Fri Mar 15 11:10:09 2019 +0100
object c21cd4ae82e169b394139243684aaacf31bfcdf8

Renesas ARM Based SoC Fixes for v5.1

R-Car Gen3 E3 (r8a77990) and RZ/G2E (r8a774c0) SoCs:
* Correct SCIF5 DMA channels

commit c21cd4ae82e169b394139243684aaacf31bfcdf8
author Geert Uytterhoeven <geert+renesas@glider.be> Thu Feb 21 15:04:28 2019 +0100
committer Simon Horman <horms+renesas@verge.net.au> Mon Feb 25 10:37:55 2019 +0100
tree 7877fa44db2abb462f67a6c5a955c7d0cc3a909a
parent e20119f7eaaaf6aad5b44f35155ce500429e17f6

arm64: dts: renesas: r8a774c0: Fix SCIF5 DMA channels

Correct the DMA channels for SCIF5 from 16..47 to 0..15, as was done for
R-Car E3.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 2660a6af690ebbb4 ("arm64: dts: renesas: r8a774c0: Add SCIF and HSCIF nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>