)]}'
{
  "commit": "082ad5ed078516972571060b54643a0777486071",
  "tree": "78f20a6c157ab6bdfb4a8530da150435fc76c2d9",
  "parents": [
    "835d06ee7ef0c2fc2adcf5bae5355c8bad900c21"
  ],
  "author": {
    "name": "Jason Gunthorpe",
    "email": "jgg@nvidia.com",
    "time": "Fri May 08 11:53:07 2026 -0300"
  },
  "committer": {
    "name": "Joerg Roedel",
    "email": "joerg.roedel@amd.com",
    "time": "Tue May 19 10:48:09 2026 +0200"
  },
  "message": "iommu/riscv: Add NAPOT range invalidation support\n\nUse the RISC-V IOMMU Address Range Invalidation extension\n(capabilities.S, spec section 9.3) to invalidate an IOVA range with\na single IOTINVAL.VMA command using NAPOT-encoded addressing.\n\nOne iommu_iotlb_gather maps to one NAPOT invalidation command. The\nsmallest power-of-two aligned range covering the gather is used since\nover-invalidation is always safe.\n\nS and NL seem to be orthogonal in the spec, so if NL is not\nsupported then global invalidation is probably always going to happen\nas wiping a large range without a table change is not common.\n\nReviewed-by: Tomasz Jeznach \u003ctjeznach@rivosinc.com\u003e\nSigned-off-by: Jason Gunthorpe \u003cjgg@nvidia.com\u003e\nTested-by: Andrew Jones \u003candrew.jones@oss.qualcomm.com\u003e\nSigned-off-by: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8c60780363da720c8e54088cbf4527d4d440bc4c",
      "old_mode": 33188,
      "old_path": "drivers/iommu/riscv/iommu-bits.h",
      "new_id": "f2ef9bd3cde960a3c6c2f86032a958226dfb4c38",
      "new_mode": 33188,
      "new_path": "drivers/iommu/riscv/iommu-bits.h"
    },
    {
      "type": "modify",
      "old_id": "165ced9937562b533723e4ed2bd526b6e11ecac2",
      "old_mode": 33188,
      "old_path": "drivers/iommu/riscv/iommu.c",
      "new_id": "cec3ddd7ab1032f3ee2d66d21ef6bea3dd545d17",
      "new_mode": 33188,
      "new_path": "drivers/iommu/riscv/iommu.c"
    }
  ]
}