Merge tag 'v5.18-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt
MT8195:
- add evaluation and demo board
MT8192:
- add new nodes: pwrap, PMIC, scp, USB, efuse, IOMMU, smi, DPI, PCIe,
SPMI, audio system, MMC and video enconder
- add evaluation board
MT8183:
- fix dtschema issues
- update compatible for the display ambient light processor (disp-aal)
- fix dtschema warning for the pumpki board
MT8173:
- add power domains to the video enconder nodes
- add GCE support to the display mutex node
MT7622:
- specify number of DMA requests explicitely
- specify level 2 cache topology
- add SPI-NAND flash device
- fix dtschema warnings for the System Companion Processor (SCP)
* tag 'v5.18-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (37 commits)
arm64: dts: mt8192: Follow binding order for SCP registers
arm64: dts: mediatek: add mtk-snfi for mt7622
arm64: dts: mediatek: mt8195-demo: enable uart1
arm64: dts: mediatek: mt8195-demo: Remove input-name property
arm64: dts: mediatek: mt8183-pumpkin: fix bad thermistor node name
arm64: dts: mt7622: specify the L2 cache topology
arm64: dts: mt7622: specify the number of DMA requests
arm64: dts: mediatek: pumpkin: Remove input-name property
arm64: dts: mediatek: mt8173: Add gce-client-reg handle to disp-mutex
arm64: dts: mediatek: Add device-tree for MT8195 Demo board
dt-bindings: arm64: dts: mediatek: Add mt8195-demo board
arm64: dts: Add mediatek SoC mt8195 and evaluation board
arm64: dts: mt8192: Add mmc device nodes
arm64: dts: mt8183: Update disp_aal node compatible
arm64: dts: mt8192: Add audio-related nodes
arm64: dts: mt8192: Add spmi node
dt-bindings: arm: Add compatible for Mediatek MT8192
arm64: dts: mt6359: add PMIC MT6359 related nodes
arm64: dts: mediatek: mt8173: Add power domain to encoder nodes
arm64: dts: mediatek: Get rid of mediatek, larb for MM nodes
...
Link: https://lore.kernel.org/r/2cd90ca7-7541-d47a-fec6-b0c64cf74fa3@gmail.com
Like the 32-bit branch, this contains an incompatible binding change
by removing the mediatek,larb properties from the dts files, so these
no longer work with kernels prior to 5.18.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index ab0593c..4a2bd97 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -133,6 +133,11 @@
- const: mediatek,mt8183
- items:
- enum:
+ - mediatek,mt8192-evb
+ - const: mediatek,mt8192
+ - items:
+ - enum:
+ - mediatek,mt8195-demo
- mediatek,mt8195-evb
- const: mediatek,mt8195
- description: Google Burnet (HP Chromebook x360 11MK G3 EE)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
index 8723dfe..611f666 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
@@ -26,6 +26,7 @@
- mediatek,mt8135-pericfg
- mediatek,mt8173-pericfg
- mediatek,mt8183-pericfg
+ - mediatek,mt8195-pericfg
- mediatek,mt8516-pericfg
- const: syscon
- items:
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 8c1e180..c7d4636 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -38,4 +38,6 @@
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index a27b762..623eb3b 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -19,7 +19,7 @@ / {
#address-cells = <2>;
#size-cells = <2>;
- cluster0_opp: opp_table0 {
+ cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
@@ -36,7 +36,7 @@ opp02 {
};
};
- cluster1_opp: opp_table1 {
+ cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
@@ -329,8 +329,8 @@ iommu0: iommu@10205000 {
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
- mediatek,larbs = <&larb0 &larb1 &larb2
- &larb3 &larb6>;
+ mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+ <&larb3>, <&larb6>;
#iommu-cells = <1>;
};
@@ -346,7 +346,7 @@ iommu1: iommu@1020a000 {
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
- mediatek,larbs = <&larb4 &larb5 &larb7>;
+ mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
#iommu-cells = <1>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi
new file mode 100644
index 0000000..df3e822
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+
+&pwrap {
+ pmic: pmic {
+ compatible = "mediatek,mt6359";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ mt6359codec: mt6359codec {
+ };
+
+ regulators {
+ mt6359_vs1_buck_reg: buck_vs1 {
+ regulator-name = "vs1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+ mt6359_vgpu11_buck_reg: buck_vgpu11 {
+ regulator-name = "vgpu11";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <5000>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vmodem_buck_reg: buck_vmodem {
+ regulator-name = "vmodem";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-ramp-delay = <10760>;
+ regulator-enable-ramp-delay = <200>;
+ };
+ mt6359_vpu_buck_reg: buck_vpu {
+ regulator-name = "vpu";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <5000>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vcore_buck_reg: buck_vcore {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <5000>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vs2_buck_reg: buck_vs2 {
+ regulator-name = "vs2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1600000>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+ mt6359_vpa_buck_reg: buck_vpa {
+ regulator-name = "vpa";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3650000>;
+ regulator-enable-ramp-delay = <300>;
+ };
+ mt6359_vproc2_buck_reg: buck_vproc2 {
+ regulator-name = "vproc2";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <7500>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vproc1_buck_reg: buck_vproc1 {
+ regulator-name = "vproc1";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <7500>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vcore_sshub_buck_reg: buck_vcore_sshub {
+ regulator-name = "vcore_sshub";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ };
+ mt6359_vgpu11_sshub_buck_reg: buck_vgpu11_sshub {
+ regulator-name = "vgpu11_sshub";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ };
+ mt6359_vaud18_ldo_reg: ldo_vaud18 {
+ regulator-name = "vaud18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vsim1_ldo_reg: ldo_vsim1 {
+ regulator-name = "vsim1";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ };
+ mt6359_vibr_ldo_reg: ldo_vibr {
+ regulator-name = "vibr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ mt6359_vrf12_ldo_reg: ldo_vrf12 {
+ regulator-name = "vrf12";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ };
+ mt6359_vusb_ldo_reg: ldo_vusb {
+ regulator-name = "vusb";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <960>;
+ regulator-always-on;
+ };
+ mt6359_vsram_proc2_ldo_reg: ldo_vsram_proc2 {
+ regulator-name = "vsram_proc2";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <7500>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vio18_ldo_reg: ldo_vio18 {
+ regulator-name = "vio18";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-enable-ramp-delay = <960>;
+ regulator-always-on;
+ };
+ mt6359_vcamio_ldo_reg: ldo_vcamio {
+ regulator-name = "vcamio";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ };
+ mt6359_vcn18_ldo_reg: ldo_vcn18 {
+ regulator-name = "vcn18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vfe28_ldo_reg: ldo_vfe28 {
+ regulator-name = "vfe28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+ mt6359_vcn13_ldo_reg: ldo_vcn13 {
+ regulator-name = "vcn13";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1300000>;
+ };
+ mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt {
+ regulator-name = "vcn33_1_bt";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3500000>;
+ };
+ mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi {
+ regulator-name = "vcn33_1_wifi";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3500000>;
+ };
+ mt6359_vaux18_ldo_reg: ldo_vaux18 {
+ regulator-name = "vaux18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vsram_others_ldo_reg: ldo_vsram_others {
+ regulator-name = "vsram_others";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <5000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vefuse_ldo_reg: ldo_vefuse {
+ regulator-name = "vefuse";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <2000000>;
+ };
+ mt6359_vxo22_ldo_reg: ldo_vxo22 {
+ regulator-name = "vxo22";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-always-on;
+ };
+ mt6359_vrfck_ldo_reg: ldo_vrfck {
+ regulator-name = "vrfck";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1700000>;
+ };
+ mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 {
+ regulator-name = "vrfck";
+ regulator-min-microvolt = <1240000>;
+ regulator-max-microvolt = <1600000>;
+ };
+ mt6359_vbif28_ldo_reg: ldo_vbif28 {
+ regulator-name = "vbif28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vio28_ldo_reg: ldo_vio28 {
+ regulator-name = "vio28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ mt6359_vemc_ldo_reg: ldo_vemc {
+ regulator-name = "vemc";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ mt6359_vemc_1_ldo_reg: ldo_vemc_1 {
+ regulator-name = "vemc";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt {
+ regulator-name = "vcn33_2_bt";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3500000>;
+ };
+ mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi {
+ regulator-name = "vcn33_2_wifi";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3500000>;
+ };
+ mt6359_va12_ldo_reg: ldo_va12 {
+ regulator-name = "va12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ };
+ mt6359_va09_ldo_reg: ldo_va09 {
+ regulator-name = "va09";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ mt6359_vrf18_ldo_reg: ldo_vrf18 {
+ regulator-name = "vrf18";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1810000>;
+ };
+ mt6359_vsram_md_ldo_reg: ldo_vsram_md {
+ regulator-name = "vsram_md";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <10760>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vufs_ldo_reg: ldo_vufs {
+ regulator-name = "vufs";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ };
+ mt6359_vm18_ldo_reg: ldo_vm18 {
+ regulator-name = "vm18";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-always-on;
+ };
+ mt6359_vbbck_ldo_reg: ldo_vbbck {
+ regulator-name = "vbbck";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ mt6359_vsram_proc1_ldo_reg: ldo_vsram_proc1 {
+ regulator-name = "vsram_proc1";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <7500>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vsim2_ldo_reg: ldo_vsim2 {
+ regulator-name = "vsim2";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ };
+ mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub {
+ regulator-name = "vsram_others_sshub";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ };
+ };
+
+ mt6359rtc: mt6359rtc {
+ compatible = "mediatek,mt6358-rtc";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 6f8cb3a..9768523 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -80,6 +80,7 @@ cpu0: cpu@0 {
enable-method = "psci";
clock-frequency = <1300000000>;
cci-control-port = <&cci_control2>;
+ next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@@ -94,6 +95,12 @@ cpu1: cpu@1 {
enable-method = "psci";
clock-frequency = <1300000000>;
cci-control-port = <&cci_control2>;
+ next-level-cache = <&L2>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
};
};
@@ -545,6 +552,18 @@ nandc: nfi@1100d000 {
status = "disabled";
};
+ snfi: spi@1100d000 {
+ compatible = "mediatek,mt7622-snand";
+ reg = <0 0x1100d000 0 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "pad_clk";
+ nand-ecc-engine = <&bch>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
bch: ecc@1100e000 {
compatible = "mediatek,mt7622-ecc";
reg = <0 0x1100e000 0 0x1000>;
@@ -917,6 +936,7 @@ hsdma: dma-controller@1b007000 {
clock-names = "hsdma";
power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
#dma-cells = <1>;
+ dma-requests = <3>;
};
eth: ethernet@1b100000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 9029051..54655f2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -174,7 +174,7 @@ larb2: larb@16010000 {
iommu: m4u@10203000 {
compatible = "mediatek,mt8167-m4u";
reg = <0 0x10203000 0 0x1000>;
- mediatek,larbs = <&larb0 &larb1 &larb2>;
+ mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
#iommu-cells = <1>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 2b7d331..40d7b47 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -57,7 +57,7 @@ aliases {
serial3 = &uart3;
};
- cluster0_opp: opp_table0 {
+ cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-507000000 {
@@ -94,7 +94,7 @@ opp-1703000000 {
};
};
- cluster1_opp: opp_table1 {
+ cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
opp-507000000 {
@@ -273,7 +273,7 @@ cpum_ck: oscillator2 {
};
thermal-zones {
- cpu_thermal: cpu_thermal {
+ cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
@@ -588,8 +588,8 @@ iommu: iommu@10205000 {
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
- mediatek,larbs = <&larb0 &larb1 &larb2
- &larb3 &larb4 &larb5>;
+ mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+ <&larb3>, <&larb4>, <&larb5>;
#iommu-cells = <1>;
};
@@ -1010,7 +1010,6 @@ mdp_rdma0: rdma@14001000 {
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
- mediatek,larb = <&larb0>;
mediatek,vpu = <&vpu>;
};
@@ -1021,7 +1020,6 @@ mdp_rdma1: rdma@14002000 {
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA1>;
- mediatek,larb = <&larb4>;
};
mdp_rsz0: rsz@14003000 {
@@ -1051,7 +1049,6 @@ mdp_wdma0: wdma@14006000 {
clocks = <&mmsys CLK_MM_MDP_WDMA>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WDMA>;
- mediatek,larb = <&larb0>;
};
mdp_wrot0: wrot@14007000 {
@@ -1060,7 +1057,6 @@ mdp_wrot0: wrot@14007000 {
clocks = <&mmsys CLK_MM_MDP_WROT0>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
- mediatek,larb = <&larb0>;
};
mdp_wrot1: wrot@14008000 {
@@ -1069,7 +1065,6 @@ mdp_wrot1: wrot@14008000 {
clocks = <&mmsys CLK_MM_MDP_WROT1>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT1>;
- mediatek,larb = <&larb4>;
};
ovl0: ovl@1400c000 {
@@ -1079,7 +1074,6 @@ ovl0: ovl@1400c000 {
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
@@ -1090,7 +1084,6 @@ ovl1: ovl@1400d000 {
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL1>;
iommus = <&iommu M4U_PORT_DISP_OVL1>;
- mediatek,larb = <&larb4>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
};
@@ -1101,7 +1094,6 @@ rdma0: rdma@1400e000 {
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
@@ -1112,7 +1104,6 @@ rdma1: rdma@1400f000 {
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb4>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
};
@@ -1123,7 +1114,6 @@ rdma2: rdma@14010000 {
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
- mediatek,larb = <&larb4>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
};
@@ -1134,7 +1124,6 @@ wdma0: wdma@14011000 {
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
};
@@ -1145,7 +1134,6 @@ wdma1: wdma@14012000 {
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
- mediatek,larb = <&larb4>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
};
@@ -1290,6 +1278,7 @@ mutex: mutex@14020000 {
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_MUTEX_32K>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
};
@@ -1399,7 +1388,6 @@ vcodec_dec: vcodec@16000000 {
<0 0x16027800 0 0x800>, /* VDEC_HWB */
<0 0x16028400 0 0x400>; /* VDEC_HWG */
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb1>;
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
@@ -1467,7 +1455,6 @@ vcodec_enc_avc: vcodec@18002000 {
compatible = "mediatek,mt8173-vcodec-enc";
reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
@@ -1484,6 +1471,7 @@ vcodec_enc_avc: vcodec@18002000 {
clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
};
jpegdec: jpegdec@18004000 {
@@ -1495,7 +1483,6 @@ jpegdec: jpegdec@18004000 {
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
- mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
<&iommu M4U_PORT_JPGDEC_BSDMA>;
};
@@ -1529,13 +1516,13 @@ vcodec_enc_vp8: vcodec@19002000 {
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
- mediatek,larb = <&larb5>;
mediatek,vpu = <&vpu>;
clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "venc_lt_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents =
<&topckgen CLK_TOP_VCODECPLL_370P5>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
};
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
index 8f7bf33f..2d7a193 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
@@ -92,7 +92,7 @@ volume_up {
};
&cros_ec {
- cros_ec_pwm: ec-pwm {
+ cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
index 0f9480f..8d5bf73 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
@@ -849,7 +849,7 @@ &spi1 {
mediatek,pad-select = <0>;
status = "okay";
- w25q64dw: spi-flash@0 {
+ w25q64dw: flash@0 {
compatible = "winbond,w25q64dw", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
index ee91282..afeb5cd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
@@ -55,7 +55,7 @@ led-green {
};
};
- ntc {
+ thermistor {
compatible = "murata,ncp03wf104";
pullup-uv = <1800000>;
pullup-ohm = <390000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 4b08691e..01e6502 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -197,7 +197,7 @@ CLUSTER_SLEEP1: cluster-sleep-1 {
};
};
- gpu_opp_table: opp_table0 {
+ gpu_opp_table: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -682,8 +682,8 @@ iommu: iommu@10205000 {
compatible = "mediatek,mt8183-m4u";
reg = <0 0x10205000 0 0x1000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larbs = <&larb0 &larb1 &larb2 &larb3
- &larb4 &larb5 &larb6>;
+ mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>,
+ <&larb4>, <&larb5>, <&larb6>;
#iommu-cells = <1>;
};
@@ -823,7 +823,7 @@ thermal: thermal@1100b000 {
};
thermal_zones: thermal-zones {
- cpu_thermal: cpu_thermal {
+ cpu_thermal: cpu-thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
thermal-sensors = <&thermal 0>;
@@ -1396,7 +1396,6 @@ ovl0: ovl@14008000 {
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
};
@@ -1407,7 +1406,6 @@ ovl_2l0: ovl@14009000 {
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
};
@@ -1418,7 +1416,6 @@ ovl_2l1: ovl@1400a000 {
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
};
@@ -1429,7 +1426,6 @@ rdma0: rdma@1400b000 {
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
mediatek,rdma-fifo-size = <5120>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
};
@@ -1441,7 +1437,6 @@ rdma1: rdma@1400c000 {
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb0>;
mediatek,rdma-fifo-size = <2048>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
@@ -1466,8 +1461,7 @@ ccorr0: ccorr@1400f000 {
};
aal0: aal@14010000 {
- compatible = "mediatek,mt8183-disp-aal",
- "mediatek,mt8173-disp-aal";
+ compatible = "mediatek,mt8183-disp-aal";
reg = <0 0x14010000 0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
@@ -1598,7 +1592,6 @@ venc_jpg: venc_jpg@17030000 {
compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
reg = <0 0x17030000 0 0x1000>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb4>;
iommus = <&iommu M4U_PORT_JPGENC_RDMA>,
<&iommu M4U_PORT_JPGENC_BSDMA>;
power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 0205837..808be49 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
#include "mt8192.dtsi"
+#include "mt6359.dtsi"
/ {
model = "MediaTek MT8192 evaluation board";
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 411feb2..733aec2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -8,7 +8,9 @@
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8192-larb-port.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
/ {
@@ -523,6 +525,33 @@ systimer: timer@10017000 {
clock-names = "clk13m";
};
+ pwrap: pwrap@10026000 {
+ compatible = "mediatek,mt6873-pwrap";
+ reg = <0 0x10026000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+ <&infracfg CLK_INFRA_PMIC_TMR>;
+ clock-names = "spi", "wrap";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ };
+
+ spmi: spmi@10027000 {
+ compatible = "mediatek,mt6873-spmi";
+ reg = <0 0x10027000 0 0x000e00>,
+ <0 0x10029000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&infracfg CLK_INFRA_PMIC_AP>,
+ <&infracfg CLK_INFRA_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_MST_SEL>;
+ clock-names = "pmif_sys_ck",
+ "pmif_tmr_ck",
+ "spmimst_clk_mux";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
@@ -667,6 +696,205 @@ spi7: spi@1101e000 {
status = "disabled";
};
+ scp: scp@10500000 {
+ compatible = "mediatek,mt8192-scp";
+ reg = <0 0x10500000 0 0x100000>,
+ <0 0x10720000 0 0xe0000>,
+ <0 0x10700000 0 0x8000>;
+ reg-names = "sram", "cfg", "l1tcm";
+ interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_SCPSYS>;
+ clock-names = "main";
+ status = "disabled";
+ };
+
+ xhci: usb@11200000 {
+ compatible = "mediatek,mt8192-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "host";
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&infracfg CLK_INFRA_SSUSB>,
+ <&infracfg CLK_INFRA_SSUSB_XHCI>,
+ <&apmixedsys CLK_APMIXED_USBPLL>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x420 102>;
+ status = "disabled";
+ };
+
+ audsys: syscon@11210000 {
+ compatible = "mediatek,mt8192-audsys", "syscon";
+ reg = <0 0x11210000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: mt8192-afe-pcm {
+ compatible = "mediatek,mt8192-audio";
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&watchdog 17>;
+ reset-names = "audiosys";
+ mediatek,apmixedsys = <&apmixedsys>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,topckgen = <&topckgen>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_DAC>,
+ <&audsys CLK_AUD_DAC_PREDIS>,
+ <&audsys CLK_AUD_ADC>,
+ <&audsys CLK_AUD_ADDA6_ADC>,
+ <&audsys CLK_AUD_22M>,
+ <&audsys CLK_AUD_24M>,
+ <&audsys CLK_AUD_APLL_TUNER>,
+ <&audsys CLK_AUD_APLL2_TUNER>,
+ <&audsys CLK_AUD_TDM>,
+ <&audsys CLK_AUD_TML>,
+ <&audsys CLK_AUD_NLE>,
+ <&audsys CLK_AUD_DAC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES>,
+ <&audsys CLK_AUD_ADC_HIRES_TML>,
+ <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+ <&audsys CLK_AUD_3RD_DAC>,
+ <&audsys CLK_AUD_3RD_DAC_PREDIS>,
+ <&audsys CLK_AUD_3RD_DAC_TML>,
+ <&audsys CLK_AUD_3RD_DAC_HIRES>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&topckgen CLK_TOP_AUDIO_SEL>,
+ <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+ <&topckgen CLK_TOP_AUD_1_SEL>,
+ <&topckgen CLK_TOP_APLL1>,
+ <&topckgen CLK_TOP_AUD_2_SEL>,
+ <&topckgen CLK_TOP_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
+ <&topckgen CLK_TOP_APLL1_D4>,
+ <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV4>,
+ <&topckgen CLK_TOP_APLL12_DIVB>,
+ <&topckgen CLK_TOP_APLL12_DIV5>,
+ <&topckgen CLK_TOP_APLL12_DIV6>,
+ <&topckgen CLK_TOP_APLL12_DIV7>,
+ <&topckgen CLK_TOP_APLL12_DIV8>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_AUDIO_H_SEL>,
+ <&clk26m>;
+ clock-names = "aud_afe_clk",
+ "aud_dac_clk",
+ "aud_dac_predis_clk",
+ "aud_adc_clk",
+ "aud_adda6_adc_clk",
+ "aud_apll22m_clk",
+ "aud_apll24m_clk",
+ "aud_apll1_tuner_clk",
+ "aud_apll2_tuner_clk",
+ "aud_tdm_clk",
+ "aud_tml_clk",
+ "aud_nle",
+ "aud_dac_hires_clk",
+ "aud_adc_hires_clk",
+ "aud_adc_hires_tml",
+ "aud_adda6_adc_hires_clk",
+ "aud_3rd_dac_clk",
+ "aud_3rd_dac_predis_clk",
+ "aud_3rd_dac_tml",
+ "aud_3rd_dac_hires_clk",
+ "aud_infra_clk",
+ "aud_infra_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d4_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d4",
+ "top_mux_aud_eng2",
+ "top_apll2_d4",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s3_m_sel",
+ "top_i2s4_m_sel",
+ "top_i2s5_m_sel",
+ "top_i2s6_m_sel",
+ "top_i2s7_m_sel",
+ "top_i2s8_m_sel",
+ "top_i2s9_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div3",
+ "top_apll12_div4",
+ "top_apll12_divb",
+ "top_apll12_div5",
+ "top_apll12_div6",
+ "top_apll12_div7",
+ "top_apll12_div8",
+ "top_apll12_div9",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ };
+ };
+
+ pcie: pcie@11230000 {
+ compatible = "mediatek,mt8192-pcie";
+ device_type = "pci";
+ reg = <0 0x11230000 0 0x2000>;
+ reg-names = "pcie-mac";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>,
+ <&infracfg CLK_INFRA_PCIE_TL_26M>,
+ <&infracfg CLK_INFRA_PCIE_TL_96M>,
+ <&infracfg CLK_INFRA_PCIE_TL_32K>,
+ <&infracfg CLK_INFRA_PCIE_PERI_26M>,
+ <&infracfg CLK_INFRA_PCIE_TOP_H_133M>;
+ clock-names = "pl_250m", "tl_26m", "tl_96m",
+ "tl_32k", "peri_26m", "top_133m";
+ assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
+ interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
+ <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
@@ -679,13 +907,22 @@ nor_flash: spi@11234000 {
assigned-clock-parents = <&clk26m>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disable";
+ status = "disabled";
};
- audsys: clock-controller@11210000 {
- compatible = "mediatek,mt8192-audsys", "syscon";
- reg = <0 0x11210000 0 0x1000>;
- #clock-cells = <1>;
+ efuse: efuse@11c10000 {
+ compatible = "mediatek,efuse";
+ reg = <0 0x11c10000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ lvts_e_data1: data1@1c0 {
+ reg = <0x1c0 0x58>;
+ };
+
+ svs_calibration: calib@580 {
+ reg = <0x580 0x68>;
+ };
};
i2c3: i2c@11cb0000 {
@@ -824,6 +1061,28 @@ imp_iic_wrap_w: clock-controller@11e01000 {
#clock-cells = <1>;
};
+ u3phy0: t-phy@11e40000 {
+ compatible = "mediatek,mt8192-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x11e40000 0x1000>;
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x900>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
i2c0: i2c@11f00000 {
compatible = "mediatek,mt8192-i2c";
reg = <0 0x11f00000 0 0x1000>,
@@ -864,10 +1123,36 @@ msdc_top: clock-controller@11f10000 {
#clock-cells = <1>;
};
- msdc: clock-controller@11f60000 {
- compatible = "mediatek,mt8192-msdc";
- reg = <0 0x11f60000 0 0x1000>;
- #clock-cells = <1>;
+ mmc0: mmc@11f60000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_0P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11f70000 {
+ compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
+ <&msdc_top CLK_MSDC_TOP_SRC_1P>,
+ <&msdc_top CLK_MSDC_TOP_P_CFG>,
+ <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
+ <&msdc_top CLK_MSDC_TOP_AXI>,
+ <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
+ clock-names = "source", "hclk", "source_cg", "sys_cg",
+ "pclk_cg", "axi_cg", "ahb_cg";
+ status = "disabled";
};
mfgcfg: clock-controller@13fbf000 {
@@ -882,24 +1167,125 @@ mmsys: syscon@14000000 {
#clock-cells = <1>;
};
+ smi_common: smi@14002000 {
+ compatible = "mediatek,mt8192-smi-common";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_INFRA>,
+ <&mmsys CLK_MM_SMI_GALS>,
+ <&mmsys CLK_MM_SMI_GALS>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ larb0: larb@14003000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,larb-id = <0>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ larb1: larb@14004000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,larb-id = <1>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ dpi0: dpi@14016000 {
+ compatible = "mediatek,mt8192-dpi";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_DPI_DPI0>,
+ <&mmsys CLK_MM_DISP_DPI0>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+ status = "disabled";
+ };
+
+ iommu0: m4u@1401d000 {
+ compatible = "mediatek,mt8192-m4u";
+ reg = <0 0x1401d000 0 0x1000>;
+ mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+ <&larb4>, <&larb5>, <&larb7>,
+ <&larb9>, <&larb11>, <&larb13>,
+ <&larb14>, <&larb16>, <&larb17>,
+ <&larb18>, <&larb19>, <&larb20>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_SMI_IOMMU>;
+ clock-names = "bclk";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ #iommu-cells = <1>;
+ };
+
imgsys: clock-controller@15020000 {
compatible = "mediatek,mt8192-imgsys";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
+ larb9: larb@1502e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1502e000 0 0x1000>;
+ mediatek,larb-id = <9>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_LARB9>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
+ };
+
imgsys2: clock-controller@15820000 {
compatible = "mediatek,mt8192-imgsys2";
reg = <0 0x15820000 0 0x1000>;
#clock-cells = <1>;
};
+ larb11: larb@1582e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1582e000 0 0x1000>;
+ mediatek,larb-id = <11>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys2 CLK_IMG2_LARB11>,
+ <&imgsys2 CLK_IMG2_LARB11>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
+ };
+
+ larb5: larb@1600d000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1600d000 0 0x1000>;
+ mediatek,larb-id = <5>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
vdecsys_soc: clock-controller@1600f000 {
compatible = "mediatek,mt8192-vdecsys_soc";
reg = <0 0x1600f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb4: larb@1602e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1602e000 0 0x1000>;
+ mediatek,larb-id = <4>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
+ <&vdecsys CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+
vdecsys: clock-controller@1602f000 {
compatible = "mediatek,mt8192-vdecsys";
reg = <0 0x1602f000 0 0x1000>;
@@ -912,12 +1298,101 @@ vencsys: clock-controller@17000000 {
#clock-cells = <1>;
};
+ larb7: larb@17010000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x17010000 0 0x1000>;
+ mediatek,larb-id = <7>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vencsys CLK_VENC_SET0_LARB>,
+ <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+ };
+
+ vcodec_enc: vcodec@17020000 {
+ compatible = "mediatek,mt8192-vcodec-enc";
+ reg = <0 0x17020000 0 0x2000>;
+ iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
+ <&iommu0 M4U_PORT_L7_VENC_REC>,
+ <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
+ <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
+ <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
+ <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
+ <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,scp = <&scp>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+ clocks = <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "venc-set1";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+ };
+
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8192-camsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb13: larb@1a001000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a001000 0 0x1000>;
+ mediatek,larb-id = <13>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_LARB13>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+ };
+
+ larb14: larb@1a002000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a002000 0 0x1000>;
+ mediatek,larb-id = <14>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_LARB14>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+ };
+
+ larb16: larb@1a00f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a00f000 0 0x1000>;
+ mediatek,larb-id = <16>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
+ };
+
+ larb17: larb@1a010000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a010000 0 0x1000>;
+ mediatek,larb-id = <17>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
+ <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
+ };
+
+ larb18: larb@1a011000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a011000 0 0x1000>;
+ mediatek,larb-id = <18>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
+ <&camsys_rawc CLK_CAM_RAWC_CAM>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
+ };
+
camsys_rawa: clock-controller@1a04f000 {
compatible = "mediatek,mt8192-camsys_rawa";
reg = <0 0x1a04f000 0 0x1000>;
@@ -942,10 +1417,43 @@ ipesys: clock-controller@1b000000 {
#clock-cells = <1>;
};
+ larb20: larb@1b00f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1b00f000 0 0x1000>;
+ mediatek,larb-id = <20>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_LARB20>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+ };
+
+ larb19: larb@1b10f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1b10f000 0 0x1000>;
+ mediatek,larb-id = <19>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_LARB19>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+ };
+
mdpsys: clock-controller@1f000000 {
compatible = "mediatek,mt8192-mdpsys";
reg = <0 0x1f000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ larb2: larb@1f002000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1f002000 0 0x1000>;
+ mediatek,larb-id = <2>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mdpsys CLK_MDP_SMI0>,
+ <&mdpsys CLK_MDP_SMI0>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
new file mode 100644
index 0000000..4fbd99e
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
@@ -0,0 +1,450 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 BayLibre, SAS.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+/dts-v1/;
+
+#include "mt8195.dtsi"
+#include "mt6359.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
+#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
+
+/ {
+ model = "MediaTek MT8195 demo board";
+ compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pins>;
+
+ key-0 {
+ gpios = <&pio 106 GPIO_ACTIVE_LOW>;
+ label = "volume_up";
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@54600000 {
+ no-map;
+ reg = <0 0x54600000 0x0 0x30000>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+ };
+};
+
+&i2c6 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&i2c6_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mt6360: pmic@34 {
+ compatible = "mediatek,mt6360";
+ reg = <0x34>;
+ interrupt-controller;
+ interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "IRQB";
+
+ charger {
+ compatible = "mediatek,mt6360-chg";
+ richtek,vinovp-microvolt = <14500000>;
+
+ otg_vbus_regulator: usb-otg-vbus-regulator {
+ regulator-compatible = "usb-otg-vbus";
+ regulator-name = "usb-otg-vbus";
+ regulator-min-microvolt = <4425000>;
+ regulator-max-microvolt = <5825000>;
+ };
+ };
+
+ regulator {
+ compatible = "mediatek,mt6360-regulator";
+ LDO_VIN3-supply = <&mt6360_buck2>;
+
+ mt6360_buck1: buck1 {
+ regulator-compatible = "BUCK1";
+ regulator-name = "mt6360,buck1";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP
+ MT6360_OPMODE_ULP>;
+ regulator-always-on;
+ };
+
+ mt6360_buck2: buck2 {
+ regulator-compatible = "BUCK2";
+ regulator-name = "mt6360,buck2";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP
+ MT6360_OPMODE_ULP>;
+ regulator-always-on;
+ };
+
+ mt6360_ldo1: ldo1 {
+ regulator-compatible = "LDO1";
+ regulator-name = "mt6360,ldo1";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo2: ldo2 {
+ regulator-compatible = "LDO2";
+ regulator-name = "mt6360,ldo2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo3: ldo3 {
+ regulator-compatible = "LDO3";
+ regulator-name = "mt6360,ldo3";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo5: ldo5 {
+ regulator-compatible = "LDO5";
+ regulator-name = "mt6360,ldo5";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo6: ldo6 {
+ regulator-compatible = "LDO6";
+ regulator-name = "mt6360,ldo6";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2100000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ };
+
+ mt6360_ldo7: ldo7 {
+ regulator-compatible = "LDO7";
+ regulator-name = "mt6360,ldo7";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <2100000>;
+ regulator-allowed-modes = <MT6360_OPMODE_NORMAL
+ MT6360_OPMODE_LP>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&mmc0 {
+ status = "okay";
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_default_pins>;
+ pinctrl-1 = <&mmc0_uhs_pins>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cap-mmc-hw-reset;
+ no-sdio;
+ no-sd;
+ hs400-ds-delay = <0x14c11>;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ non-removable;
+};
+
+&mmc1 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc1_default_pins>;
+ pinctrl-1 = <&mmc1_uhs_pins>;
+ cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&mt6360_ldo5>;
+ vqmmc-supply = <&mt6360_ldo3>;
+ status = "okay";
+};
+
+&mt6359_vbbck_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vcore_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vgpu11_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vproc1_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vproc2_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vpu_buck_reg {
+ regulator-always-on;
+};
+
+&mt6359_vrf12_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vsram_md_ldo_reg {
+ regulator-always-on;
+};
+
+&mt6359_vsram_others_ldo_reg {
+ regulator-always-on;
+};
+
+&pio {
+ gpio_keys_pins: gpio-keys-pins {
+ pins {
+ pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
+ input-enable;
+ };
+ };
+
+ i2c6_pins: i2c6-pins {
+ pins {
+ pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
+ <PINMUX_GPIO26__FUNC_SCL6>;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_default_pins: mmc0-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
+ drive-strength = <MTK_DRIVE_6mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_6mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
+ drive-strength = <MTK_DRIVE_6mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc0_uhs_pins: mmc0-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-ds {
+ pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_default_pins: mmc1-default-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
+ <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-insert {
+ pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_uhs_pins: mmc1-uhs-pins {
+ pins-clk {
+ pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
+ <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
+ <PINMUX_GPIO99__FUNC_URXD0>;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ pins {
+ pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
+ <PINMUX_GPIO103__FUNC_URXD1>;
+ };
+ };
+};
+
+
+&pmic {
+ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
+&u3phy0 {
+ status = "okay";
+};
+
+&u3phy1 {
+ status = "okay";
+};
+
+&u3phy2 {
+ status = "okay";
+};
+
+&u3phy3 {
+ status = "okay";
+};
+
+&xhci0 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ vbus-supply = <&otg_vbus_regulator>;
+ status = "okay";
+};
+
+&xhci1 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&xhci2 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
+&xhci3 {
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
new file mode 100644
index 0000000..db25a51
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Seiya Wang <seiya.wang@mediatek.com>
+ */
+/dts-v1/;
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 evaluation board";
+ compatible = "mediatek,mt8195-evb", "mediatek,mt8195";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+};
+
+&auxadc {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pin>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pin>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pin>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pin>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&nor_flash {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nor_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&pio {
+ i2c0_pin: i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
+ <PINMUX_GPIO9__FUNC_SCL0>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ mediatek,drive-strength-adv = <0>;
+ drive-strength = <6>;
+ };
+ };
+
+ i2c1_pin: i2c1-pins {
+ pins {
+ pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
+ <PINMUX_GPIO11__FUNC_SCL1>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ mediatek,drive-strength-adv = <0>;
+ drive-strength = <6>;
+ };
+ };
+
+ i2c4_pin: i2c4-pins {
+ pins {
+ pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
+ <PINMUX_GPIO17__FUNC_SCL4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ mediatek,drive-strength-adv = <7>;
+ };
+ };
+
+ i2c6_pin: i2c6-pins {
+ pins {
+ pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
+ <PINMUX_GPIO26__FUNC_SCL6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ i2c7_pin: i2c7-pins {
+ pins {
+ pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
+ <PINMUX_GPIO28__FUNC_SDA7>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ nor_pins_default: nor-pins {
+ pins0 {
+ pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
+ <PINMUX_GPIO141__FUNC_SPINOR_CK>,
+ <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
+ bias-pull-down;
+ };
+
+ pins1 {
+ pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>,
+ <PINMUX_GPIO130__FUNC_SPINOR_IO2>,
+ <PINMUX_GPIO131__FUNC_SPINOR_IO3>;
+ bias-pull-up;
+ };
+ };
+
+ uart0_pin: uart0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
+ <PINMUX_GPIO99__FUNC_URXD0>;
+ };
+ };
+};
+
+&u3phy0 {
+ status="okay";
+};
+
+&u3phy1 {
+ status="okay";
+};
+
+&u3phy2 {
+ status="okay";
+};
+
+&u3phy3 {
+ status="okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pin>;
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci1 {
+ status = "okay";
+};
+
+&xhci2 {
+ status = "okay";
+};
+
+&xhci3 {
+ /* This controller is connected with a BT device.
+ * Disable usb2 lpm to prevent known issues.
+ */
+ usb2-lpm-disable;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
new file mode 100644
index 0000000..b57e620
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -0,0 +1,1045 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Seiya Wang <seiya.wang@mediatek.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
+#include <dt-bindings/reset/ti-syscon.h>
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x000>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x400>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x500>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x600>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x700>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+
+ core1 {
+ cpu = <&cpu5>;
+ };
+
+ core2 {
+ cpu = <&cpu6>;
+ };
+
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_off_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <95>;
+ min-residency-us = <580>;
+ };
+
+ cpu_off_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <45>;
+ exit-latency-us = <140>;
+ min-residency-us = <740>;
+ };
+
+ cluster_off_l: cluster-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <55>;
+ exit-latency-us = <155>;
+ min-residency-us = <840>;
+ };
+
+ cluster_off_b: cluster-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <200>;
+ min-residency-us = <1000>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+
+ dsu-pmu {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
+ cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
+ <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ clk26m: oscillator-26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "clk32k";
+ };
+
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+ };
+
+ pmu-a78 {
+ compatible = "arm,cortex-a78-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>,
+ <0 0x0c040000 0 0x200000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8195-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg_ao: syscon@10001000 {
+ compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+
+ infracfg_rst: reset-controller {
+ compatible = "ti,syscon-reset";
+ #reset-cells = <1>;
+ ti,reset-bits = <
+ 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
+ 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
+ 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
+ 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
+ >;
+ };
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8195-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt8195-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11d10000 0 0x1000>,
+ <0 0x11d30000 0 0x1000>,
+ <0 0x11d40000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11eb0000 0 0x1000>,
+ <0 0x11f40000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
+ "iocfg_br", "iocfg_lm", "iocfg_rb",
+ "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 144>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
+ #interrupt-cells = <2>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8195-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8195-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ systimer: timer@10017000 {
+ compatible = "mediatek,mt8195-timer",
+ "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x1000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_CLK26M_D2>;
+ };
+
+ pwrap: pwrap@10024000 {
+ compatible = "mediatek,mt8195-pwrap", "syscon";
+ reg = <0 0x10024000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
+ clock-names = "spi", "wrap";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+ };
+
+ scp_adsp: clock-controller@10720000 {
+ compatible = "mediatek,mt8195-scp_adsp";
+ reg = <0 0x10720000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@11001100 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001100 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11001200 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001200 0 0x100>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11001300 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001300 0 0x100>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial@11001400 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001400 0 0x100>;
+ interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart4: serial@11001500 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001500 0 0x100>;
+ interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart5: serial@11001600 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001600 0 0x100>;
+ interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ auxadc: auxadc@11002000 {
+ compatible = "mediatek,mt8195-auxadc",
+ "mediatek,mt8173-auxadc";
+ reg = <0 0x11002000 0 0x1000>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ pericfg_ao: syscon@11003000 {
+ compatible = "mediatek,mt8195-pericfg_ao", "syscon";
+ reg = <0 0x11003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ spi0: spi@1100a000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi1: spi@11010000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11010000 0 0x1000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi2: spi@11012000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11012000 0 0x1000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi3: spi@11013000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11013000 0 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI3>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi4: spi@11018000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI4>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi5: spi@11019000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11019000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI5>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spis0: spi@1101d000 {
+ compatible = "mediatek,mt8195-spi-slave";
+ reg = <0 0x1101d000 0 0x1000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
+ clock-names = "spi";
+ assigned-clocks = <&topckgen CLK_TOP_SPIS>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+ status = "disabled";
+ };
+
+ spis1: spi@1101e000 {
+ compatible = "mediatek,mt8195-spi-slave";
+ reg = <0 0x1101e000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
+ clock-names = "spi";
+ assigned-clocks = <&topckgen CLK_TOP_SPIS>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+ status = "disabled";
+ };
+
+ xhci0: usb@11200000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&topckgen CLK_TOP_SSUSB_XHCI>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
+ <&topckgen CLK_TOP_SSUSB_REF>,
+ <&apmixedsys CLK_APMIXED_USB1PLL>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x10000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC1>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@11250000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11250000 0 0x1000>,
+ <0 0x11e60000 0 0x1000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_2>,
+ <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
+ <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
+ clock-names = "source", "hclk", "source_cg";
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ status = "disabled";
+ };
+
+ xhci1: usb@11290000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11290000 0 0x1000>,
+ <0 0x11293e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port1 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P1_REF>,
+ <&apmixedsys CLK_APMIXED_USB1PLL>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck";
+ status = "disabled";
+ };
+
+ xhci2: usb@112a0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112a0000 0 0x1000>,
+ <0 0x112a3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P2_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ status = "disabled";
+ };
+
+ xhci3: usb@112b0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112b0000 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port3 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P3_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ status = "disabled";
+ };
+
+ nor_flash: spi@1132c000 {
+ compatible = "mediatek,mt8195-nor",
+ "mediatek,mt8173-nor";
+ reg = <0 0x1132c000 0 0x1000>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_SPINOR>,
+ <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
+ <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
+ clock-names = "spi", "sf", "axi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ u3phy2: t-phy@11c40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c40000 0x700>;
+ status = "disabled";
+
+ u2port2: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy3: t-phy@11c50000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c50000 0x700>;
+ status = "disabled";
+
+ u2port3: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ i2c5: i2c@11d00000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d00000 0 0x1000>,
+ <0 0x10220580 0 0x80>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@11d01000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d01000 0 0x1000>,
+ <0 0x10220600 0 0x80>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@11d02000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d02000 0 0x1000>,
+ <0 0x10220680 0 0x80>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ imp_iic_wrap_s: clock-controller@11d03000 {
+ compatible = "mediatek,mt8195-imp_iic_wrap_s";
+ reg = <0 0x11d03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ i2c0: i2c@11e00000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e00000 0 0x1000>,
+ <0 0x10220080 0 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ };
+
+ i2c1: i2c@11e01000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e01000 0 0x1000>,
+ <0 0x10220200 0 0x80>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11e02000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e02000 0 0x1000>,
+ <0 0x10220380 0 0x80>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@11e03000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e03000 0 0x1000>,
+ <0 0x10220480 0 0x80>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@11e04000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e04000 0 0x1000>,
+ <0 0x10220500 0 0x80>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ imp_iic_wrap_w: clock-controller@11e05000 {
+ compatible = "mediatek,mt8195-imp_iic_wrap_w";
+ reg = <0 0x11e05000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ u3phy1: t-phy@11e30000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e30000 0xe00>;
+ status = "disabled";
+
+ u2port1: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u3port1: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
+ <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy0: t-phy@11e40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e40000 0xe00>;
+ status = "disabled";
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
+ <&topckgen CLK_TOP_SSUSB_PHY_REF>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ ufsphy: ufs-phy@11fa0000 {
+ compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
+ reg = <0 0x11fa0000 0 0xc000>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "unipro", "mp";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mfgcfg: clock-controller@13fbf000 {
+ compatible = "mediatek,mt8195-mfgcfg";
+ reg = <0 0x13fbf000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys: clock-controller@14e00000 {
+ compatible = "mediatek,mt8195-wpesys";
+ reg = <0 0x14e00000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys_vpp0: clock-controller@14e02000 {
+ compatible = "mediatek,mt8195-wpesys_vpp0";
+ reg = <0 0x14e02000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys_vpp1: clock-controller@14e03000 {
+ compatible = "mediatek,mt8195-wpesys_vpp1";
+ reg = <0 0x14e03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: clock-controller@15000000 {
+ compatible = "mediatek,mt8195-imgsys";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_dip_top: clock-controller@15110000 {
+ compatible = "mediatek,mt8195-imgsys1_dip_top";
+ reg = <0 0x15110000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_dip_nr: clock-controller@15130000 {
+ compatible = "mediatek,mt8195-imgsys1_dip_nr";
+ reg = <0 0x15130000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_wpe: clock-controller@15220000 {
+ compatible = "mediatek,mt8195-imgsys1_wpe";
+ reg = <0 0x15220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipesys: clock-controller@15330000 {
+ compatible = "mediatek,mt8195-ipesys";
+ reg = <0 0x15330000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: clock-controller@16000000 {
+ compatible = "mediatek,mt8195-camsys";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawa: clock-controller@1604f000 {
+ compatible = "mediatek,mt8195-camsys_rawa";
+ reg = <0 0x1604f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_yuva: clock-controller@1606f000 {
+ compatible = "mediatek,mt8195-camsys_yuva";
+ reg = <0 0x1606f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawb: clock-controller@1608f000 {
+ compatible = "mediatek,mt8195-camsys_rawb";
+ reg = <0 0x1608f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_yuvb: clock-controller@160af000 {
+ compatible = "mediatek,mt8195-camsys_yuvb";
+ reg = <0 0x160af000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_mraw: clock-controller@16140000 {
+ compatible = "mediatek,mt8195-camsys_mraw";
+ reg = <0 0x16140000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ccusys: clock-controller@17200000 {
+ compatible = "mediatek,mt8195-ccusys";
+ reg = <0 0x17200000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_soc: clock-controller@1800f000 {
+ compatible = "mediatek,mt8195-vdecsys_soc";
+ reg = <0 0x1800f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: clock-controller@1802f000 {
+ compatible = "mediatek,mt8195-vdecsys";
+ reg = <0 0x1802f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_core1: clock-controller@1803f000 {
+ compatible = "mediatek,mt8195-vdecsys_core1";
+ reg = <0 0x1803f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apusys_pll: clock-controller@190f3000 {
+ compatible = "mediatek,mt8195-apusys_pll";
+ reg = <0 0x190f3000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: clock-controller@1a000000 {
+ compatible = "mediatek,mt8195-vencsys";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys_core1: clock-controller@1b000000 {
+ compatible = "mediatek,mt8195-vencsys_core1";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
index fcddec1..7a717f9 100644
--- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
@@ -25,7 +25,6 @@ optee: optee@4fd00000 {
gpio-keys {
compatible = "gpio-keys";
- input-name = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_default>;
diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h
index be9a7ca..764ca99 100644
--- a/include/dt-bindings/reset/mt8192-resets.h
+++ b/include/dt-bindings/reset/mt8192-resets.h
@@ -27,4 +27,7 @@
#define MT8192_TOPRGU_SW_RST_NUM 23
+/* MMSYS resets */
+#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
