| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Device Tree Source for J721E SoC Family Main Domain peripherals |
| * |
| * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| #include <dt-bindings/phy/phy.h> |
| #include <dt-bindings/mux/mux.h> |
| #include <dt-bindings/mux/mux-j721e-wiz.h> |
| |
| &cbass_main { |
| msmc_ram: sram@70000000 { |
| compatible = "mmio-sram"; |
| reg = <0x0 0x70000000 0x0 0x800000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x70000000 0x800000>; |
| |
| atf-sram@0 { |
| reg = <0x0 0x20000>; |
| }; |
| }; |
| |
| scm_conf: scm-conf@100000 { |
| compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; |
| reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x00100000 0x1c000>; |
| |
| serdes_ln_ctrl: serdes-ln-ctrl@4080 { |
| compatible = "mmio-mux"; |
| reg = <0x00004080 0x50>; |
| #mux-control-cells = <1>; |
| mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ |
| <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ |
| <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ |
| <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ |
| <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; |
| /* SERDES4 lane0/1/2/3 select */ |
| idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>, |
| <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>, |
| <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>, |
| <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>, |
| <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>; |
| }; |
| |
| usb_serdes_mux: mux-controller@4000 { |
| compatible = "mmio-mux"; |
| #mux-control-cells = <1>; |
| mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ |
| <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ |
| }; |
| }; |
| |
| gic500: interrupt-controller@1800000 { |
| compatible = "arm,gic-v3"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ |
| <0x00 0x01900000 0x00 0x100000>; /* GICR */ |
| |
| /* vcpumntirq: virtual CPU interface maintenance interrupt */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| |
| gic_its: msi-controller@1820000 { |
| compatible = "arm,gic-v3-its"; |
| reg = <0x00 0x01820000 0x00 0x10000>; |
| socionext,synquacer-pre-its = <0x1000000 0x400000>; |
| msi-controller; |
| #msi-cells = <1>; |
| }; |
| }; |
| |
| main_gpio_intr: interrupt-controller0 { |
| compatible = "ti,sci-intr"; |
| ti,intr-trigger-type = <1>; |
| interrupt-controller; |
| interrupt-parent = <&gic500>; |
| #interrupt-cells = <1>; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <131>; |
| ti,interrupt-ranges = <8 392 56>; |
| }; |
| |
| main_navss { |
| compatible = "simple-mfd"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| dma-coherent; |
| dma-ranges; |
| |
| ti,sci-dev-id = <199>; |
| |
| main_navss_intr: interrupt-controller1 { |
| compatible = "ti,sci-intr"; |
| ti,intr-trigger-type = <4>; |
| interrupt-controller; |
| interrupt-parent = <&gic500>; |
| #interrupt-cells = <1>; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <213>; |
| ti,interrupt-ranges = <0 64 64>, |
| <64 448 64>, |
| <128 672 64>; |
| }; |
| |
| main_udmass_inta: interrupt-controller@33d00000 { |
| compatible = "ti,sci-inta"; |
| reg = <0x0 0x33d00000 0x0 0x100000>; |
| interrupt-controller; |
| interrupt-parent = <&main_navss_intr>; |
| msi-controller; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <209>; |
| ti,interrupt-ranges = <0 0 256>; |
| }; |
| |
| secure_proxy_main: mailbox@32c00000 { |
| compatible = "ti,am654-secure-proxy"; |
| #mbox-cells = <1>; |
| reg-names = "target_data", "rt", "scfg"; |
| reg = <0x00 0x32c00000 0x00 0x100000>, |
| <0x00 0x32400000 0x00 0x100000>, |
| <0x00 0x32800000 0x00 0x100000>; |
| interrupt-names = "rx_011"; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| smmu0: iommu@36600000 { |
| compatible = "arm,smmu-v3"; |
| reg = <0x0 0x36600000 0x0 0x100000>; |
| interrupt-parent = <&gic500>; |
| interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "eventq", "gerror"; |
| #iommu-cells = <1>; |
| }; |
| |
| hwspinlock: spinlock@30e00000 { |
| compatible = "ti,am654-hwspinlock"; |
| reg = <0x00 0x30e00000 0x00 0x1000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| mailbox0_cluster0: mailbox@31f80000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f80000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster1: mailbox@31f81000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f81000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster2: mailbox@31f82000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f82000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster3: mailbox@31f83000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f83000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster4: mailbox@31f84000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f84000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster5: mailbox@31f85000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f85000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster6: mailbox@31f86000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f86000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster7: mailbox@31f87000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f87000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster8: mailbox@31f88000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f88000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster9: mailbox@31f89000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f89000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster10: mailbox@31f8a000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f8a000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| mailbox0_cluster11: mailbox@31f8b000 { |
| compatible = "ti,am654-mailbox"; |
| reg = <0x00 0x31f8b000 0x00 0x200>; |
| #mbox-cells = <1>; |
| ti,mbox-num-users = <4>; |
| ti,mbox-num-fifos = <16>; |
| interrupt-parent = <&main_navss_intr>; |
| }; |
| |
| main_ringacc: ringacc@3c000000 { |
| compatible = "ti,am654-navss-ringacc"; |
| reg = <0x0 0x3c000000 0x0 0x400000>, |
| <0x0 0x38000000 0x0 0x400000>, |
| <0x0 0x31120000 0x0 0x100>, |
| <0x0 0x33000000 0x0 0x40000>; |
| reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; |
| ti,num-rings = <1024>; |
| ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <211>; |
| msi-parent = <&main_udmass_inta>; |
| }; |
| |
| main_udmap: dma-controller@31150000 { |
| compatible = "ti,j721e-navss-main-udmap"; |
| reg = <0x0 0x31150000 0x0 0x100>, |
| <0x0 0x34000000 0x0 0x100000>, |
| <0x0 0x35000000 0x0 0x100000>; |
| reg-names = "gcfg", "rchanrt", "tchanrt"; |
| msi-parent = <&main_udmass_inta>; |
| #dma-cells = <1>; |
| |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <212>; |
| ti,ringacc = <&main_ringacc>; |
| |
| ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ |
| <0x0f>, /* TX_HCHAN */ |
| <0x10>; /* TX_UHCHAN */ |
| ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ |
| <0x0b>, /* RX_HCHAN */ |
| <0x0c>; /* RX_UHCHAN */ |
| ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ |
| }; |
| |
| cpts@310d0000 { |
| compatible = "ti,j721e-cpts"; |
| reg = <0x0 0x310d0000 0x0 0x400>; |
| reg-names = "cpts"; |
| clocks = <&k3_clks 201 1>; |
| clock-names = "cpts"; |
| interrupts-extended = <&main_navss_intr 391>; |
| interrupt-names = "cpts"; |
| ti,cpts-periodic-outputs = <6>; |
| ti,cpts-ext-ts-inputs = <8>; |
| }; |
| }; |
| |
| main_pmx0: pinmux@11c000 { |
| compatible = "pinctrl-single"; |
| /* Proxy 0 addressing */ |
| reg = <0x0 0x11c000 0x0 0x2b4>; |
| #pinctrl-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0xffffffff>; |
| }; |
| |
| dummy_cmn_refclk: dummy-cmn-refclk { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <100000000>; |
| }; |
| |
| dummy_cmn_refclk1: dummy-cmn-refclk1 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <100000000>; |
| }; |
| |
| serdes_wiz0: wiz@5000000 { |
| compatible = "ti,j721e-wiz-16g"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; |
| clock-names = "fck", "core_ref_clk", "ext_ref_clk"; |
| assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; |
| assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; |
| num-lanes = <2>; |
| #reset-cells = <1>; |
| ranges = <0x5000000 0x0 0x5000000 0x10000>; |
| |
| wiz0_pll0_refclk: pll0-refclk { |
| clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz0_pll0_refclk>; |
| assigned-clock-parents = <&k3_clks 292 11>; |
| }; |
| |
| wiz0_pll1_refclk: pll1-refclk { |
| clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz0_pll1_refclk>; |
| assigned-clock-parents = <&k3_clks 292 0>; |
| }; |
| |
| wiz0_refclk_dig: refclk-dig { |
| clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz0_refclk_dig>; |
| assigned-clock-parents = <&k3_clks 292 11>; |
| }; |
| |
| wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { |
| clocks = <&wiz0_refclk_dig>; |
| #clock-cells = <0>; |
| }; |
| |
| wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { |
| clocks = <&wiz0_pll1_refclk>; |
| #clock-cells = <0>; |
| }; |
| |
| serdes0: serdes@5000000 { |
| compatible = "ti,sierra-phy-t0"; |
| reg-names = "serdes"; |
| reg = <0x5000000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| resets = <&serdes_wiz0 0>; |
| reset-names = "sierra_reset"; |
| clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; |
| clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; |
| }; |
| }; |
| |
| serdes_wiz1: wiz@5010000 { |
| compatible = "ti,j721e-wiz-16g"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>; |
| clock-names = "fck", "core_ref_clk", "ext_ref_clk"; |
| assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; |
| assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; |
| num-lanes = <2>; |
| #reset-cells = <1>; |
| ranges = <0x5010000 0x0 0x5010000 0x10000>; |
| |
| wiz1_pll0_refclk: pll0-refclk { |
| clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz1_pll0_refclk>; |
| assigned-clock-parents = <&k3_clks 293 13>; |
| }; |
| |
| wiz1_pll1_refclk: pll1-refclk { |
| clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz1_pll1_refclk>; |
| assigned-clock-parents = <&k3_clks 293 0>; |
| }; |
| |
| wiz1_refclk_dig: refclk-dig { |
| clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz1_refclk_dig>; |
| assigned-clock-parents = <&k3_clks 293 13>; |
| }; |
| |
| wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ |
| clocks = <&wiz1_refclk_dig>; |
| #clock-cells = <0>; |
| }; |
| |
| wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { |
| clocks = <&wiz1_pll1_refclk>; |
| #clock-cells = <0>; |
| }; |
| |
| serdes1: serdes@5010000 { |
| compatible = "ti,sierra-phy-t0"; |
| reg-names = "serdes"; |
| reg = <0x5010000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| resets = <&serdes_wiz1 0>; |
| reset-names = "sierra_reset"; |
| clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>; |
| clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; |
| }; |
| }; |
| |
| serdes_wiz2: wiz@5020000 { |
| compatible = "ti,j721e-wiz-16g"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>; |
| clock-names = "fck", "core_ref_clk", "ext_ref_clk"; |
| assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; |
| assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; |
| num-lanes = <2>; |
| #reset-cells = <1>; |
| ranges = <0x5020000 0x0 0x5020000 0x10000>; |
| |
| wiz2_pll0_refclk: pll0-refclk { |
| clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz2_pll0_refclk>; |
| assigned-clock-parents = <&k3_clks 294 11>; |
| }; |
| |
| wiz2_pll1_refclk: pll1-refclk { |
| clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz2_pll1_refclk>; |
| assigned-clock-parents = <&k3_clks 294 0>; |
| }; |
| |
| wiz2_refclk_dig: refclk-dig { |
| clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz2_refclk_dig>; |
| assigned-clock-parents = <&k3_clks 294 11>; |
| }; |
| |
| wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { |
| clocks = <&wiz2_refclk_dig>; |
| #clock-cells = <0>; |
| }; |
| |
| wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { |
| clocks = <&wiz2_pll1_refclk>; |
| #clock-cells = <0>; |
| }; |
| |
| serdes2: serdes@5020000 { |
| compatible = "ti,sierra-phy-t0"; |
| reg-names = "serdes"; |
| reg = <0x5020000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| resets = <&serdes_wiz2 0>; |
| reset-names = "sierra_reset"; |
| clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>; |
| clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; |
| }; |
| }; |
| |
| serdes_wiz3: wiz@5030000 { |
| compatible = "ti,j721e-wiz-16g"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>; |
| clock-names = "fck", "core_ref_clk", "ext_ref_clk"; |
| assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; |
| assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; |
| num-lanes = <2>; |
| #reset-cells = <1>; |
| ranges = <0x5030000 0x0 0x5030000 0x10000>; |
| |
| wiz3_pll0_refclk: pll0-refclk { |
| clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz3_pll0_refclk>; |
| assigned-clock-parents = <&k3_clks 295 9>; |
| }; |
| |
| wiz3_pll1_refclk: pll1-refclk { |
| clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz3_pll1_refclk>; |
| assigned-clock-parents = <&k3_clks 295 0>; |
| }; |
| |
| wiz3_refclk_dig: refclk-dig { |
| clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; |
| #clock-cells = <0>; |
| assigned-clocks = <&wiz3_refclk_dig>; |
| assigned-clock-parents = <&k3_clks 295 9>; |
| }; |
| |
| wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { |
| clocks = <&wiz3_refclk_dig>; |
| #clock-cells = <0>; |
| }; |
| |
| wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { |
| clocks = <&wiz3_pll1_refclk>; |
| #clock-cells = <0>; |
| }; |
| |
| serdes3: serdes@5030000 { |
| compatible = "ti,sierra-phy-t0"; |
| reg-names = "serdes"; |
| reg = <0x5030000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| resets = <&serdes_wiz3 0>; |
| reset-names = "sierra_reset"; |
| clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>; |
| clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; |
| }; |
| }; |
| |
| main_uart0: serial@2800000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02800000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 146 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart1: serial@2810000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02810000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 278 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart2: serial@2820000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02820000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 279 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart3: serial@2830000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02830000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 280 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart4: serial@2840000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02840000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 281 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart5: serial@2850000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02850000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 282 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart6: serial@2860000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02860000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 283 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart7: serial@2870000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02870000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 284 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart8: serial@2880000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02880000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 285 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_uart9: serial@2890000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x02890000 0x00 0x100>; |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 286 0>; |
| clock-names = "fclk"; |
| }; |
| |
| main_gpio0: gpio@600000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x0 0x00600000 0x0 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <256>, <257>, <258>, <259>, |
| <260>, <261>, <262>, <263>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <128>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 105 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_gpio1: gpio@601000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x0 0x00601000 0x0 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <288>, <289>, <290>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <36>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 106 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_gpio2: gpio@610000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x0 0x00610000 0x0 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <264>, <265>, <266>, <267>, |
| <268>, <269>, <270>, <271>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <128>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 107 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_gpio3: gpio@611000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x0 0x00611000 0x0 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <292>, <293>, <294>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <36>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 108 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_gpio4: gpio@620000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x0 0x00620000 0x0 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <272>, <273>, <274>, <275>, |
| <276>, <277>, <278>, <279>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <128>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 109 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_gpio5: gpio@621000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x0 0x00621000 0x0 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <296>, <297>, <298>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <36>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 110 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_gpio6: gpio@630000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x0 0x00630000 0x0 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <280>, <281>, <282>, <283>, |
| <284>, <285>, <286>, <287>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <128>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 111 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_gpio7: gpio@631000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x0 0x00631000 0x0 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <300>, <301>, <302>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <36>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 112 0>; |
| clock-names = "gpio"; |
| }; |
| |
| main_sdhci0: sdhci@4f80000 { |
| compatible = "ti,j721e-sdhci-8bit"; |
| reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; |
| clock-names = "clk_xin", "clk_ahb"; |
| clocks = <&k3_clks 91 1>, <&k3_clks 91 0>; |
| assigned-clocks = <&k3_clks 91 1>; |
| assigned-clock-parents = <&k3_clks 91 2>; |
| bus-width = <8>; |
| mmc-hs400-1_8v; |
| mmc-ddr-1_8v; |
| ti,otap-del-sel = <0x2>; |
| ti,trm-icp = <0x8>; |
| ti,strobe-sel = <0x77>; |
| dma-coherent; |
| }; |
| |
| main_sdhci1: sdhci@4fb0000 { |
| compatible = "ti,j721e-sdhci-4bit"; |
| reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; |
| clock-names = "clk_xin", "clk_ahb"; |
| clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; |
| assigned-clocks = <&k3_clks 92 0>; |
| assigned-clock-parents = <&k3_clks 92 1>; |
| ti,otap-del-sel = <0x2>; |
| ti,trm-icp = <0x8>; |
| ti,clkbuf-sel = <0x7>; |
| dma-coherent; |
| no-1-8-v; |
| }; |
| |
| main_sdhci2: sdhci@4f98000 { |
| compatible = "ti,j721e-sdhci-4bit"; |
| reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; |
| clock-names = "clk_xin", "clk_ahb"; |
| clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; |
| assigned-clocks = <&k3_clks 93 0>; |
| assigned-clock-parents = <&k3_clks 93 1>; |
| ti,otap-del-sel = <0x2>; |
| ti,trm-icp = <0x8>; |
| ti,clkbuf-sel = <0x7>; |
| dma-coherent; |
| no-1-8-v; |
| }; |
| |
| usbss0: cdns_usb@4104000 { |
| compatible = "ti,j721e-usb"; |
| reg = <0x00 0x4104000 0x00 0x100>; |
| dma-coherent; |
| power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; |
| clock-names = "ref", "lpm"; |
| assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ |
| assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| usb0: usb@6000000 { |
| compatible = "cdns,usb3"; |
| reg = <0x00 0x6000000 0x00 0x10000>, |
| <0x00 0x6010000 0x00 0x10000>, |
| <0x00 0x6020000 0x00 0x10000>; |
| reg-names = "otg", "xhci", "dev"; |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ |
| <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ |
| <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ |
| interrupt-names = "host", |
| "peripheral", |
| "otg"; |
| maximum-speed = "super-speed"; |
| dr_mode = "otg"; |
| }; |
| }; |
| |
| usbss1: cdns_usb@4114000 { |
| compatible = "ti,j721e-usb"; |
| reg = <0x00 0x4114000 0x00 0x100>; |
| dma-coherent; |
| power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; |
| clock-names = "ref", "lpm"; |
| assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ |
| assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| usb1: usb@6400000 { |
| compatible = "cdns,usb3"; |
| reg = <0x00 0x6400000 0x00 0x10000>, |
| <0x00 0x6410000 0x00 0x10000>, |
| <0x00 0x6420000 0x00 0x10000>; |
| reg-names = "otg", "xhci", "dev"; |
| interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ |
| <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ |
| <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ |
| interrupt-names = "host", |
| "peripheral", |
| "otg"; |
| maximum-speed = "super-speed"; |
| dr_mode = "otg"; |
| }; |
| }; |
| |
| main_i2c0: i2c@2000000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x0 0x2000000 0x0 0x100>; |
| interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 187 0>; |
| power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; |
| }; |
| |
| main_i2c1: i2c@2010000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x0 0x2010000 0x0 0x100>; |
| interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 188 0>; |
| power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; |
| }; |
| |
| main_i2c2: i2c@2020000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x0 0x2020000 0x0 0x100>; |
| interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 189 0>; |
| power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; |
| }; |
| |
| main_i2c3: i2c@2030000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x0 0x2030000 0x0 0x100>; |
| interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 190 0>; |
| power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; |
| }; |
| |
| main_i2c4: i2c@2040000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x0 0x2040000 0x0 0x100>; |
| interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 191 0>; |
| power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; |
| }; |
| |
| main_i2c5: i2c@2050000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x0 0x2050000 0x0 0x100>; |
| interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 192 0>; |
| power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; |
| }; |
| |
| main_i2c6: i2c@2060000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x0 0x2060000 0x0 0x100>; |
| interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "fck"; |
| clocks = <&k3_clks 193 0>; |
| power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; |
| }; |
| |
| ufs_wrapper: ufs-wrapper@4e80000 { |
| compatible = "ti,j721e-ufs"; |
| reg = <0x0 0x4e80000 0x0 0x100>; |
| power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 277 1>; |
| assigned-clocks = <&k3_clks 277 1>; |
| assigned-clock-parents = <&k3_clks 277 4>; |
| ranges; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| ufs@4e84000 { |
| compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; |
| reg = <0x0 0x4e84000 0x0 0x10000>; |
| interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; |
| clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; |
| clock-names = "core_clk", "phy_clk", "ref_clk"; |
| dma-coherent; |
| }; |
| }; |
| |
| dss: dss@04a00000 { |
| compatible = "ti,j721e-dss"; |
| reg = |
| <0x00 0x04a00000 0x00 0x10000>, /* common_m */ |
| <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ |
| <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ |
| <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ |
| |
| <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ |
| <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ |
| <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ |
| <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ |
| |
| <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ |
| <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ |
| <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ |
| <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ |
| |
| <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ |
| <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ |
| <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ |
| <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ |
| <0x00 0x04af0000 0x00 0x10000>; /* wb */ |
| |
| reg-names = "common_m", "common_s0", |
| "common_s1", "common_s2", |
| "vidl1", "vidl2","vid1","vid2", |
| "ovr1", "ovr2", "ovr3", "ovr4", |
| "vp1", "vp2", "vp3", "vp4", |
| "wb"; |
| |
| clocks = <&k3_clks 152 0>, |
| <&k3_clks 152 1>, |
| <&k3_clks 152 4>, |
| <&k3_clks 152 9>, |
| <&k3_clks 152 13>; |
| clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; |
| |
| power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; |
| |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "common_m", |
| "common_s0", |
| "common_s1", |
| "common_s2"; |
| |
| status = "disabled"; |
| |
| dss_ports: ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| mcasp0: mcasp@2b00000 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x02b00000 0x0 0x2000>, |
| <0x0 0x02b08000 0x0 0x1000>; |
| reg-names = "mpu","dat"; |
| interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| |
| dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; |
| dma-names = "tx", "rx"; |
| |
| clocks = <&k3_clks 174 1>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; |
| |
| status = "disabled"; |
| }; |
| |
| mcasp1: mcasp@2b10000 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x02b10000 0x0 0x2000>, |
| <0x0 0x02b18000 0x0 0x1000>; |
| reg-names = "mpu","dat"; |
| interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| |
| dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; |
| dma-names = "tx", "rx"; |
| |
| clocks = <&k3_clks 175 1>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; |
| |
| status = "disabled"; |
| }; |
| |
| mcasp2: mcasp@2b20000 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x02b20000 0x0 0x2000>, |
| <0x0 0x02b28000 0x0 0x1000>; |
| reg-names = "mpu","dat"; |
| interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| |
| dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; |
| dma-names = "tx", "rx"; |
| |
| clocks = <&k3_clks 176 1>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; |
| |
| status = "disabled"; |
| }; |
| |
| mcasp3: mcasp@2b30000 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x02b30000 0x0 0x2000>, |
| <0x0 0x02b38000 0x0 0x1000>; |
| reg-names = "mpu","dat"; |
| interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| |
| dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; |
| dma-names = "tx", "rx"; |
| |
| clocks = <&k3_clks 177 1>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; |
| |
| status = "disabled"; |
| }; |
| |
| mcasp4: mcasp@2b40000 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x02b40000 0x0 0x2000>, |
| <0x0 0x02b48000 0x0 0x1000>; |
| reg-names = "mpu","dat"; |
| interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| |
| dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; |
| dma-names = "tx", "rx"; |
| |
| clocks = <&k3_clks 178 1>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; |
| |
| status = "disabled"; |
| }; |
| |
| mcasp5: mcasp@2b50000 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x02b50000 0x0 0x2000>, |
| <0x0 0x02b58000 0x0 0x1000>; |
| reg-names = "mpu","dat"; |
| interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| |
| dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; |
| dma-names = "tx", "rx"; |
| |
| clocks = <&k3_clks 179 1>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; |
| |
| status = "disabled"; |
| }; |
| |
| mcasp6: mcasp@2b60000 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x02b60000 0x0 0x2000>, |
| <0x0 0x02b68000 0x0 0x1000>; |
| reg-names = "mpu","dat"; |
| interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| |
| dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; |
| dma-names = "tx", "rx"; |
| |
| clocks = <&k3_clks 180 1>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; |
| |
| status = "disabled"; |
| }; |
| |
| mcasp7: mcasp@2b70000 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x02b70000 0x0 0x2000>, |
| <0x0 0x02b78000 0x0 0x1000>; |
| reg-names = "mpu","dat"; |
| interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| |
| dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; |
| dma-names = "tx", "rx"; |
| |
| clocks = <&k3_clks 181 1>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; |
| |
| status = "disabled"; |
| }; |
| |
| mcasp8: mcasp@2b80000 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x02b80000 0x0 0x2000>, |
| <0x0 0x02b88000 0x0 0x1000>; |
| reg-names = "mpu","dat"; |
| interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| |
| dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; |
| dma-names = "tx", "rx"; |
| |
| clocks = <&k3_clks 182 1>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; |
| |
| status = "disabled"; |
| }; |
| |
| mcasp9: mcasp@2b90000 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x02b90000 0x0 0x2000>, |
| <0x0 0x02b98000 0x0 0x1000>; |
| reg-names = "mpu","dat"; |
| interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| |
| dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; |
| dma-names = "tx", "rx"; |
| |
| clocks = <&k3_clks 183 1>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; |
| |
| status = "disabled"; |
| }; |
| |
| mcasp10: mcasp@2ba0000 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x02ba0000 0x0 0x2000>, |
| <0x0 0x02ba8000 0x0 0x1000>; |
| reg-names = "mpu","dat"; |
| interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| |
| dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; |
| dma-names = "tx", "rx"; |
| |
| clocks = <&k3_clks 184 1>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; |
| |
| status = "disabled"; |
| }; |
| |
| mcasp11: mcasp@2bb0000 { |
| compatible = "ti,am33xx-mcasp-audio"; |
| reg = <0x0 0x02bb0000 0x0 0x2000>, |
| <0x0 0x02bb8000 0x0 0x1000>; |
| reg-names = "mpu","dat"; |
| interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tx", "rx"; |
| |
| dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; |
| dma-names = "tx", "rx"; |
| |
| clocks = <&k3_clks 185 1>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; |
| |
| status = "disabled"; |
| }; |
| |
| watchdog0: watchdog@2200000 { |
| compatible = "ti,j7-rti-wdt"; |
| reg = <0x0 0x2200000 0x0 0x100>; |
| clocks = <&k3_clks 252 1>; |
| power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; |
| assigned-clocks = <&k3_clks 252 1>; |
| assigned-clock-parents = <&k3_clks 252 5>; |
| }; |
| |
| watchdog1: watchdog@2210000 { |
| compatible = "ti,j7-rti-wdt"; |
| reg = <0x0 0x2210000 0x0 0x100>; |
| clocks = <&k3_clks 253 1>; |
| power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; |
| assigned-clocks = <&k3_clks 253 1>; |
| assigned-clock-parents = <&k3_clks 253 5>; |
| }; |
| }; |
