blob: 6fc70e441458de27128e0ac36fcbd11790e8d8b8 [file] [log] [blame]
/*
* rt5677.c -- RT5677 ALSA SoC audio codec driver
*
* Copyright 2013 Realtek Semiconductor Corp.
* Author: Oder Chiou <oder_chiou@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/firmware.h>
#include <linux/of_device.h>
#include <linux/property.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rl6231.h"
#include "rt5677.h"
#include "rt5677-spi.h"
#define RT5677_DEVICE_ID 0x6327
#define RT5677_PR_RANGE_BASE (0xff + 1)
#define RT5677_PR_SPACING 0x100
#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
static const struct regmap_range_cfg rt5677_ranges[] = {
{
.name = "PR",
.range_min = RT5677_PR_BASE,
.range_max = RT5677_PR_BASE + 0xfd,
.selector_reg = RT5677_PRIV_INDEX,
.selector_mask = 0xff,
.selector_shift = 0x0,
.window_start = RT5677_PRIV_DATA,
.window_len = 0x1,
},
};
static const struct reg_sequence init_list[] = {
{RT5677_ASRC_12, 0x0018},
{RT5677_PR_BASE + 0x3d, 0x364d},
{RT5677_PR_BASE + 0x17, 0x4fc0},
{RT5677_PR_BASE + 0x13, 0x0312},
{RT5677_PR_BASE + 0x1e, 0x0000},
{RT5677_PR_BASE + 0x12, 0x0eaa},
{RT5677_PR_BASE + 0x14, 0x018a},
{RT5677_PR_BASE + 0x15, 0x0490},
{RT5677_PR_BASE + 0x38, 0x0f71},
{RT5677_PR_BASE + 0x39, 0x0f71},
};
#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
static const struct reg_default rt5677_reg[] = {
{RT5677_RESET , 0x0000},
{RT5677_LOUT1 , 0xa800},
{RT5677_IN1 , 0x0000},
{RT5677_MICBIAS , 0x0000},
{RT5677_SLIMBUS_PARAM , 0x0000},
{RT5677_SLIMBUS_RX , 0x0000},
{RT5677_SLIMBUS_CTRL , 0x0000},
{RT5677_SIDETONE_CTRL , 0x000b},
{RT5677_ANA_DAC1_2_3_SRC , 0x0000},
{RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
{RT5677_DAC4_DIG_VOL , 0xafaf},
{RT5677_DAC3_DIG_VOL , 0xafaf},
{RT5677_DAC1_DIG_VOL , 0xafaf},
{RT5677_DAC2_DIG_VOL , 0xafaf},
{RT5677_IF_DSP_DAC2_MIXER , 0x0011},
{RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
{RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
{RT5677_STO1_2_ADC_BST , 0x0000},
{RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
{RT5677_ADC_BST_CTRL2 , 0x0000},
{RT5677_STO3_4_ADC_BST , 0x0000},
{RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
{RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
{RT5677_STO4_ADC_MIXER , 0xd4c0},
{RT5677_STO3_ADC_MIXER , 0xd4c0},
{RT5677_STO2_ADC_MIXER , 0xd4c0},
{RT5677_STO1_ADC_MIXER , 0xd4c0},
{RT5677_MONO_ADC_MIXER , 0xd4d1},
{RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
{RT5677_STO1_DAC_MIXER , 0xaaaa},
{RT5677_MONO_DAC_MIXER , 0xaaaa},
{RT5677_DD1_MIXER , 0xaaaa},
{RT5677_DD2_MIXER , 0xaaaa},
{RT5677_IF3_DATA , 0x0000},
{RT5677_IF4_DATA , 0x0000},
{RT5677_PDM_OUT_CTRL , 0x8888},
{RT5677_PDM_DATA_CTRL1 , 0x0000},
{RT5677_PDM_DATA_CTRL2 , 0x0000},
{RT5677_PDM1_DATA_CTRL2 , 0x0000},
{RT5677_PDM1_DATA_CTRL3 , 0x0000},
{RT5677_PDM1_DATA_CTRL4 , 0x0000},
{RT5677_PDM2_DATA_CTRL2 , 0x0000},
{RT5677_PDM2_DATA_CTRL3 , 0x0000},
{RT5677_PDM2_DATA_CTRL4 , 0x0000},
{RT5677_TDM1_CTRL1 , 0x0300},
{RT5677_TDM1_CTRL2 , 0x0000},
{RT5677_TDM1_CTRL3 , 0x4000},
{RT5677_TDM1_CTRL4 , 0x0123},
{RT5677_TDM1_CTRL5 , 0x4567},
{RT5677_TDM2_CTRL1 , 0x0300},
{RT5677_TDM2_CTRL2 , 0x0000},
{RT5677_TDM2_CTRL3 , 0x4000},
{RT5677_TDM2_CTRL4 , 0x0123},
{RT5677_TDM2_CTRL5 , 0x4567},
{RT5677_I2C_MASTER_CTRL1 , 0x0001},
{RT5677_I2C_MASTER_CTRL2 , 0x0000},
{RT5677_I2C_MASTER_CTRL3 , 0x0000},
{RT5677_I2C_MASTER_CTRL4 , 0x0000},
{RT5677_I2C_MASTER_CTRL5 , 0x0000},
{RT5677_I2C_MASTER_CTRL6 , 0x0000},
{RT5677_I2C_MASTER_CTRL7 , 0x0000},
{RT5677_I2C_MASTER_CTRL8 , 0x0000},
{RT5677_DMIC_CTRL1 , 0x1505},
{RT5677_DMIC_CTRL2 , 0x0055},
{RT5677_HAP_GENE_CTRL1 , 0x0111},
{RT5677_HAP_GENE_CTRL2 , 0x0064},
{RT5677_HAP_GENE_CTRL3 , 0xef0e},
{RT5677_HAP_GENE_CTRL4 , 0xf0f0},
{RT5677_HAP_GENE_CTRL5 , 0xef0e},
{RT5677_HAP_GENE_CTRL6 , 0xf0f0},
{RT5677_HAP_GENE_CTRL7 , 0xef0e},
{RT5677_HAP_GENE_CTRL8 , 0xf0f0},
{RT5677_HAP_GENE_CTRL9 , 0xf000},
{RT5677_HAP_GENE_CTRL10 , 0x0000},
{RT5677_PWR_DIG1 , 0x0000},
{RT5677_PWR_DIG2 , 0x0000},
{RT5677_PWR_ANLG1 , 0x0055},
{RT5677_PWR_ANLG2 , 0x0000},
{RT5677_PWR_DSP1 , 0x0001},
{RT5677_PWR_DSP_ST , 0x0000},
{RT5677_PWR_DSP2 , 0x0000},
{RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
{RT5677_PRIV_INDEX , 0x0000},
{RT5677_PRIV_DATA , 0x0000},
{RT5677_I2S4_SDP , 0x8000},
{RT5677_I2S1_SDP , 0x8000},
{RT5677_I2S2_SDP , 0x8000},
{RT5677_I2S3_SDP , 0x8000},
{RT5677_CLK_TREE_CTRL1 , 0x1111},
{RT5677_CLK_TREE_CTRL2 , 0x1111},
{RT5677_CLK_TREE_CTRL3 , 0x0000},
{RT5677_PLL1_CTRL1 , 0x0000},
{RT5677_PLL1_CTRL2 , 0x0000},
{RT5677_PLL2_CTRL1 , 0x0c60},
{RT5677_PLL2_CTRL2 , 0x2000},
{RT5677_GLB_CLK1 , 0x0000},
{RT5677_GLB_CLK2 , 0x0000},
{RT5677_ASRC_1 , 0x0000},
{RT5677_ASRC_2 , 0x0000},
{RT5677_ASRC_3 , 0x0000},
{RT5677_ASRC_4 , 0x0000},
{RT5677_ASRC_5 , 0x0000},
{RT5677_ASRC_6 , 0x0000},
{RT5677_ASRC_7 , 0x0000},
{RT5677_ASRC_8 , 0x0000},
{RT5677_ASRC_9 , 0x0000},
{RT5677_ASRC_10 , 0x0000},
{RT5677_ASRC_11 , 0x0000},
{RT5677_ASRC_12 , 0x0018},
{RT5677_ASRC_13 , 0x0000},
{RT5677_ASRC_14 , 0x0000},
{RT5677_ASRC_15 , 0x0000},
{RT5677_ASRC_16 , 0x0000},
{RT5677_ASRC_17 , 0x0000},
{RT5677_ASRC_18 , 0x0000},
{RT5677_ASRC_19 , 0x0000},
{RT5677_ASRC_20 , 0x0000},
{RT5677_ASRC_21 , 0x000c},
{RT5677_ASRC_22 , 0x0000},
{RT5677_ASRC_23 , 0x0000},
{RT5677_VAD_CTRL1 , 0x2184},
{RT5677_VAD_CTRL2 , 0x010a},
{RT5677_VAD_CTRL3 , 0x0aea},
{RT5677_VAD_CTRL4 , 0x000c},
{RT5677_VAD_CTRL5 , 0x0000},
{RT5677_DSP_INB_CTRL1 , 0x0000},
{RT5677_DSP_INB_CTRL2 , 0x0000},
{RT5677_DSP_IN_OUTB_CTRL , 0x0000},
{RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
{RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
{RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
{RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
{RT5677_ADC_EQ_CTRL1 , 0x6000},
{RT5677_ADC_EQ_CTRL2 , 0x0000},
{RT5677_EQ_CTRL1 , 0xc000},
{RT5677_EQ_CTRL2 , 0x0000},
{RT5677_EQ_CTRL3 , 0x0000},
{RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
{RT5677_JD_CTRL1 , 0x0000},
{RT5677_JD_CTRL2 , 0x0000},
{RT5677_JD_CTRL3 , 0x0000},
{RT5677_IRQ_CTRL1 , 0x0000},
{RT5677_IRQ_CTRL2 , 0x0000},
{RT5677_GPIO_ST , 0x0000},
{RT5677_GPIO_CTRL1 , 0x0000},
{RT5677_GPIO_CTRL2 , 0x0000},
{RT5677_GPIO_CTRL3 , 0x0000},
{RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
{RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
{RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
{RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
{RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
{RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
{RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
{RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
{RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
{RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
{RT5677_MB_DRC_CTRL1 , 0x0f20},
{RT5677_DRC1_CTRL1 , 0x001f},
{RT5677_DRC1_CTRL2 , 0x020c},
{RT5677_DRC1_CTRL3 , 0x1f00},
{RT5677_DRC1_CTRL4 , 0x0000},
{RT5677_DRC1_CTRL5 , 0x0000},
{RT5677_DRC1_CTRL6 , 0x0029},
{RT5677_DRC2_CTRL1 , 0x001f},
{RT5677_DRC2_CTRL2 , 0x020c},
{RT5677_DRC2_CTRL3 , 0x1f00},
{RT5677_DRC2_CTRL4 , 0x0000},
{RT5677_DRC2_CTRL5 , 0x0000},
{RT5677_DRC2_CTRL6 , 0x0029},
{RT5677_DRC1_HL_CTRL1 , 0x8000},
{RT5677_DRC1_HL_CTRL2 , 0x0200},
{RT5677_DRC2_HL_CTRL1 , 0x8000},
{RT5677_DRC2_HL_CTRL2 , 0x0200},
{RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
{RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
{RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
{RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
{RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
{RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
{RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
{RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
{RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
{RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
{RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
{RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
{RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
{RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
{RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
{RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
{RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
{RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
{RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
{RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
{RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
{RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
{RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
{RT5677_DIG_MISC , 0x0000},
{RT5677_GEN_CTRL1 , 0x0000},
{RT5677_GEN_CTRL2 , 0x0000},
{RT5677_VENDOR_ID , 0x0000},
{RT5677_VENDOR_ID1 , 0x10ec},
{RT5677_VENDOR_ID2 , 0x6327},
};
static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
if (reg >= rt5677_ranges[i].range_min &&
reg <= rt5677_ranges[i].range_max) {
return true;
}
}
switch (reg) {
case RT5677_RESET:
case RT5677_SLIMBUS_PARAM:
case RT5677_PDM_DATA_CTRL1:
case RT5677_PDM_DATA_CTRL2:
case RT5677_PDM1_DATA_CTRL4:
case RT5677_PDM2_DATA_CTRL4:
case RT5677_I2C_MASTER_CTRL1:
case RT5677_I2C_MASTER_CTRL7:
case RT5677_I2C_MASTER_CTRL8:
case RT5677_HAP_GENE_CTRL2:
case RT5677_PWR_DSP_ST:
case RT5677_PRIV_DATA:
case RT5677_ASRC_22:
case RT5677_ASRC_23:
case RT5677_VAD_CTRL5:
case RT5677_ADC_EQ_CTRL1:
case RT5677_EQ_CTRL1:
case RT5677_IRQ_CTRL1:
case RT5677_IRQ_CTRL2:
case RT5677_GPIO_ST:
case RT5677_DSP_INB1_SRC_CTRL4:
case RT5677_DSP_INB2_SRC_CTRL4:
case RT5677_DSP_INB3_SRC_CTRL4:
case RT5677_DSP_OUTB1_SRC_CTRL4:
case RT5677_DSP_OUTB2_SRC_CTRL4:
case RT5677_VENDOR_ID:
case RT5677_VENDOR_ID1:
case RT5677_VENDOR_ID2:
return true;
default:
return false;
}
}
static bool rt5677_readable_register(struct device *dev, unsigned int reg)
{
int i;
for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
if (reg >= rt5677_ranges[i].range_min &&
reg <= rt5677_ranges[i].range_max) {
return true;
}
}
switch (reg) {
case RT5677_RESET:
case RT5677_LOUT1:
case RT5677_IN1:
case RT5677_MICBIAS:
case RT5677_SLIMBUS_PARAM:
case RT5677_SLIMBUS_RX:
case RT5677_SLIMBUS_CTRL:
case RT5677_SIDETONE_CTRL:
case RT5677_ANA_DAC1_2_3_SRC:
case RT5677_IF_DSP_DAC3_4_MIXER:
case RT5677_DAC4_DIG_VOL:
case RT5677_DAC3_DIG_VOL:
case RT5677_DAC1_DIG_VOL:
case RT5677_DAC2_DIG_VOL:
case RT5677_IF_DSP_DAC2_MIXER:
case RT5677_STO1_ADC_DIG_VOL:
case RT5677_MONO_ADC_DIG_VOL:
case RT5677_STO1_2_ADC_BST:
case RT5677_STO2_ADC_DIG_VOL:
case RT5677_ADC_BST_CTRL2:
case RT5677_STO3_4_ADC_BST:
case RT5677_STO3_ADC_DIG_VOL:
case RT5677_STO4_ADC_DIG_VOL:
case RT5677_STO4_ADC_MIXER:
case RT5677_STO3_ADC_MIXER:
case RT5677_STO2_ADC_MIXER:
case RT5677_STO1_ADC_MIXER:
case RT5677_MONO_ADC_MIXER:
case RT5677_ADC_IF_DSP_DAC1_MIXER:
case RT5677_STO1_DAC_MIXER:
case RT5677_MONO_DAC_MIXER:
case RT5677_DD1_MIXER:
case RT5677_DD2_MIXER:
case RT5677_IF3_DATA:
case RT5677_IF4_DATA:
case RT5677_PDM_OUT_CTRL:
case RT5677_PDM_DATA_CTRL1:
case RT5677_PDM_DATA_CTRL2:
case RT5677_PDM1_DATA_CTRL2:
case RT5677_PDM1_DATA_CTRL3:
case RT5677_PDM1_DATA_CTRL4:
case RT5677_PDM2_DATA_CTRL2:
case RT5677_PDM2_DATA_CTRL3:
case RT5677_PDM2_DATA_CTRL4:
case RT5677_TDM1_CTRL1:
case RT5677_TDM1_CTRL2:
case RT5677_TDM1_CTRL3:
case RT5677_TDM1_CTRL4:
case RT5677_TDM1_CTRL5:
case RT5677_TDM2_CTRL1:
case RT5677_TDM2_CTRL2:
case RT5677_TDM2_CTRL3:
case RT5677_TDM2_CTRL4:
case RT5677_TDM2_CTRL5:
case RT5677_I2C_MASTER_CTRL1:
case RT5677_I2C_MASTER_CTRL2:
case RT5677_I2C_MASTER_CTRL3:
case RT5677_I2C_MASTER_CTRL4:
case RT5677_I2C_MASTER_CTRL5:
case RT5677_I2C_MASTER_CTRL6:
case RT5677_I2C_MASTER_CTRL7:
case RT5677_I2C_MASTER_CTRL8:
case RT5677_DMIC_CTRL1:
case RT5677_DMIC_CTRL2:
case RT5677_HAP_GENE_CTRL1:
case RT5677_HAP_GENE_CTRL2:
case RT5677_HAP_GENE_CTRL3:
case RT5677_HAP_GENE_CTRL4:
case RT5677_HAP_GENE_CTRL5:
case RT5677_HAP_GENE_CTRL6:
case RT5677_HAP_GENE_CTRL7:
case RT5677_HAP_GENE_CTRL8:
case RT5677_HAP_GENE_CTRL9:
case RT5677_HAP_GENE_CTRL10:
case RT5677_PWR_DIG1:
case RT5677_PWR_DIG2:
case RT5677_PWR_ANLG1:
case RT5677_PWR_ANLG2:
case RT5677_PWR_DSP1:
case RT5677_PWR_DSP_ST:
case RT5677_PWR_DSP2:
case RT5677_ADC_DAC_HPF_CTRL1:
case RT5677_PRIV_INDEX:
case RT5677_PRIV_DATA:
case RT5677_I2S4_SDP:
case RT5677_I2S1_SDP:
case RT5677_I2S2_SDP:
case RT5677_I2S3_SDP:
case RT5677_CLK_TREE_CTRL1:
case RT5677_CLK_TREE_CTRL2:
case RT5677_CLK_TREE_CTRL3:
case RT5677_PLL1_CTRL1:
case RT5677_PLL1_CTRL2:
case RT5677_PLL2_CTRL1:
case RT5677_PLL2_CTRL2:
case RT5677_GLB_CLK1:
case RT5677_GLB_CLK2:
case RT5677_ASRC_1:
case RT5677_ASRC_2:
case RT5677_ASRC_3:
case RT5677_ASRC_4:
case RT5677_ASRC_5:
case RT5677_ASRC_6:
case RT5677_ASRC_7:
case RT5677_ASRC_8:
case RT5677_ASRC_9:
case RT5677_ASRC_10:
case RT5677_ASRC_11:
case RT5677_ASRC_12:
case RT5677_ASRC_13:
case RT5677_ASRC_14:
case RT5677_ASRC_15:
case RT5677_ASRC_16:
case RT5677_ASRC_17:
case RT5677_ASRC_18:
case RT5677_ASRC_19:
case RT5677_ASRC_20:
case RT5677_ASRC_21:
case RT5677_ASRC_22:
case RT5677_ASRC_23:
case RT5677_VAD_CTRL1:
case RT5677_VAD_CTRL2:
case RT5677_VAD_CTRL3:
case RT5677_VAD_CTRL4:
case RT5677_VAD_CTRL5:
case RT5677_DSP_INB_CTRL1:
case RT5677_DSP_INB_CTRL2:
case RT5677_DSP_IN_OUTB_CTRL:
case RT5677_DSP_OUTB0_1_DIG_VOL:
case RT5677_DSP_OUTB2_3_DIG_VOL:
case RT5677_DSP_OUTB4_5_DIG_VOL:
case RT5677_DSP_OUTB6_7_DIG_VOL:
case RT5677_ADC_EQ_CTRL1:
case RT5677_ADC_EQ_CTRL2:
case RT5677_EQ_CTRL1:
case RT5677_EQ_CTRL2:
case RT5677_EQ_CTRL3:
case RT5677_SOFT_VOL_ZERO_CROSS1:
case RT5677_JD_CTRL1:
case RT5677_JD_CTRL2:
case RT5677_JD_CTRL3:
case RT5677_IRQ_CTRL1:
case RT5677_IRQ_CTRL2:
case RT5677_GPIO_ST:
case RT5677_GPIO_CTRL1:
case RT5677_GPIO_CTRL2:
case RT5677_GPIO_CTRL3:
case RT5677_STO1_ADC_HI_FILTER1:
case RT5677_STO1_ADC_HI_FILTER2:
case RT5677_MONO_ADC_HI_FILTER1:
case RT5677_MONO_ADC_HI_FILTER2:
case RT5677_STO2_ADC_HI_FILTER1:
case RT5677_STO2_ADC_HI_FILTER2:
case RT5677_STO3_ADC_HI_FILTER1:
case RT5677_STO3_ADC_HI_FILTER2:
case RT5677_STO4_ADC_HI_FILTER1:
case RT5677_STO4_ADC_HI_FILTER2:
case RT5677_MB_DRC_CTRL1:
case RT5677_DRC1_CTRL1:
case RT5677_DRC1_CTRL2:
case RT5677_DRC1_CTRL3:
case RT5677_DRC1_CTRL4:
case RT5677_DRC1_CTRL5:
case RT5677_DRC1_CTRL6:
case RT5677_DRC2_CTRL1:
case RT5677_DRC2_CTRL2:
case RT5677_DRC2_CTRL3:
case RT5677_DRC2_CTRL4:
case RT5677_DRC2_CTRL5:
case RT5677_DRC2_CTRL6:
case RT5677_DRC1_HL_CTRL1:
case RT5677_DRC1_HL_CTRL2:
case RT5677_DRC2_HL_CTRL1:
case RT5677_DRC2_HL_CTRL2:
case RT5677_DSP_INB1_SRC_CTRL1:
case RT5677_DSP_INB1_SRC_CTRL2:
case RT5677_DSP_INB1_SRC_CTRL3:
case RT5677_DSP_INB1_SRC_CTRL4:
case RT5677_DSP_INB2_SRC_CTRL1:
case RT5677_DSP_INB2_SRC_CTRL2:
case RT5677_DSP_INB2_SRC_CTRL3:
case RT5677_DSP_INB2_SRC_CTRL4:
case RT5677_DSP_INB3_SRC_CTRL1:
case RT5677_DSP_INB3_SRC_CTRL2:
case RT5677_DSP_INB3_SRC_CTRL3:
case RT5677_DSP_INB3_SRC_CTRL4:
case RT5677_DSP_OUTB1_SRC_CTRL1:
case RT5677_DSP_OUTB1_SRC_CTRL2:
case RT5677_DSP_OUTB1_SRC_CTRL3:
case RT5677_DSP_OUTB1_SRC_CTRL4:
case RT5677_DSP_OUTB2_SRC_CTRL1:
case RT5677_DSP_OUTB2_SRC_CTRL2:
case RT5677_DSP_OUTB2_SRC_CTRL3:
case RT5677_DSP_OUTB2_SRC_CTRL4:
case RT5677_DSP_OUTB_0123_MIXER_CTRL:
case RT5677_DSP_OUTB_45_MIXER_CTRL:
case RT5677_DSP_OUTB_67_MIXER_CTRL:
case RT5677_DIG_MISC:
case RT5677_GEN_CTRL1:
case RT5677_GEN_CTRL2:
case RT5677_VENDOR_ID:
case RT5677_VENDOR_ID1:
case RT5677_VENDOR_ID2:
return true;
default:
return false;
}
}
/**
* rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
* @rt5677: Private Data.
* @addr: Address index.
* @value: Address data.
* @opcode: opcode value
*
* Returns 0 for success or negative error code.
*/
static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
unsigned int addr, unsigned int value, unsigned int opcode)
{
struct snd_soc_component *component = rt5677->component;
int ret;
mutex_lock(&rt5677->dsp_cmd_lock);
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
addr >> 16);
if (ret < 0) {
dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
addr & 0xffff);
if (ret < 0) {
dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
value >> 16);
if (ret < 0) {
dev_err(component->dev, "Failed to set data msb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
value & 0xffff);
if (ret < 0) {
dev_err(component->dev, "Failed to set data lsb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
opcode);
if (ret < 0) {
dev_err(component->dev, "Failed to set op code value: %d\n", ret);
goto err;
}
err:
mutex_unlock(&rt5677->dsp_cmd_lock);
return ret;
}
/**
* rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
* @rt5677: Private Data.
* @addr: Address index.
* @value: Address data.
*
*
* Returns 0 for success or negative error code.
*/
static int rt5677_dsp_mode_i2c_read_addr(
struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
{
struct snd_soc_component *component = rt5677->component;
int ret;
unsigned int msb, lsb;
mutex_lock(&rt5677->dsp_cmd_lock);
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
addr >> 16);
if (ret < 0) {
dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
addr & 0xffff);
if (ret < 0) {
dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
goto err;
}
ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
0x0002);
if (ret < 0) {
dev_err(component->dev, "Failed to set op code value: %d\n", ret);
goto err;
}
regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
*value = (msb << 16) | lsb;
err:
mutex_unlock(&rt5677->dsp_cmd_lock);
return ret;
}
/**
* rt5677_dsp_mode_i2c_write - Write register on DSP mode.
* @rt5677: Private Data.
* @reg: Register index.
* @value: Register data.
*
*
* Returns 0 for success or negative error code.
*/
static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
unsigned int reg, unsigned int value)
{
return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
value, 0x0001);
}
/**
* rt5677_dsp_mode_i2c_read - Read register on DSP mode.
* @rt5677: Private Data
* @reg: Register index.
* @value: Register data.
*
*
* Returns 0 for success or negative error code.
*/
static int rt5677_dsp_mode_i2c_read(
struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
{
int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
value);
*value &= 0xffff;
return ret;
}
static void rt5677_set_dsp_mode(struct snd_soc_component *component, bool on)
{
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
if (on) {
regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
rt5677->is_dsp_mode = true;
} else {
regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
rt5677->is_dsp_mode = false;
}
}
static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on)
{
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
static bool activity;
int ret;
if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
return -ENXIO;
if (on && !activity) {
activity = true;
regcache_cache_only(rt5677->regmap, false);
regcache_cache_bypass(rt5677->regmap, true);
regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
regmap_update_bits(rt5677->regmap,
RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
RT5677_LDO1_SEL_MASK, 0x0);
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_LDO1, RT5677_PWR_LDO1);
switch (rt5677->type) {
case RT5677:
regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
RT5677_PLL2_PR_SRC_MASK |
RT5677_DSP_CLK_SRC_MASK,
RT5677_PLL2_PR_SRC_MCLK2 |
RT5677_DSP_CLK_SRC_BYPASS);
break;
case RT5676:
regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
RT5677_DSP_CLK_SRC_MASK,
RT5677_DSP_CLK_SRC_BYPASS);
break;
default:
break;
}
regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
rt5677_set_dsp_mode(component, true);
ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
component->dev);
if (ret == 0) {
rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
release_firmware(rt5677->fw1);
}
ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
component->dev);
if (ret == 0) {
rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
release_firmware(rt5677->fw2);
}
regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
regcache_cache_bypass(rt5677->regmap, false);
regcache_cache_only(rt5677->regmap, true);
} else if (!on && activity) {
activity = false;
regcache_cache_only(rt5677->regmap, false);
regcache_cache_bypass(rt5677->regmap, true);
regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
rt5677_set_dsp_mode(component, false);
regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
regcache_cache_bypass(rt5677->regmap, false);
regcache_mark_dirty(rt5677->regmap);
regcache_sync(rt5677->regmap);
}
return 0;
}
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const DECLARE_TLV_DB_RANGE(bst_tlv,
0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);
static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
return 0;
}
static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
rt5677_set_dsp_vad(component, rt5677->dsp_vad_en);
return 0;
}
static const struct snd_kcontrol_new rt5677_snd_controls[] = {
/* OUTPUT Control */
SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
RT5677_LOUT1_L_MUTE_SFT, 1, 1),
SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
RT5677_LOUT2_L_MUTE_SFT, 1, 1),
SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
RT5677_LOUT3_L_MUTE_SFT, 1, 1),
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
/* IN1/IN2 Control */
SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
adc_vol_tlv),
SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
adc_vol_tlv),
SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
adc_vol_tlv),
SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
adc_vol_tlv),
SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
adc_vol_tlv),
/* Sidetone Control */
SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
/* ADC Boost Volume Control */
SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
adc_bst_tlv),
SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
rt5677_dsp_vad_get, rt5677_dsp_vad_put),
};
/**
* set_dmic_clk - Set parameter of dmic.
*
* @w: DAPM widget.
* @kcontrol: The kcontrol of this widget.
* @event: Event id.
*
* Choose dmic clock between 1MHz and 3MHz.
* It is better for clock to approximate 3MHz.
*/
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
int idx, rate;
rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
idx = rl6231_calc_dmic_clk(rate);
if (idx < 0)
dev_err(component->dev, "Failed to set DMIC clock\n");
else
regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
return idx;
}
static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int val;
regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
val &= RT5677_SCLK_SRC_MASK;
if (val == RT5677_SCLK_SRC_PLL1)
return 1;
else
return 0;
}
static int is_using_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int reg, shift, val;
if (source->reg == RT5677_ASRC_1) {
switch (source->shift) {
case 12:
reg = RT5677_ASRC_4;
shift = 0;
break;
case 13:
reg = RT5677_ASRC_4;
shift = 4;
break;
case 14:
reg = RT5677_ASRC_4;
shift = 8;
break;
case 15:
reg = RT5677_ASRC_4;
shift = 12;
break;
default:
return 0;
}
} else {
switch (source->shift) {
case 0:
reg = RT5677_ASRC_6;
shift = 8;
break;
case 1:
reg = RT5677_ASRC_6;
shift = 12;
break;
case 2:
reg = RT5677_ASRC_5;
shift = 0;
break;
case 3:
reg = RT5677_ASRC_5;
shift = 4;
break;
case 4:
reg = RT5677_ASRC_5;
shift = 8;
break;
case 5:
reg = RT5677_ASRC_5;
shift = 12;
break;
case 12:
reg = RT5677_ASRC_3;
shift = 0;
break;
case 13:
reg = RT5677_ASRC_3;
shift = 4;
break;
case 14:
reg = RT5677_ASRC_3;
shift = 12;
break;
default:
return 0;
}
}
regmap_read(rt5677->regmap, reg, &val);
val = (val >> shift) & 0xf;
switch (val) {
case 1 ... 6:
return 1;
default:
return 0;
}
}
static int can_use_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
return 1;
return 0;
}
/**
* rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
* @component: SoC audio component device.
* @filter_mask: mask of filters.
* @clk_src: clock source
*
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
* ASRC function will track i2s clock and generate a corresponding system clock
* for codec. This function provides an API to select the clock source for a
* set of filters specified by the mask. And the codec driver will turn on ASRC
* for these filters if ASRC is selected as their clock source.
*/
int rt5677_sel_asrc_clk_src(struct snd_soc_component *component,
unsigned int filter_mask, unsigned int clk_src)
{
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int asrc3_mask = 0, asrc3_value = 0;
unsigned int asrc4_mask = 0, asrc4_value = 0;
unsigned int asrc5_mask = 0, asrc5_value = 0;
unsigned int asrc6_mask = 0, asrc6_value = 0;
unsigned int asrc7_mask = 0, asrc7_value = 0;
unsigned int asrc8_mask = 0, asrc8_value = 0;
switch (clk_src) {
case RT5677_CLK_SEL_SYS:
case RT5677_CLK_SEL_I2S1_ASRC:
case RT5677_CLK_SEL_I2S2_ASRC:
case RT5677_CLK_SEL_I2S3_ASRC:
case RT5677_CLK_SEL_I2S4_ASRC:
case RT5677_CLK_SEL_I2S5_ASRC:
case RT5677_CLK_SEL_I2S6_ASRC:
case RT5677_CLK_SEL_SYS2:
case RT5677_CLK_SEL_SYS3:
case RT5677_CLK_SEL_SYS4:
case RT5677_CLK_SEL_SYS5:
case RT5677_CLK_SEL_SYS6:
case RT5677_CLK_SEL_SYS7:
break;
default:
return -EINVAL;
}
/* ASRC 3 */
if (filter_mask & RT5677_DA_STEREO_FILTER) {
asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
| (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
}
if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
| (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
}
if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
| (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
}
if (asrc3_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
asrc3_value);
/* ASRC 4 */
if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
| (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
}
if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
| (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
}
if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
| (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
}
if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
| (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
}
if (asrc4_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
asrc4_value);
/* ASRC 5 */
if (filter_mask & RT5677_AD_STEREO1_FILTER) {
asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
| (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
}
if (filter_mask & RT5677_AD_STEREO2_FILTER) {
asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
| (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
}
if (filter_mask & RT5677_AD_STEREO3_FILTER) {
asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
| (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
}
if (filter_mask & RT5677_AD_STEREO4_FILTER) {
asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
| (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
}
if (asrc5_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
asrc5_value);
/* ASRC 6 */
if (filter_mask & RT5677_AD_MONO_L_FILTER) {
asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
| (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
}
if (filter_mask & RT5677_AD_MONO_R_FILTER) {
asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
| (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
}
if (asrc6_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
asrc6_value);
/* ASRC 7 */
if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
| (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
}
if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
| (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
}
if (asrc7_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
asrc7_value);
/* ASRC 8 */
if (filter_mask & RT5677_I2S1_SOURCE) {
asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
| ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
}
if (filter_mask & RT5677_I2S2_SOURCE) {
asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
| ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
}
if (filter_mask & RT5677_I2S3_SOURCE) {
asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
| ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
}
if (filter_mask & RT5677_I2S4_SOURCE) {
asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
| ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
}
if (asrc8_mask)
regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
asrc8_value);
return 0;
}
EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
struct snd_soc_dapm_widget *sink)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int asrc_setting;
switch (source->shift) {
case 11:
regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
RT5677_AD_STO1_CLK_SEL_SFT;
break;
case 10:
regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
RT5677_AD_STO2_CLK_SEL_SFT;
break;
case 9:
regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
RT5677_AD_STO3_CLK_SEL_SFT;
break;
case 8:
regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
RT5677_AD_STO4_CLK_SEL_SFT;
break;
case 7:
regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
RT5677_AD_MONOL_CLK_SEL_SFT;
break;
case 6:
regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
RT5677_AD_MONOR_CLK_SEL_SFT;
break;
default:
return 0;
}
if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
return 1;
return 0;
}
/* Digital Mixer */
static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
RT5677_M_STO1_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
RT5677_M_STO1_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
RT5677_M_STO1_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
RT5677_M_STO1_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
RT5677_M_STO2_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
RT5677_M_STO2_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
RT5677_M_STO2_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
RT5677_M_STO2_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
RT5677_M_STO3_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
RT5677_M_STO3_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
RT5677_M_STO3_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
RT5677_M_STO3_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
RT5677_M_STO4_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
RT5677_M_STO4_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
RT5677_M_STO4_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
RT5677_M_STO4_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
RT5677_M_MONO_ADC_L1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
RT5677_M_MONO_ADC_L2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
RT5677_M_MONO_ADC_R1_SFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
RT5677_M_MONO_ADC_R2_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
RT5677_M_DAC1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
RT5677_M_DAC1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_ST_DAC1_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_ST_DAC1_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_ST_DAC2_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_ST_DAC2_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
RT5677_M_STO_L_DD1_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
RT5677_M_STO_R_DD1_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
RT5677_M_STO_L_DD2_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
RT5677_M_STO_R_DD2_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_01_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_23_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_45_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_6_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_7_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_8_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_9_H_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_01_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_23_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_45_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_6_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_7_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_8_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
RT5677_DSP_IB_9_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_01_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_23_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_45_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_6_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_7_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_8_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_9_H_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_01_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_23_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_45_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_6_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_7_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_8_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
RT5677_DSP_IB_9_L_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_01_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_23_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_45_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_6_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_7_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_8_H_SFT, 1, 1),
SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_9_H_SFT, 1, 1),
};
static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_01_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_23_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_45_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_6_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_7_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_8_L_SFT, 1, 1),
SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
RT5677_DSP_IB_9_L_SFT, 1, 1),
};
/* Mux */
/* DAC1 L/R Source */ /* MX-29 [10:8] */
static const char * const rt5677_dac1_src[] = {
"IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
"OB 01"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
static const struct snd_kcontrol_new rt5677_dac1_mux =
SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
/* ADDA1 L/R Source */ /* MX-29 [1:0] */
static const char * const rt5677_adda1_src[] = {
"STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
};
static SOC_ENUM_SINGLE_DECL(
rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
static const struct snd_kcontrol_new rt5677_adda1_mux =
SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
static const char * const rt5677_dac2l_src[] = {
"IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
"OB 2",
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
static const struct snd_kcontrol_new rt5677_dac2_l_mux =
SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
static const char * const rt5677_dac2r_src[] = {
"IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
"OB 3", "Haptic Generator", "VAD ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
static const struct snd_kcontrol_new rt5677_dac2_r_mux =
SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
static const char * const rt5677_dac3l_src[] = {
"IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
"SLB DAC 4", "OB 4"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
static const struct snd_kcontrol_new rt5677_dac3_l_mux =
SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
static const char * const rt5677_dac3r_src[] = {
"IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
"SLB DAC 5", "OB 5"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
static const struct snd_kcontrol_new rt5677_dac3_r_mux =
SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
static const char * const rt5677_dac4l_src[] = {
"IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
"SLB DAC 6", "OB 6"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
static const struct snd_kcontrol_new rt5677_dac4_l_mux =
SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
static const char * const rt5677_dac4r_src[] = {
"IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
"SLB DAC 7", "OB 7"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
static const struct snd_kcontrol_new rt5677_dac4_r_mux =
SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
static const char * const rt5677_iob_bypass_src[] = {
"Bypass", "Pass SRC"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
static const char * const rt5677_stereo_adc2_src[] = {
"DD MIX1", "DMIC", "Stereo DAC MIX"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
static const char * const rt5677_dmic_src[] = {
"DMIC1", "DMIC2", "DMIC3", "DMIC4"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
/* Stereo2 ADC Source */ /* MX-26 [0] */
static const char * const rt5677_stereo2_adc_lr_src[] = {
"L", "LR"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
static const char * const rt5677_stereo_adc1_src[] = {
"DD MIX1", "ADC1/2", "Stereo DAC MIX"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
static const char * const rt5677_mono_adc2_l_src[] = {
"DD MIX1L", "DMIC", "MONO DAC MIXL"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
/* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
static const char * const rt5677_mono_adc1_l_src[] = {
"DD MIX1L", "ADC1", "MONO DAC MIXL"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
/* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
static const char * const rt5677_mono_adc2_r_src[] = {
"DD MIX1R", "DMIC", "MONO DAC MIXR"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
/* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
static const char * const rt5677_mono_adc1_r_src[] = {
"DD MIX1R", "ADC2", "MONO DAC MIXR"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
static const char * const rt5677_stereo4_adc2_src[] = {
"DD MIX1", "DMIC", "DD MIX2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
static const char * const rt5677_stereo4_adc1_src[] = {
"DD MIX1", "ADC1/2", "DD MIX2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
/* InBound0/1 Source */ /* MX-A3 [14:12] */
static const char * const rt5677_inbound01_src[] = {
"IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
"VAD ADC/DAC1 FS"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
static const struct snd_kcontrol_new rt5677_ib01_src_mux =
SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
/* InBound2/3 Source */ /* MX-A3 [10:8] */
static const char * const rt5677_inbound23_src[] = {
"IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
"DAC1 FS", "IF4 DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
static const struct snd_kcontrol_new rt5677_ib23_src_mux =
SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
/* InBound4/5 Source */ /* MX-A3 [6:4] */
static const char * const rt5677_inbound45_src[] = {
"IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
"IF3 DAC"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
static const struct snd_kcontrol_new rt5677_ib45_src_mux =
SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
/* InBound6 Source */ /* MX-A3 [2:0] */
static const char * const rt5677_inbound6_src[] = {
"IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
"IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
static const struct snd_kcontrol_new rt5677_ib6_src_mux =
SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
/* InBound7 Source */ /* MX-A4 [14:12] */
static const char * const rt5677_inbound7_src[] = {
"IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
"IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
static const struct snd_kcontrol_new rt5677_ib7_src_mux =
SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
/* InBound8 Source */ /* MX-A4 [10:8] */
static const char * const rt5677_inbound8_src[] = {
"STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
"MONO ADC MIX L", "DACL1 FS"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
static const struct snd_kcontrol_new rt5677_ib8_src_mux =
SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
/* InBound9 Source */ /* MX-A4 [6:4] */
static const char * const rt5677_inbound9_src[] = {
"STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
"MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
static const struct snd_kcontrol_new rt5677_ib9_src_mux =
SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
/* VAD Source */ /* MX-9F [6:4] */
static const char * const rt5677_vad_src[] = {
"STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
"STO3 ADC MIX L"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_vad_enum, RT5677_VAD_CTRL4,
RT5677_VAD_SRC_SFT, rt5677_vad_src);
static const struct snd_kcontrol_new rt5677_vad_src_mux =
SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
/* Sidetone Source */ /* MX-13 [11:9] */
static const char * const rt5677_sidetone_src[] = {
"DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
RT5677_ST_SEL_SFT, rt5677_sidetone_src);
static const struct snd_kcontrol_new rt5677_sidetone_mux =
SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
/* DAC1/2 Source */ /* MX-15 [1:0] */
static const char * const rt5677_dac12_src[] = {
"STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
static const struct snd_kcontrol_new rt5677_dac12_mux =
SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
/* DAC3 Source */ /* MX-15 [5:4] */
static const char * const rt5677_dac3_src[] = {
"MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
static const struct snd_kcontrol_new rt5677_dac3_mux =
SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
/* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
static const char * const rt5677_pdm_src[] = {
"STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
static const char * const rt5677_if12_adc1_src[] = {
"STO1 ADC MIX", "OB01", "VAD ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
static const char * const rt5677_if12_adc2_src[] = {
"STO2 ADC MIX", "OB23"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
static const char * const rt5677_if12_adc3_src[] = {
"STO3 ADC MIX", "MONO ADC MIX", "OB45"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
static const char * const rt5677_if12_adc4_src[] = {
"STO4 ADC MIX", "OB67", "OB01"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
static const char * const rt5677_if34_adc_src[] = {
"STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
"MONO ADC MIX", "OB01", "OB23", "VAD ADC"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if3_adc_enum, RT5677_IF3_DATA,
RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
static const struct snd_kcontrol_new rt5677_if3_adc_mux =
SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if4_adc_enum, RT5677_IF4_DATA,
RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
static const struct snd_kcontrol_new rt5677_if4_adc_mux =
SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
/* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
static const char * const rt5677_if12_adc_swap_src[] = {
"L/R", "R/L", "L/L", "R/R"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
/* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
static const char * const rt5677_if1_adc_tdm_swap_src[] = {
"1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
"3/1/2/4", "3/4/1/2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
/* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
static const char * const rt5677_if2_adc_tdm_swap_src[] = {
"1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
"2/3/1/4", "3/4/1/2"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
/* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
MX-3F[14:12][10:8][6:4][2:0]
MX-43[14:12][10:8][6:4][2:0]
MX-44[14:12][10:8][6:4][2:0] */
static const char * const rt5677_if12_dac_tdm_sel_src[] = {
"Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
};
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
static SOC_ENUM_SINGLE_DECL(
rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_BST1_P, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_BST2_P, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
break;
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
break;
default:
return 0;
}
return 0;
}
static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
break;
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
break;
default:
return 0;
}
return 0;
}
static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
RT5677_PWR_CLK_MB, 0);
break;
default:
return 0;
}
return 0;
}
static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int value;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
if (value & RT5677_IF1_ADC_CTRL_MASK)
regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
RT5677_IF1_ADC_MODE_MASK,
RT5677_IF1_ADC_MODE_TDM);
break;
default:
return 0;
}
return 0;
}
static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
unsigned int value;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
if (value & RT5677_IF2_ADC_CTRL_MASK)
regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
RT5677_IF2_ADC_MODE_MASK,
RT5677_IF2_ADC_MODE_TDM);
break;
default:
return 0;
}
return 0;
}
static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON &&
!rt5677->is_vref_slow) {
mdelay(20);
regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
RT5677_PWR_FV1 | RT5677_PWR_FV2,
RT5677_PWR_FV1 | RT5677_PWR_FV2);
rt5677->is_vref_slow = true;
}
break;
default:
return 0;
}
return 0;
}
static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
switch (event) {
case SND_SOC_DAPM_POST_PMU:
msleep(50);
break;
default:
return 0;
}
return 0;
}
static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
SND_SOC_DAPM_POST_PMU),
/* ASRC */
SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
0),
SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
0),
/* Input Side */
/* micbias */
SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
/* Input Lines */
SND_SOC_DAPM_INPUT("DMIC L1"),
SND_SOC_DAPM_INPUT("DMIC R1"),
SND_SOC_DAPM_INPUT("DMIC L2"),
SND_SOC_DAPM_INPUT("DMIC R2"),
SND_SOC_DAPM_INPUT("DMIC L3"),
SND_SOC_DAPM_INPUT("DMIC R3"),
SND_SOC_DAPM_INPUT("DMIC L4"),
SND_SOC_DAPM_INPUT("DMIC R4"),
SND_SOC_DAPM_INPUT("IN1P"),
SND_SOC_DAPM_INPUT("IN1N"),
SND_SOC_DAPM_INPUT("IN2P"),
SND_SOC_DAPM_INPUT("IN2N"),
SND_SOC_DAPM_INPUT("Haptic Generator"),
SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
/* Boost */
SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
/* ADCs */
SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
0, 0),
SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
0, 0),
SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),