)]}'
{
  "commit": "ea0bdf2b945e91137cc465d3833aeb659ba93d79",
  "tree": "607026e4d1e8adae55d275ba903b30daf9ada0fd",
  "parents": [
    "2953fb65481b262514ac13f24ffbc70eeace68c6",
    "a4bbb493a3247ef32f6191fd8b2a0657139f8e08"
  ],
  "author": {
    "name": "Linus Torvalds",
    "email": "torvalds@linux-foundation.org",
    "time": "Sat Oct 18 08:22:07 2025 -1000"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@linux-foundation.org",
    "time": "Sat Oct 18 08:22:07 2025 -1000"
  },
  "message": "Merge tag \u0027cxl-fixes-6.18-rc2\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl\n\nPull Compute Express Link fixes from Dave Jiang:\n \"A small collection of CXL fixes. In addition to some misc fixes for\n  the CXL subsystem, a number of fixes for CXL extended linear cache\n  support are included to make it functional again.\n\n   - Avoid missing port component registers setup due to dport\n     enumeration failure\n\n   - Add check for no entries in cxl_feature_info to address accessing\n     invalid pointer.\n\n   - Use %pa printk format to emit resource_size_t in\n     validate_region_offset()\n\n  CXL extended linear cache support fixes:\n\n   - Fix setup of memory resource in cxl_acpi_set_cache_size()\n\n   - Set range param for region_res_match_cxl_range() as const\n     (addresses a compile warning for match_region_by_range() fix)\n\n   - Fix match_region_by_range() to use region_res_match_cxl_range()\n\n   - Subtract to find an hpa_alias0 in cxl_poison events to correct the\n     alias math calculation\"\n\n* tag \u0027cxl-fixes-6.18-rc2\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl:\n  cxl/trace: Subtract to find an hpa_alias0 in cxl_poison events\n  cxl/region: Use %pa printk format to emit resource_size_t\n  cxl: Fix match_region_by_range() to use region_res_match_cxl_range()\n  cxl: Set range param for region_res_match_cxl_range() as const\n  cxl/acpi: Fix setup of memory resource in cxl_acpi_set_cache_size()\n  cxl/features: Add check for no entries in cxl_feature_info\n  cxl/port: Avoid missing port component registers setup\n",
  "tree_diff": []
}