)]}' { "log": [ { "commit": "5fee33d97a7f2e95716417bd164f2f5264acd976", "tree": "165f1dc522f40c7f37d9fed30d4007b853d39cb9", "parents": [ "fd87be1dada5672f877e03c2ca8504458292c479", "03555199b63aa1fbce24d16287e141c33f572a24" ], "author": { "name": "Richard Henderson", "email": "richard.henderson@linaro.org", "time": "Mon Apr 29 14:34:25 2024 -0700" }, "committer": { "name": "Richard Henderson", "email": "richard.henderson@linaro.org", "time": "Mon Apr 29 14:34:25 2024 -0700" }, "message": "Merge tag \u0027samuel-thibault\u0027 of https://people.debian.org/~sthibault/qemu into staging\n\nslirp: Use newer slirp_*_hostxfwd API\n\nNicholas Ngai (1):\n net/slirp: Use newer slirp_*_hostxfwd API\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQIzBAABCgAdFiEEqpLrvfAUiqYaQ7iu5IlMrEVBS7AFAmYu5OgACgkQ5IlMrEVB\n# S7DGOQ//cnW2fiXnj+ijmQ4+h8Yj2vCtGZ9+7D74Q6KSbY0AkYVhRm+qWJA1XJrR\n# Y7JvetqKGCxhol24x0aopDvcybIDU/EqFrxhmZY+dJhZWxfsvYpLGJ5TfulRA1gy\n# PSDYQi6LlwDJyQT08po2TLA0zSOmxycdrA8mTJuf8UHDiXnwcy9WjDFF1tCrGoN4\n# LgvsUUpQ6y9fZQxbFyPFwtHkUeREvfhRPT0c5lNsF0Cot8uXt5YOyCc0XKjX1d0F\n# ucuCwv65gsIdcaDHcHIYhyKZX3lfAXAAaDe9njvISYcyOlyXOZS9df3tuMTeEW8S\n# wuN10WuQHI7mpLS/IomnmYxb16lyhhwLC9kmNVZt6jGfTYB/xHUeXb9gIsdkc05s\n# Cxy+VdxgnzGji6dOwufI8/ufWSti1PRB1yhZsmJtLC7MDOv5EJkxrmRXhWkr6LYZ\n# CU52uT7CsOTKdmmwdjTUqkfswB70Js68J33Rbm3VWJlnSBAQ/ioGt50r7tqFBwT8\n# HQc4CqYBT58BPb7rKrUa6dCy1uAprYl2juU3vl/nHcp2zIxIar1yzQK3OG+3h6fZ\n# Mrg/C5l4WiEKFgdl5sMj1xJK15aC42/UyzxUFM12usKaOtKjQAIkjx6U7HCjwfdR\n# BZmxTx2u7jGm9a0R3qhVhZjmIIbfLoeEHepLMOAHN+TGAl0bcxc\u003d\n# \u003d22cZ\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Sun 28 Apr 2024 05:08:08 PM PDT\n# gpg: using RSA key AA92EBBDF0148AA61A43B8AEE4894CAC45414BB0\n# gpg: Good signature from \"Samuel Thibault \u003csamuel.thibault@ens-lyon.org\u003e\" [undefined]\n# gpg: aka \"Samuel Thibault \u003csthibault@debian.org\u003e\" [undefined]\n# gpg: aka \"Samuel Thibault \u003csamuel.thibault@gnu.org\u003e\" [unknown]\n# gpg: aka \"Samuel Thibault \u003csamuel.thibault@inria.fr\u003e\" [undefined]\n# gpg: aka \"Samuel Thibault \u003csamuel.thibault@labri.fr\u003e\" [undefined]\n# gpg: aka \"Samuel Thibault \u003csamuel.thibault@aquilenet.fr\u003e\" [unknown]\n# gpg: aka \"Samuel Thibault \u003csamuel.thibault@u-bordeaux.fr\u003e\" [unknown]\n# gpg: aka \"Samuel Thibault \u003csthibault@hypra.fr\u003e\" [unknown]\n# gpg: WARNING: This key is not certified with a trusted signature!\n# gpg: There is no indication that the signature belongs to the owner.\n# Primary key fingerprint: 900C B024 B679 31D4 0F82 304B D017 8C76 7D06 9EE6\n# Subkey fingerprint: AA92 EBBD F014 8AA6 1A43 B8AE E489 4CAC 4541 4BB0\n\n* tag \u0027samuel-thibault\u0027 of https://people.debian.org/~sthibault/qemu:\n net/slirp: Use newer slirp_*_hostxfwd API\n\nSigned-off-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "03555199b63aa1fbce24d16287e141c33f572a24", "tree": "165f1dc522f40c7f37d9fed30d4007b853d39cb9", "parents": [ "fd87be1dada5672f877e03c2ca8504458292c479" ], "author": { "name": "Nicholas Ngai", "email": "nicholas@ngai.me", "time": "Sat Sep 25 14:48:20 2021 -0700" }, "committer": { "name": "Samuel Thibault", "email": "samuel.thibault@ens-lyon.org", "time": "Mon Apr 29 02:04:58 2024 +0200" }, "message": "net/slirp: Use newer slirp_*_hostxfwd API\n\nlibslirp provides a newer slirp_*_hostxfwd API meant for\naddress-agnostic forwarding instead of the is_udp parameter which is\nlimited to just TCP/UDP.\n\nThis paves the way for IPv6 and Unix socket support.\n\nSigned-off-by: Nicholas Ngai \u003cnicholas@ngai.me\u003e\nSigned-off-by: Samuel Thibault \u003csamuel.thibault@ens-lyon.org\u003e\nTested-by: Breno Leitao \u003cleitao@debian.org\u003e\nMessage-Id: \u003c20210925214820.18078-1-nicholas@ngai.me\u003e\n" }, { "commit": "fd87be1dada5672f877e03c2ca8504458292c479", "tree": "0d16a4a1b07aa48ad251a83c37b5baf902da70a9", "parents": [ "77bcaf5f222fb19667738dc2ca7dec6172d69db7", "671558d290ffb93752d3245e7c5604b04b6dcdf2" ], "author": { "name": "Richard Henderson", "email": "richard.henderson@linaro.org", "time": "Fri Apr 26 15:28:13 2024 -0700" }, "committer": { "name": "Richard Henderson", "email": "richard.henderson@linaro.org", "time": "Fri Apr 26 15:28:13 2024 -0700" }, "message": "Merge tag \u0027accel-20240426\u0027 of https://github.com/philmd/qemu into staging\n\nAccelerators patches\n\nA lot of trivial cleanups and simplifications (moving methods around,\nadding/removing #include statements). Most notable changes:\n\n- Rename NEED_CPU_H -\u003e COMPILING_PER_TARGET\n- Rename few template headers using the \u0027.h.inc\u0027 suffix\n- Extract some definitions / declarations into their own header:\n - accel/tcg/user-retaddr.h (helper_retaddr)\n - include/exec/abi_ptr.h (abi_ptr)\n - include/exec/breakpoint.h (CPUBreakpoint, CPUWatchpoint)\n - include/exec/mmu-access-type.h (MMUAccessType)\n - include/user/tswap-target.h (tswapl, bswaptls)\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmYsAuEACgkQ4+MsLN6t\n# wN78Rg//V9UoE0U9Lh6Sd2WpcSAYP9D1CBa+iGXhrmel0utER1sQLu022nvcLdHc\n# XtCgtX3H0yECF8dPX02rVp8IbSlOv3c8N/a6BxD79cRGqgXBYR/dEUqfXqeLJn3l\n# a58YU3i7sLNQ0l7VnwTiBnI0lw170/xJl2B2mcR1SvWuH3dr5vTeIXNureu36ORo\n# rc0oqWHbw1Pyyn8ADE2kPyFCOiwPwvcOvAk8dXGfib+mNCwNVV+ZUtAPi711VD8d\n# 9VW2gu2sXwnWdpROrSugSw+aPVF4UjltL9qJEl5bxoqWFmlET1Zn2NpKvsocUXmh\n# CMQQS2Tr4LpaaVQJGxx0yUe0B65X5+gCkIhsMOubED7GRyTCjrkOPm6exz3ge6WV\n# YmIboggFAk3OjAzLs7yZVkWsTK1Y3+3eX0u7AWPUsUu7rCT/Toc6QxDS7eT2hJfq\n# UDXI355PGbImgiArQa+OsT7v1Le4/iQa+TfN4fdUDpxEdfaxhnijWh+E91CEp+w/\n# Mq7db9Z1aMnhFKIKdkPYyfwB74yXQrmYchJ0QojZjbzqNGwkt9VeC7O9RcYjEaHM\n# hMIexwccxexqGH22wn8vPd6ZVKtiLaG4AXO0v6Dn2YJ7/zb/ntcI6lRZqdBAHKNK\n# MzkjTRRRR0wAfu8Lk8CaNNEqUP4Po43fbYymo6AZhIR8NqfApL0\u003d\n# \u003difBx\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Fri 26 Apr 2024 12:39:13 PM PDT\n# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE\n# gpg: Good signature from \"Philippe Mathieu-Daudé (F4BUG) \u003cf4bug@amsat.org\u003e\" [full]\n\n* tag \u0027accel-20240426\u0027 of https://github.com/philmd/qemu: (38 commits)\n plugins: Include missing \u0027qemu/bitmap.h\u0027 header\n hw/core: Avoid including the full \u0027hw/core/cpu.h\u0027 in \u0027tcg-cpu-ops.h\u0027\n exec: Move CPUTLBEntry helpers to cputlb.c\n exec: Restrict inclusion of \u0027user/guest-base.h\u0027\n exec: Rename \u0027exec/user/guest-base.h\u0027 as \u0027user/guest-base.h\u0027\n exec: Restrict \u0027cpu_ldst.h\u0027 to TCG accelerator\n exec: Restrict TCG specific declarations of \u0027cputlb.h\u0027\n exec: Declare CPUBreakpoint/CPUWatchpoint type in \u0027breakpoint.h\u0027 header\n exec: Declare MMUAccessType type in \u0027mmu-access-type.h\u0027 header\n exec: Declare abi_ptr type in its own \u0027abi_ptr.h\u0027 header\n exec/user: Do not include \u0027cpu.h\u0027 in \u0027abitypes.h\u0027\n exec: Move [b]tswapl() declarations to \u0027exec/user/tswap-target.h\u0027\n exec: Declare target_words_bigendian() in \u0027exec/tswap.h\u0027\n exec/cpu-all: Remove unused tswapls() definitions\n exec/cpu-all: Remove unused \u0027qemu/thread.h\u0027 header\n exec/cpu-all: Reduce \u0027qemu/rcu.h\u0027 header inclusion\n accel/hvf: Use accel-specific per-vcpu @dirty field\n accel/nvmm: Use accel-specific per-vcpu @dirty field\n accel/whpx: Use accel-specific per-vcpu @dirty field\n accel/tcg: Rename helper-head.h -\u003e helper-head.h.inc\n ...\n\nSigned-off-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "671558d290ffb93752d3245e7c5604b04b6dcdf2", "tree": "41da6f1e626ca4b85b233522bae024ad58b11432", "parents": [ "76d07d321fad2e05f8a86243724f91577c5f94c6" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 18 16:32:01 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 21:36:19 2024 +0200" }, "message": "plugins: Include missing \u0027qemu/bitmap.h\u0027 header\n\nSince commit c006147122 (\"plugins: create CPUPluginState and\nmigrate plugin_mask\") \"qemu/plugin.h\" uses DECLARE_BITMAP(),\nwhich is declared in \"qemu/bitmap.h\".\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Pierrick Bouvier \u003cpierrick.bouvier@linaro.org\u003e\nMessage-Id: \u003c20240418192525.97451-19-philmd@linaro.org\u003e\n" }, { "commit": "77bcaf5f222fb19667738dc2ca7dec6172d69db7", "tree": "364214a6cc3fea5fc3e231629433647744a855b5", "parents": [ "a118c4aff4087eafb68f7132b233ad548cf16376", "4fa333e08dd96395a99ea8dd9e4c73a29dd23344" ], "author": { "name": "Richard Henderson", "email": "richard.henderson@linaro.org", "time": "Fri Apr 26 08:16:50 2024 -0700" }, "committer": { "name": "Richard Henderson", "email": "richard.henderson@linaro.org", "time": "Fri Apr 26 08:16:50 2024 -0700" }, "message": "Merge tag \u0027pull-nbd-2024-04-25\u0027 of https://repo.or.cz/qemu/ericb into staging\n\nNBD patches for 2024-04-25\n\n- Avoid calling poll() within coroutine\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQEzBAABCAAdFiEEccLMIrHEYCkn0vOqp6FrSiUnQ2oFAmYqzkMACgkQp6FrSiUn\n# Q2ol3wf9HbwiYkyHhqybb4ykEs75N8B2JPbOj6gYRSBn7rz90k1vElDCM2yQhlDN\n# Ltuh8lTOaJb+Z4n2dKIF2m5hL2GTm/xtErIIpP7o6A+11mHW9ag/VLaAMdWJxmUr\n# WEUIH6mVtuRcxTTCp01l/JAYpUxOoQs1fyQljONH5kg1MAZpTTD61/cuhrXlvPLU\n# cVlrLfob90oYhydCq5o6ucW3GhaEYkaZzHIWFy7LphFySebMmnbnPhYf/JD6RZPL\n# s5K7njMK1DOyguCLlOzSuRM4gIbYunnr0Ofr/orTlAUZvbhRGKUlH0RTMWVMzgek\n# xArnEZYlsqF2wIvrz0GwMDL7BMmG7A\u003d\u003d\n# \u003dvXJj\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Thu 25 Apr 2024 02:42:27 PM PDT\n# gpg: using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A\n# gpg: Good signature from \"Eric Blake \u003ceblake@redhat.com\u003e\" [full]\n# gpg: aka \"Eric Blake (Free Software Programmer) \u003cebb9@byu.net\u003e\" [full]\n# gpg: aka \"[jpeg image of size 6874]\" [full]\n\n* tag \u0027pull-nbd-2024-04-25\u0027 of https://repo.or.cz/qemu/ericb:\n nbd/server: Mark negotiation functions as coroutine_fn\n nbd/server: do not poll within a coroutine context\n\nSigned-off-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "76d07d321fad2e05f8a86243724f91577c5f94c6", "tree": "305a0f7763d35c0382393236ca155e2a48024d8f", "parents": [ "aacfd8bbaf99444f84b408e6b052651fb8056c41" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Mar 26 18:38:02 2024 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "hw/core: Avoid including the full \u0027hw/core/cpu.h\u0027 in \u0027tcg-cpu-ops.h\u0027\n\nOnly include what is required, avoiding the full\nCPUState API from the huge \"hw/core/cpu.h\" header.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240418192525.97451-4-philmd@linaro.org\u003e\n" }, { "commit": "aacfd8bbaf99444f84b408e6b052651fb8056c41", "tree": "428e588b6a5244052766f53e876e88cf874fb76f", "parents": [ "16aa8eaaace3f8eb2d14521705fdccab518388a3" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Wed Apr 03 14:13:18 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec: Move CPUTLBEntry helpers to cputlb.c\n\nThe following CPUTLBEntry helpers are only used in accel/tcg/cputlb.c:\n - tlb_index()\n - tlb_entry()\n - tlb_read_idx()\n - tlb_addr_write()\n\nMove them to this file, allowing to remove the huge \"cpu.h\" header\ninclusion from \"exec/cpu_ldst.h\".\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240418192525.97451-13-philmd@linaro.org\u003e\n" }, { "commit": "16aa8eaaace3f8eb2d14521705fdccab518388a3", "tree": "b208ad5804bffbe1acadb0673edada801a23c506", "parents": [ "d3cbde7402fa44b1be898df0e13257e6fc399974" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Mon Dec 11 21:51:26 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec: Restrict inclusion of \u0027user/guest-base.h\u0027\n\nDeclare \u0027have_guest_base\u0027 in \"user/guest-base.h\".\n\nVery few files require this header, so explicitly include\nit there instead of \"exec/cpu-all.h\" which is used in many\nsource files.\n\nAssert this user-specific header is only included from user\nemulation.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20231211212003.21686-23-philmd@linaro.org\u003e\nReviewed-by: Anton Johansson \u003canjo@rev.ng\u003e\n" }, { "commit": "d3cbde7402fa44b1be898df0e13257e6fc399974", "tree": "e0ca80a290b43f03d26b625b2e354e963e77bac8", "parents": [ "1ce871a3e7dd3913752966064c406c08193aa992" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Mar 26 12:27:29 2024 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec: Rename \u0027exec/user/guest-base.h\u0027 as \u0027user/guest-base.h\u0027\n\nThe include/user/ directory contains the user-emulation\nspecific headers. Move guest-base.h there too.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Anton Johansson \u003canjo@rev.ng\u003e\nMessage-Id: \u003c20240418192525.97451-15-philmd@linaro.org\u003e\n" }, { "commit": "1ce871a3e7dd3913752966064c406c08193aa992", "tree": "9adafae7bed175e62614bfde9253663268bd2baa", "parents": [ "43bc8a6f1a5aa69b815548ab79ec2ff38812135e" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Wed Apr 03 13:55:51 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec: Restrict \u0027cpu_ldst.h\u0027 to TCG accelerator\n\n\"exec/cpu_ldst.h\" is specific to TCG, do not allow its\ninclusion from other accelerators.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240418192525.97451-6-philmd@linaro.org\u003e\n" }, { "commit": "43bc8a6f1a5aa69b815548ab79ec2ff38812135e", "tree": "fc0a943dabe70c31b279c8a3ccec329a8d8f556d", "parents": [ "6ce1c9d08554c70da6ca7262b00361d8bdc1705b" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Wed Apr 03 12:32:14 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec: Restrict TCG specific declarations of \u0027cputlb.h\u0027\n\nAvoid TCG specific declarations being used from non-TCG accelerators.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240418192525.97451-5-philmd@linaro.org\u003e\n" }, { "commit": "6ce1c9d08554c70da6ca7262b00361d8bdc1705b", "tree": "85c01501363a29f5ee3cc50e841c8a3f65d01b98", "parents": [ "9c1283dd76a4c21e1dd9d6a268f5d7383bbde77f" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Mar 26 18:37:25 2024 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec: Declare CPUBreakpoint/CPUWatchpoint type in \u0027breakpoint.h\u0027 header\n\nThe CPUBreakpoint and CPUWatchpoint structures are declared\nin \"hw/core/cpu.h\", which contains declarations related to\nCPUState and CPUClass. Some source files only require the\nBP/WP definitions and don\u0027t need to pull in all CPU* API.\nIn order to simplify, create a new \"exec/breakpoint.h\" header.\n\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Anton Johansson \u003canjo@rev.ng\u003e\nMessage-Id: \u003c20240418192525.97451-3-philmd@linaro.org\u003e\n" }, { "commit": "9c1283dd76a4c21e1dd9d6a268f5d7383bbde77f", "tree": "874cfd680167a4ff86a572a5d04cb38df1984b09", "parents": [ "471558cb6e1dcda005a61f66516684262864fc9f" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Mar 26 18:27:31 2024 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec: Declare MMUAccessType type in \u0027mmu-access-type.h\u0027 header\n\nThe MMUAccessType enum is declared in \"hw/core/cpu.h\".\n\"hw/core/cpu.h\" contains declarations related to CPUState\nand CPUClass. Some source files only require MMUAccessType\nand don\u0027t need to pull in all CPU* declarations. In order\nto simplify, create a new \"exec/mmu-access-type.h\" header.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240418192525.97451-2-philmd@linaro.org\u003e\n" }, { "commit": "471558cb6e1dcda005a61f66516684262864fc9f", "tree": "a48eee30cc7aaea570225cc08d6a0d6c51efc521", "parents": [ "d25ddb3f543dda8189b19dafd0b9a972c331fade" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Dec 05 14:20:34 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec: Declare abi_ptr type in its own \u0027abi_ptr.h\u0027 header\n\nThe abi_ptr type is declared in \"exec/cpu_ldst.h\" with all\nthe load/store helpers. Some source files requiring abi_ptr\ntype don\u0027t need the load/store helpers. In order to simplify,\ncreate a new \"exec/abi_ptr.h\" header.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20231212123401.37493-21-philmd@linaro.org\u003e\n" }, { "commit": "d25ddb3f543dda8189b19dafd0b9a972c331fade", "tree": "5d4c940361efc903b4c1c64390747b5cfc2496f5", "parents": [ "827238668e7dc44e43e71a3e12b605881fe6887e" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Dec 05 22:45:37 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec/user: Do not include \u0027cpu.h\u0027 in \u0027abitypes.h\u0027\n\n\"exec/user/abitypes.h\" requires:\n\n - \"exec/cpu-defs.h\" (TARGET_LONG_BITS)\n - \"exec/tswap.h\" (tswap32)\n\nIn order to avoid \"cpu.h\", pick the minimum required headers.\n\nAssert this user-specific header is only included from user\nemulation.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Thomas Huth \u003cthuth@redhat.com\u003e\nMessage-Id: \u003c20231212123401.37493-20-philmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "827238668e7dc44e43e71a3e12b605881fe6887e", "tree": "f0311bc47207fc93bfa8df8176afe947570ffa99", "parents": [ "425082612c012843d8b33fa0d35966adf5600c47" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Dec 12 11:27:18 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec: Move [b]tswapl() declarations to \u0027exec/user/tswap-target.h\u0027\n\ntswapl() and bswaptls() are target-dependent and only used\nby user emulation. Move their definitions to a new header:\n\"exec/user/tswap-target.h\".\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Anton Johansson \u003canjo@rev.ng\u003e\nMessage-Id: \u003c20231212123401.37493-17-philmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "425082612c012843d8b33fa0d35966adf5600c47", "tree": "f4998d44fed185a83d0a067e63cf60dfdf424df0", "parents": [ "77166c4568eb7cbd81afeecf4975c607b734f1f0" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Dec 12 11:34:25 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec: Declare target_words_bigendian() in \u0027exec/tswap.h\u0027\n\nWe usually check target endianess before swapping values,\nso target_words_bigendian() declaration makes sense in\n\"exec/tswap.h\" with the target swapping helpers.\n\nRemove \"hw/core/cpu.h\" when it was only included to get\nthe target_words_bigendian() declaration.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Anton Johansson \u003canjo@rev.ng\u003e\nMessage-Id: \u003c20231212123401.37493-16-philmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "77166c4568eb7cbd81afeecf4975c607b734f1f0", "tree": "5aceafc334a2afbc5cd3b048a86639e53d6ce8d4", "parents": [ "c8f7bbb773ec815aa49c15abd87ba8b02a14add3" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Dec 12 11:18:13 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec/cpu-all: Remove unused tswapls() definitions\n\nLast use of tswapls() was removed 2 years ago in commit\naee14c77f4 (\"linux-user: Rewrite do_getdents, do_getdents64\").\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Anton Johansson \u003canjo@rev.ng\u003e\nMessage-Id: \u003c20231212123401.37493-15-philmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "c8f7bbb773ec815aa49c15abd87ba8b02a14add3", "tree": "6a335394f28a052a66a27911421d51a4bc68cc2b", "parents": [ "edfc85875d4926208a86acd8f4f212b664df35ca" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Sat Dec 02 20:01:07 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec/cpu-all: Remove unused \u0027qemu/thread.h\u0027 header\n\nNothing is required from \"qemu/thread.h\" in \"exec/cpu-all.h\".\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Anton Johansson \u003canjo@rev.ng\u003e\nMessage-Id: \u003c20231212123401.37493-13-philmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "edfc85875d4926208a86acd8f4f212b664df35ca", "tree": "637fdeca7bfd322ff22b46f5a14bff72dd438b11", "parents": [ "e620363687d468530e00db59ea00f08e6f67eabc" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Sat Dec 02 20:00:02 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:05 2024 +0200" }, "message": "exec/cpu-all: Reduce \u0027qemu/rcu.h\u0027 header inclusion\n\n\"exec/cpu-all.h\" doesn\u0027t need definitions from \"qemu/rcu.h\",\nhowever \"exec/ram_addr.h\" does.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20231211212003.21686-17-philmd@linaro.org\u003e\n" }, { "commit": "e620363687d468530e00db59ea00f08e6f67eabc", "tree": "0ca99496d6daaf8d065e9256a149e7f4d80acdd9", "parents": [ "79f1926b2dfa25ac47adbdc0748dc5f951b55ac5" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Wed Apr 24 18:16:59 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:03:00 2024 +0200" }, "message": "accel/hvf: Use accel-specific per-vcpu @dirty field\n\nHVF has a specific use of the CPUState::vcpu_dirty field\n(CPUState::vcpu_dirty is not used by common code).\nTo make this field accel-specific, add and use a new\n@dirty variable in the AccelCPUState structure.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240424174506.326-4-philmd@linaro.org\u003e\n" }, { "commit": "79f1926b2dfa25ac47adbdc0748dc5f951b55ac5", "tree": "bf448e93b8f752f2bd5c2f7d58ae9cb610dd7f7c", "parents": [ "9ad49538c7b7c0672110994d81d687ed42bf3ef4" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Wed Apr 24 18:16:49 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:02:56 2024 +0200" }, "message": "accel/nvmm: Use accel-specific per-vcpu @dirty field\n\nNVMM has a specific use of the CPUState::vcpu_dirty field\n(CPUState::vcpu_dirty is not used by common code).\nTo make this field accel-specific, add and use a new\n@dirty variable in the AccelCPUState structure.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240424174506.326-3-philmd@linaro.org\u003e\n" }, { "commit": "9ad49538c7b7c0672110994d81d687ed42bf3ef4", "tree": "da3e7d1f3d9be68e682f88a645675b50675d41b4", "parents": [ "2379866c3bf7c5fd654cef64246af9d8a03f7d49" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Wed Apr 24 18:16:34 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 17:02:24 2024 +0200" }, "message": "accel/whpx: Use accel-specific per-vcpu @dirty field\n\nWHPX has a specific use of the CPUState::vcpu_dirty field\n(CPUState::vcpu_dirty is not used by common code).\nTo make this field accel-specific, add and use a new\n@dirty variable in the AccelCPUState structure.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240424174506.326-2-philmd@linaro.org\u003e\n" }, { "commit": "2379866c3bf7c5fd654cef64246af9d8a03f7d49", "tree": "2e9c4e78386ca433d5f76030c490863cc228742b", "parents": [ "e4751d340a49b117b90a411b179b8c892cf43d85" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Mon Apr 22 16:41:04 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "accel/tcg: Rename helper-head.h -\u003e helper-head.h.inc\n\nSince commit 139c1837db (\"meson: rename included C source files\nto .c.inc\"), QEMU standard procedure for included C files is to\nuse *.c.inc.\n\nBesides, since commit 6a0057aa22 (\"docs/devel: make a statement\nabout includes\") this is documented in the Coding Style:\n\n If you do use template header files they should be named with\n the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are\n being included for expansion.\n\nTherefore rename \"exec/helper-head.h\" as \"exec/helper-head.h.inc\".\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nAcked-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240424173333.96148-4-philmd@linaro.org\u003e\n" }, { "commit": "e4751d340a49b117b90a411b179b8c892cf43d85", "tree": "079d7c7aa2ff11a921275802b09699e97206b657", "parents": [ "893b4bde885c1f02edbe9d9533919abb0ac50490" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Mon Mar 25 15:30:33 2024 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "accel/tcg: Rename load-extract/store-insert headers using .h.inc suffix\n\nSince commit 139c1837db (\"meson: rename included C source files\nto .c.inc\"), QEMU standard procedure for included C files is to\nuse *.c.inc.\n\nBesides, since commit 6a0057aa22 (\"docs/devel: make a statement\nabout includes\") this is documented in the Coding Style:\n\n If you do use template header files they should be named with\n the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are\n being included for expansion.\n\nTherefore rename \u0027store-insert-al16.h\u0027 as \u0027store-insert-al16.h.inc\u0027\nand \u0027load-extract-al16-al8.h\u0027 as \u0027load-extract-al16-al8.h.inc\u0027.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nAcked-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240424173333.96148-3-philmd@linaro.org\u003e\n" }, { "commit": "893b4bde885c1f02edbe9d9533919abb0ac50490", "tree": "d1384fa8380a4e010addcaf0f4b7c647b7c37526", "parents": [ "6bba316e2333462aa8e93eda6908c06db3e4727a" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Wed Jan 10 15:49:40 2024 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "accel/tcg: Include missing headers in \u0027tb-jmp-cache.h\u0027\n\nDue to missing headers, when including \"tb-jmp-cache.h\" we might get:\n\n accel/tcg/tb-jmp-cache.h:21:21: error: field ‘rcu’ has incomplete type\n 21 | struct rcu_head rcu;\n | ^~~\n accel/tcg/tb-jmp-cache.h:24:9: error: unknown type name ‘vaddr’\n 24 | vaddr pc;\n | ^~~~~\n\nAdd the missing \"qemu/rcu.h\" and \"exec/cpu-common.h\" headers.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nAcked-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240111162442.43755-1-philmd@linaro.org\u003e\n" }, { "commit": "6bba316e2333462aa8e93eda6908c06db3e4727a", "tree": "8dcf0d4109bc280a4c71b37e196e17e177a1eb6a", "parents": [ "3b28c27067dd577a3ea137724c4247c8356915d0" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Dec 01 16:15:27 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "accel/tcg: Include missing \u0027hw/core/cpu.h\u0027 header\n\ntcg_cpu_init_cflags() accesses CPUState fields, so requires\n\"hw/core/cpu.h\" to get its structure definition.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Anton Johansson \u003canjo@rev.ng\u003e\nMessage-Id: \u003c20231212123401.37493-12-philmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "3b28c27067dd577a3ea137724c4247c8356915d0", "tree": "b401d4950380683479686a9ab5affbd48be6eb90", "parents": [ "7e17a524698809ea0cd2b848eab5516a480af75a" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Dec 05 22:40:15 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "accel/tcg: Un-inline retaddr helpers to \u0027user-retaddr.h\u0027\n\nset_helper_retaddr() is only used in accel/tcg/user-exec.c.\n\nclear_helper_retaddr() is only used in accel/tcg/cpu-exec.c\nand accel/tcg/user-exec.c.\n\nNo need to expose their definitions to all user-emulation\nfiles including \"exec/cpu_ldst.h\", move them to a new\n\"user-retaddr.h\" header (restricted to accel/tcg/).\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20231211212003.21686-19-philmd@linaro.org\u003e\n" }, { "commit": "7e17a524698809ea0cd2b848eab5516a480af75a", "tree": "f6e0f84e2cef8d6b5c3af3aab0f8e19ef6222e26", "parents": [ "9b21d29acfc9b516c6785e7ca73bff735ebf3d40" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Dec 01 18:58:00 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "target/i386: Include missing \u0027exec/exec-all.h\u0027 header\n\nThe XRSTOR instruction ends calling tlb_flush(), declared\nin \"exec/exec-all.h\".\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20231211212003.21686-13-philmd@linaro.org\u003e\n" }, { "commit": "9b21d29acfc9b516c6785e7ca73bff735ebf3d40", "tree": "55e6f7260b94ec76c255779e136f8207790814cf", "parents": [ "eedd109525e12f435cf36a4a43e73bc38005caf3" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 18 13:17:47 2024 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "target/sparc: Replace abi_ulong by uint32_t for TARGET_ABI32\n\nWe have abi_ulong \u003d\u003d uint32_t for the 32-bit ABI.\nUse the generic type to avoid to depend on the\n\"exec/user/abitypes.h\" header.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240418192525.97451-14-philmd@linaro.org\u003e\n" }, { "commit": "eedd109525e12f435cf36a4a43e73bc38005caf3", "tree": "509458abe888d870fce429d286f29688ab95fc68", "parents": [ "e92dd33224603ee5a42e0b13b6e055691325ba47" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Mon Dec 04 15:29:19 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "target/ppc/excp_helper: Avoid \u0027abi_ptr\u0027 in system emulation\n\n\u0027abi_ptr\u0027 is a user specific type. The system emulation\nequivalent is \u0027target_ulong\u0027. Use it in ppc_ldl_code()\nto emphasis this is not an user emulation function.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nAcked-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nReviewed-by: Thomas Huth \u003cthuth@redhat.com\u003e\nMessage-Id: \u003c20231211212003.21686-18-philmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "e92dd33224603ee5a42e0b13b6e055691325ba47", "tree": "3b762268eaf75aabd579dabc94df8343f837fc74", "parents": [ "83fb360d6a60b0a77dce3d3643d1a5311a235e58" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Dec 05 14:31:59 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "target: Define TCG_GUEST_DEFAULT_MO in \u0027cpu-param.h\u0027\n\naccel/tcg/ files requires the following definitions:\n\n - TARGET_LONG_BITS\n - TARGET_PAGE_BITS\n - TARGET_PHYS_ADDR_SPACE_BITS\n - TCG_GUEST_DEFAULT_MO\n\nThe first 3 are defined in \"cpu-param.h\". The last one\nin \"cpu.h\", with a bunch of definitions irrelevant for\nTCG. By moving the TCG_GUEST_DEFAULT_MO definition to\n\"cpu-param.h\", we can simplify various accel/tcg includes.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nAcked-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nMessage-Id: \u003c20231211212003.21686-4-philmd@linaro.org\u003e\n" }, { "commit": "83fb360d6a60b0a77dce3d3643d1a5311a235e58", "tree": "5f9c5daeb66cf90c2507a82f9ef3bbb3562bd149", "parents": [ "3aac8abaca536db275da671db088fef2dd82536d" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Wed Dec 06 16:12:12 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "semihosting/guestfd: Remove unused \u0027semihosting/uaccess.h\u0027 header\n\nNothing in guestfd.c requires \"semihosting/uaccess.h\" nor \"qemu.h\".\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Anton Johansson \u003canjo@rev.ng\u003e\nMessage-Id: \u003c20231212123401.37493-8-philmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "3aac8abaca536db275da671db088fef2dd82536d", "tree": "25f6c47845dd45bf3030b197cc9928de65e62dcb", "parents": [ "0654c79416f346d967fbc7dad7ca451b49bbd822" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Wed Dec 06 16:11:15 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "semihosting/uaccess: Avoid including \u0027cpu.h\u0027\n\n\"semihosting/uaccess.h\" only requires the following headers:\n\n - \"exec/cpu-defs.h\" for target_ulong,\n - \"exec/cpu-common.h\" for cpu_memory_rw_debug()\n - \"exec/tswap.h\" for tswap32() and tswap64().\n\nInclude them instead of the huge \"cpu.h\".\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c42c6471e-8383-45e0-85ee-e20ca32ecbad@linaro.org\u003e\n" }, { "commit": "0654c79416f346d967fbc7dad7ca451b49bbd822", "tree": "c92b330eacadde6b6ea455f0b307789fe0dd4ea5", "parents": [ "94326e4f217991102770667f684156bdbef599e6" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 18 16:45:33 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "gdbstub: Avoid including \u0027cpu.h\u0027 in \u0027gdbstub/helpers.h\u0027\n\nWe only need the \"exec/tswap.h\" and \"cpu-param.h\" headers.\nOnly include \"cpu.h\" in the target gdbstub.c source files.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240418192525.97451-20-philmd@linaro.org\u003e\n" }, { "commit": "94326e4f217991102770667f684156bdbef599e6", "tree": "9264c9337448149aa917abf94ed55c3cb06ba9df", "parents": [ "fe7667343c81bffc5f87e591589c691faa84286a" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Mar 22 16:11:47 2024 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "gdbstub: Simplify #ifdef\u0027ry in helpers.h\n\nSlightly simplify by checking NEED_CPU_H definition in header.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240322161439.6448-2-philmd@linaro.org\u003e\n" }, { "commit": "fe7667343c81bffc5f87e591589c691faa84286a", "tree": "c7c05a14d706889e14a09613d47c865b461210d8", "parents": [ "4597463b3851d9f6ec22542b6645511d7f889f78" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Dec 07 16:52:16 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "gdbstub: Include missing \u0027hw/core/cpu.h\u0027 header\n\nFunctions such gdb_get_cpu_pid() dereference CPUState so\nrequire the structure declaration from \"hw/core/cpu.h\":\n\n static uint32_t gdb_get_cpu_pid(CPUState *cpu)\n {\n ...\n return cpu-\u003ecluster_index + 1;\n }\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Warner Losh \u003cimp@bsdimp.com\u003e\nMessage-Id: \u003c20231211212003.21686-15-philmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "4597463b3851d9f6ec22542b6645511d7f889f78", "tree": "5ca4b88b1d255a0d63f674b9c3c4e1b3bf9c4c8e", "parents": [ "75bbe6a4d2bc9c3681ab71021645d655ad045a75" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Dec 05 23:02:11 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:31:37 2024 +0200" }, "message": "accel: Include missing \u0027exec/cpu_ldst.h\u0027 header\n\nTheses files call cpu_ldl_code() which is declared\nin \"exec/cpu_ldst.h\".\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20231211212003.21686-5-philmd@linaro.org\u003e\n" }, { "commit": "75bbe6a4d2bc9c3681ab71021645d655ad045a75", "tree": "66bc852614d7ca0004ee157ed683cc98bdf5911a", "parents": [ "8501048b501aec0d2d422aafd713348c235d8b83" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Dec 07 10:41:27 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:28:11 2024 +0200" }, "message": "exec: Expose \u0027target_page.h\u0027 API to user emulation\n\nUser-only objects might benefit from the \"exec/target_page.h\"\nAPI, which allows to build some objects once for all targets.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Warner Losh \u003cimp@bsdimp.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20231211212003.21686-3-philmd@linaro.org\u003e\n" }, { "commit": "8501048b501aec0d2d422aafd713348c235d8b83", "tree": "ab6b0bd554bd32e04dc3d9e442c22dfedeb5f410", "parents": [ "51579d40f9c719361ec9355bb48386e5d3ce85c1" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Dec 05 23:24:03 2023 +0100" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:28:11 2024 +0200" }, "message": "exec: Include \u0027cpu.h\u0027 before validating CPUArchState placement\n\nCPUArchState \u0027env\u0027 field is defined within the ArchCPU structure,\nso we need to include each target \"cpu.h\" header which defines it.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Warner Losh \u003cimp@bsdimp.com\u003e\nMessage-Id: \u003c20231211212003.21686-2-philmd@linaro.org\u003e\n" }, { "commit": "51579d40f9c719361ec9355bb48386e5d3ce85c1", "tree": "dee2158b0daeba3dcb67675a791a579cd6489efa", "parents": [ "7d7a21ba691d3f52fdcf123adf2b79f7ce88174d" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Sep 14 21:40:07 2023 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 15:28:11 2024 +0200" }, "message": "exec: Reduce tlb_set_dirty() declaration scope\n\ntlb_set_dirty() is only used in accel/tcg/cputlb.c,\nwhere it is defined. Declare it statically, removing\nthe stub.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Harsh Prateek Bora \u003charshpb@linux.ibm.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240418192525.97451-11-philmd@linaro.org\u003e\n" }, { "commit": "7d7a21ba691d3f52fdcf123adf2b79f7ce88174d", "tree": "775d9df61b38437fae37c743d867dfec262f960f", "parents": [ "a118c4aff4087eafb68f7132b233ad548cf16376" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Tue Jun 13 16:29:11 2023 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 26 09:49:51 2024 +0200" }, "message": "exec: Rename NEED_CPU_H -\u003e COMPILING_PER_TARGET\n\n\u0027NEED_CPU_H\u0027 guard target-specific code; it is defined by meson\naltogether with the \u0027CONFIG_TARGET\u0027 definition. Rename NEED_CPU_H\nas COMPILING_PER_TARGET to clarify its meaning.\n\nMechanical change running:\n\n $ sed -i s/NEED_CPU_H/COMPILING_PER_TARGET/g $(git grep -l NEED_CPU_H)\n\nthen manually add a /* COMPILING_PER_TARGET */ comment\nafter the \u0027#endif\u0027 when the block is large.\n\nInspired-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240322161439.6448-4-philmd@linaro.org\u003e\n" }, { "commit": "4fa333e08dd96395a99ea8dd9e4c73a29dd23344", "tree": "fdde72d666e5d4dc1f2334cda9925ff5d03219df", "parents": [ "ae6d91a7e9b77abb029ed3fa9fad461422286942" ], "author": { "name": "Eric Blake", "email": "eblake@redhat.com", "time": "Mon Apr 08 11:00:44 2024 -0500" }, "committer": { "name": "Eric Blake", "email": "eblake@redhat.com", "time": "Thu Apr 25 12:59:19 2024 -0500" }, "message": "nbd/server: Mark negotiation functions as coroutine_fn\n\nnbd_negotiate() is already marked coroutine_fn. And given the fix in\nthe previous patch to have nbd_negotiate_handle_starttls not create\nand wait on a g_main_loop (as that would violate coroutine\nconstraints), it is worth marking the rest of the related static\nfunctions reachable only during option negotiation as also being\ncoroutine_fn.\n\nSuggested-by: Vladimir Sementsov-Ogievskiy \u003cvsementsov@yandex-team.ru\u003e\nSigned-off-by: Eric Blake \u003ceblake@redhat.com\u003e\nMessage-ID: \u003c20240408160214.1200629-6-eblake@redhat.com\u003e\nReviewed-by: Vladimir Sementsov-Ogievskiy \u003cvsementsov@yandex-team.ru\u003e\n[eblake: drop one spurious coroutine_fn marking]\nSigned-off-by: Eric Blake \u003ceblake@redhat.com\u003e\n" }, { "commit": "a118c4aff4087eafb68f7132b233ad548cf16376", "tree": "2177101d366d37a7f15c2a86e23977dbaf3780ca", "parents": [ "83baec642a13a69398a2643a1f905606c13cd363", "098de99aad1aa911b4950b47b55d2e2bcc4f9c0c" ], "author": { "name": "Richard Henderson", "email": "richard.henderson@linaro.org", "time": "Thu Apr 25 09:43:29 2024 -0700" }, "committer": { "name": "Richard Henderson", "email": "richard.henderson@linaro.org", "time": "Thu Apr 25 09:43:29 2024 -0700" }, "message": "Merge tag \u0027hw-misc-20240425\u0027 of https://github.com/philmd/qemu into staging\n\nMisc HW patch queue\n\n- Script to compare machines compat_props[] (Maksim)\n- Introduce \u0027module\u0027 CPU topology level (Zhao)\n- Various cleanups (Thomas, Zhao, Inès, Bernhard)\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmYqN3wACgkQ4+MsLN6t\n# wN4hTw/9FHsItnEkme/864DRPSP7A9mCGa+JfzJmsL8oUb9fBjXXKm+lNchMLu3B\n# uvzfXB2Ea24yf5vyrldo0XlU3i/4GDvqXTI6YFYqBvitGICauYBu+6n2NZh2Y/Pn\n# zZCcVo167o0q7dHu2WSrZ6cSUchsF2C80HjuS07QaN2YZ7QMuN1+uqTjCQ/JHQWA\n# MH4xHh7cXdfCbbv8iNhMWn6sa+Bw/UyfRcc2W6w9cF5Q5cuuTshgDyd0JBOzkM1i\n# Mcul7TuKrSiLUeeeqfTjwtw3rtbNfkelV3ycgvgECFAlzPSjF5a6d/EGdO2zo3T/\n# aFZnQBYrb4U0SzsmfXFHW7cSylIc1Jn2CCuZZBIvdVcu8TGDD5XsgZbGoCfKdWxp\n# l67qbQJy1Mp3LrRzygJIaxDOfE8fhhRrcIxfK/GoTHaCkqeFRkGjTeiDTVBqAES2\n# zs6kUYZyG/xGaa2tsMu+HbtSO5EEqPC2QCdHayY3deW42Kwjj/HFV50Ya8YgYSVp\n# gEAjTDOle2dDjlkYud+ymTJz7LnGb3G7q0EZRI9DWolx/bu+uZGQqTSRRre4qFQY\n# SgN576hsFGN4NdM7tyJWiiqD/OC9ZeqUx3gGBtmI52Q6obBCE9hcow0fPs55Tk95\n# 1YzPrt/3IoPI5ZptCoA8DFiysQ46OLtpIsQO9YcrpJmxWyLDSr0\u003d\n# \u003dtm+U\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Thu 25 Apr 2024 03:59:08 AM PDT\n# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE\n# gpg: Good signature from \"Philippe Mathieu-Daudé (F4BUG) \u003cf4bug@amsat.org\u003e\" [full]\n\n* tag \u0027hw-misc-20240425\u0027 of https://github.com/philmd/qemu: (22 commits)\n hw/core: Support module-id in numa configuration\n hw/core: Introduce module-id as the topology subindex\n hw/core/machine: Support modules in -smp\n hw/core/machine: Introduce the module as a CPU topology level\n hw/i386/pc_sysfw: Remove unused parameter from pc_isa_bios_init()\n hw/misc : Correct 5 spaces indents in stm32l4x5_exti\n hw/xtensa: Include missing \u0027exec/cpu-common.h\u0027 in \u0027bootparam.h\u0027\n hw/elf_ops: Rename elf_ops.h -\u003e elf_ops.h.inc\n hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return boolean\n hw/cxl/cxl-cdat: Make ct3_build_cdat() return boolean\n hw/cxl/cxl-cdat: Make ct3_load_cdat() return boolean\n hw: Add a Kconfig switch for the TYPE_CPU_CLUSTER device\n hw: Fix problem with the A*MPCORE switches in the Kconfig files\n hw/riscv/virt: Replace sprintf by g_strdup_printf\n hw/misc/imx: Replace sprintf() by snprintf()\n hw/misc/applesmc: Simplify DeviceReset handler\n target/i386: Move APIC related code to cpu-apic.c\n hw/core: Remove check on NEED_CPU_H in tcg-cpu-ops.h\n scripts: add script to compare compatibility properties\n python/qemu/machine: add method to retrieve QEMUMachine::binary field\n ...\n\nSigned-off-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "83baec642a13a69398a2643a1f905606c13cd363", "tree": "56ddab1c6d9d1869df33f60f34a934b726ef43ff", "parents": [ "45bef95ca5e9d649e432f2acd82163fb5bccbe47", "214652da123e3821657a64691ee556281e9f6238" ], "author": { "name": "Richard Henderson", "email": "richard.henderson@linaro.org", "time": "Thu Apr 25 08:07:45 2024 -0700" }, "committer": { "name": "Richard Henderson", "email": "richard.henderson@linaro.org", "time": "Thu Apr 25 08:07:45 2024 -0700" }, "message": "Merge tag \u0027pull-target-arm-20240425\u0027 of https://git.linaro.org/people/pmaydell/qemu-arm into staging\n\ntarget-arm queue:\n * Implement FEAT_NMI and NMI support in the GICv3\n * hw/dma: avoid apparent overflow in soc_dma_set_request\n * linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code\n * Add ResetType argument to Resettable hold and exit phase methods\n * Add RESET_TYPE_SNAPSHOT_LOAD ResetType\n * Implement STM32L4x5 USART\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmYqMhMZHHBldGVyLm1h\n# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3uVlD/47U3zYP33y4+wJcRScC0QI\n# jYd82jS7GhD5YP5QPrIEMaSbDwtYGi4Rez1taaHvZ2fWLg2gE973iixmTaM2mXCd\n# xPEqMsRXkFrQnC89K5/v9uR04AvHxoM8J2mD2OKnUT0RVBs38WxCUMLETBsD18/q\n# obs1RzDRhEs5BnwwPMm5HI1iQeVvDRe/39O3w3rZfA8DuqerrNOQWuJd43asHYjO\n# Gc1QzCGhALlXDoqk11IzjhJ7es8WbJ5XGvrSNe9QLGNJwNsu9oi1Ez+5WK2Eht9r\n# eRvGNFjH4kQY1YCShZjhWpdzU9KT0+80KLirMJFcI3vUztrYZ027/rMyKLHVOybw\n# YAqgEUELwoGVzacpaJg73f77uknKoXrfTH25DfoLX0yFCB35JHOPcjU4Uq1z1pfV\n# I80ZcJBDJ95mXPfyKLrO+0IyVBztLybufedK2aiH16waEGDpgsJv66FB2QRuQBYW\n# O0i6/4DEUZmfSpOmr8ct+julz7wCWSjbvo6JFWxzzxvD0M5T3AFKXZI244g1SMdh\n# LS8V7WVCVzVJ5mK8Ujp2fVaIIxiBzlXVZrQftWv5rhyDOiIIeP8pdekmPlI6p5HK\n# 3/2efzSYNL2UCDZToIq24El/3md/7vHR6DBfBT1/pagxWUstqqLgkJO42jQtTG0E\n# JY1cZ/EQY7cqXGrww8lhWA\u003d\u003d\n# \u003dWEsU\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Thu 25 Apr 2024 03:36:03 AM PDT\n# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE\n# gpg: issuer \"peter.maydell@linaro.org\"\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\" [full]\n# gpg: aka \"Peter Maydell \u003cpmaydell@gmail.com\u003e\" [full]\n# gpg: aka \"Peter Maydell \u003cpmaydell@chiark.greenend.org.uk\u003e\" [full]\n# gpg: aka \"Peter Maydell \u003cpeter@archaic.org.uk\u003e\" [unknown]\n\n* tag \u0027pull-target-arm-20240425\u0027 of https://git.linaro.org/people/pmaydell/qemu-arm: (37 commits)\n tests/qtest: Add tests for the STM32L4x5 USART\n hw/arm: Add the USART to the stm32l4x5 SoC\n hw/char/stm32l4x5_usart: Add options for serial parameters setting\n hw/char/stm32l4x5_usart: Enable serial read and write\n hw/char: Implement STM32L4x5 USART skeleton\n reset: Add RESET_TYPE_SNAPSHOT_LOAD\n docs/devel/reset: Update to new API for hold and exit phase methods\n hw, target: Add ResetType argument to hold and exit phase methods\n scripts/coccinelle: New script to add ResetType to hold and exit phases\n allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset\n hw/misc: Don\u0027t special case RESET_TYPE_COLD in npcm7xx_clk, gcr\n linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code\n hw/dma: avoid apparent overflow in soc_dma_set_request\n hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI\n target/arm: Add FEAT_NMI to max\n hw/intc/arm_gicv3: Report the VINMI interrupt\n hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()\n hw/intc/arm_gicv3: Implement NMI interrupt priority\n hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()\n hw/intc/arm_gicv3: Add NMI handling CPU interface registers\n ...\n\nSigned-off-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "45bef95ca5e9d649e432f2acd82163fb5bccbe47", "tree": "ceff1817f66a84b59251359bc20b3d3a3766c315", "parents": [ "5da72194df36535d773c8bdc951529ecd5e31707", "17523a38194d80f2955c6a8e0702e0fc86dd083d" ], "author": { "name": "Richard Henderson", "email": "richard.henderson@linaro.org", "time": "Thu Apr 25 08:06:33 2024 -0700" }, "committer": { "name": "Richard Henderson", "email": "richard.henderson@linaro.org", "time": "Thu Apr 25 08:06:33 2024 -0700" }, "message": "Merge tag \u0027pull-request-2024-04-25\u0027 of https://gitlab.com/thuth/qemu into staging\n\n* Update OpenBSD CI image to 7.5\n* Update/remove Ubuntu 20.04 CI jobs\n* Update (most) CentOS 8 CI jobs to CentOS 9\n* Some clean-ups and improvements to travis.yml\n* Minor test fixes\n* s390x header clean-ups\n* Doc updates\n\n# -----BEGIN PGP SIGNATURE-----\n#\n# iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmYqbu4RHHRodXRoQHJl\n# ZGhhdC5jb20ACgkQLtnXdP5wLbWqeA//cFAzjjmayCRZzuwwCFH0ILPrMNViRLFc\n# ZuslNEFygDPl1H1wnw3MKzhHy1hbaC3gf30MjtejU61OMMyxS4exZd1rvw94a0cm\n# OEisE8UG52kRsqPwKPktB2bybgX3BZbrFEwp1P0DsvpLTX7wI5nOZyNR4zWOf5Ym\n# mODN/MjMFOhWjONOnNDRn4TbySQqolIQBTCq+f1J5Ej74V+p17aC5Fe3xhlFp8Ip\n# aRockPW6dLpNt26zx6kKvQSYtkyLgQJSeUUyUCgcla03yzNSuV/kJPUoW0ewa+q8\n# DZg1Ru5WJ6O8lELQdYq630cmdwg3e9EeI6q/U/1A11auuLaafOBi0eZW9LdPlrqD\n# 6a+zwVn+ipyRdz8eRGZVRGdhJ6XT27YfFuKxdiu4BxnS0LRks4vDcXreIcQmiIUN\n# bg/zSp6snCpYf7+GlUReZXWnVx401nu59+BNNKUV0qIxdORNm8kwd9ZpSQwXP/nF\n# BMPhj2hoqvWb4C4r3WlTaSPlkJGhkb2lMLucjCbeGrdnmna0RFOFB301fllbpnVm\n# 11SRipMEfrj/G5qp4giPLcruzesvRaZm85nmwDyOQWxr5Q0KWWfBVXZMt+qqOckR\n# 2SUtLPd9nWruCy7KN15BrOWkmXc+OU8UFUqXIOvflkI6aF1bmFYRyrXgqX2q7QDT\n# kEfWnBvBqxw\u003d\n# \u003d1uVo\n# -----END PGP SIGNATURE-----\n# gpg: Signature made Thu 25 Apr 2024 07:55:42 AM PDT\n# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5\n# gpg: issuer \"thuth@redhat.com\"\n# gpg: Good signature from \"Thomas Huth \u003cth.huth@gmx.de\u003e\" [full]\n# gpg: aka \"Thomas Huth \u003cthuth@redhat.com\u003e\" [full]\n# gpg: aka \"Thomas Huth \u003cth.huth@posteo.de\u003e\" [unknown]\n# gpg: aka \"Thomas Huth \u003chuth@tuxfamily.org\u003e\" [full]\n\n* tag \u0027pull-request-2024-04-25\u0027 of https://gitlab.com/thuth/qemu:\n target/s390x: Remove KVM stubs in cpu_models.h\n tests/unit: Remove debug statements in test-nested-aio-poll.c\n docs/devel: fix minor typo in submitting-a-patch.rst\n hw/s390x: Include missing \u0027cpu.h\u0027 header\n tests: Update our CI to use CentOS Stream 9 instead of 8\n tests/docker/dockerfiles: Run lcitool-refresh after the lcitool update\n tests/lcitool/libvirt-ci: Update to the latest master branch\n tests: Remove Ubuntu 20.04 container\n .travis.yml: Do some more testing with Clang\n .travis.yml: Update the jobs to Ubuntu 22.04\n .travis.yml: Remove the unused UNRELIABLE environment variable\n Revert \".travis.yml: Cache Avocado cache\"\n tests/vm: update openbsd image to 7.5\n docs: i386: pc: Update maximum CPU numbers for PC Q35\n tests/qtest : Use `g_assert_cmphex` instead of `g_assert_cmpuint`\n MAINTAINERS: update email of Peter Lieven\n\nSigned-off-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "17523a38194d80f2955c6a8e0702e0fc86dd083d", "tree": "ceff1817f66a84b59251359bc20b3d3a3766c315", "parents": [ "73a1e96935dbaec950a310916eec13b46871b8b2" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Apr 19 11:06:31 2024 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Thu Apr 25 15:15:25 2024 +0200" }, "message": "target/s390x: Remove KVM stubs in cpu_models.h\n\nSince the calls are elided when KVM is not available,\nwe can remove the stubs (which are never compiled).\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nMessage-ID: \u003c20240419090631.48055-1-philmd@linaro.org\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "73a1e96935dbaec950a310916eec13b46871b8b2", "tree": "0d0489fd7404ce5b6cc8f775411094be52337ae8", "parents": [ "b1f8536c943dd1d0ffea081d79001ee124157f97" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Mon Apr 22 13:22:46 2024 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Thu Apr 25 15:15:25 2024 +0200" }, "message": "tests/unit: Remove debug statements in test-nested-aio-poll.c\n\nWe have been running this test for almost a year; it\nis safe to remove its debug statements, which clutter\nCI jobs output:\n\n ▶ 88/100 /nested-aio-poll OK\n io_read 0x16bb26158\n io_poll_true 0x16bb26158\n \u003e io_poll_ready\n io_read 0x16bb26164\n \u003c io_poll_ready\n io_poll_true 0x16bb26158\n io_poll_false 0x16bb26164\n \u003e io_poll_ready\n io_poll_false 0x16bb26164\n io_poll_false 0x16bb26164\n io_poll_false 0x16bb26164\n io_poll_false 0x16bb26164\n io_poll_false 0x16bb26164\n io_poll_false 0x16bb26164\n io_poll_false 0x16bb26164\n io_poll_false 0x16bb26164\n io_poll_false 0x16bb26164\n io_read 0x16bb26164\n \u003c io_poll_ready\n 88/100 qemu:unit / test-nested-aio-poll OK\n\nReviewed-by: Eric Blake \u003ceblake@redhat.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Stefan Hajnoczi \u003cstefanha@redhat.com\u003e\nMessage-ID: \u003c20240422112246.83812-1-philmd@linaro.org\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "b1f8536c943dd1d0ffea081d79001ee124157f97", "tree": "b83766d6846a20579f14908574077021f8d43b83", "parents": [ "9a72bea6828ef3f9c957fde1a390a81d66b38cec" ], "author": { "name": "Manos Pitsidianakis", "email": "manos.pitsidianakis@linaro.org", "time": "Mon Apr 22 15:41:28 2024 +0300" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Thu Apr 25 15:15:25 2024 +0200" }, "message": "docs/devel: fix minor typo in submitting-a-patch.rst\n\ns/Resolved:/Resolves:/\n\nSigned-off-by: Manos Pitsidianakis \u003cmanos.pitsidianakis@linaro.org\u003e\nMessage-ID: \u003c20240422124128.4034482-1-manos.pitsidianakis@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "9a72bea6828ef3f9c957fde1a390a81d66b38cec", "tree": "d2e8c439d9ed801c0cbe841b8d7ce0ca52db497d", "parents": [ "641b1efe01b2dd6e7ac92f23d392dcee73508746" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Fri Mar 22 17:28:22 2024 +0100" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Thu Apr 25 15:15:25 2024 +0200" }, "message": "hw/s390x: Include missing \u0027cpu.h\u0027 header\n\n\"cpu.h\" is implicitly included. Include it explicitly to\navoid the following error when refactoring headers:\n\n hw/s390x/s390-stattrib.c:86:40: error: use of undeclared identifier \u0027TARGET_PAGE_SIZE\u0027\n len \u003d sac-\u003epeek_stattr(sas, addr / TARGET_PAGE_SIZE, buflen, vals);\n ^\n hw/s390x/s390-stattrib.c:94:58: error: use of undeclared identifier \u0027TARGET_PAGE_MASK\u0027\n addr / TARGET_PAGE_SIZE, len, addr \u0026 ~TARGET_PAGE_MASK);\n ^\n hw/s390x/s390-stattrib.c:224:40: error: use of undeclared identifier \u0027TARGET_PAGE_BITS\u0027\n qemu_put_be64(f, (start_gfn \u003c\u003c TARGET_PAGE_BITS) | STATTR_FLAG_MORE);\n ^\n In file included from hw/s390x/s390-virtio-ccw.c:17:\n hw/s390x/s390-virtio-hcall.h:22:27: error: unknown type name \u0027CPUS390XState\u0027\n int s390_virtio_hypercall(CPUS390XState *env);\n ^\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Thomas Huth \u003cthuth@redhat.com\u003e\nAcked-by: Eric Farman \u003cfarman@linux.ibm.com\u003e\nMessage-ID: \u003c20240322162822.7391-1-philmd@linaro.org\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "ae6d91a7e9b77abb029ed3fa9fad461422286942", "tree": "3d8a72e2602f5d394816ba25152f7ee3c2d89648", "parents": [ "5da72194df36535d773c8bdc951529ecd5e31707" ], "author": { "name": "Zhu Yangyang", "email": "zhuyangyang14@huawei.com", "time": "Mon Apr 08 11:00:43 2024 -0500" }, "committer": { "name": "Eric Blake", "email": "eblake@redhat.com", "time": "Thu Apr 25 07:56:16 2024 -0500" }, "message": "nbd/server: do not poll within a coroutine context\n\nCoroutines are not supposed to block. Instead, they should yield.\n\nThe client performs TLS upgrade outside of an AIOContext, during\nsynchronous handshake; this still requires g_main_loop. But the\nserver responds to TLS upgrade inside a coroutine, so a nested\ng_main_loop is wrong. Since the two callbacks no longer share more\nthan the setting of data.complete and data.error, it\u0027s just as easy to\nuse static helpers instead of trying to share a common code path. It\nis also possible to add assertions that no other code is interfering\nwith the eventual path to qio reaching the callback, whether or not it\nrequired a yield or main loop.\n\nFixes: f95910f (\"nbd: implement TLS support in the protocol negotiation\")\nSigned-off-by: Zhu Yangyang \u003czhuyangyang14@huawei.com\u003e\n[eblake: move callbacks to their use point, add assertions]\nSigned-off-by: Eric Blake \u003ceblake@redhat.com\u003e\nMessage-ID: \u003c20240408160214.1200629-5-eblake@redhat.com\u003e\nReviewed-by: Vladimir Sementsov-Ogievskiy \u003cvsementsov@yandex-team.ru\u003e\n" }, { "commit": "098de99aad1aa911b4950b47b55d2e2bcc4f9c0c", "tree": "fc3a4c4161e513ac5f33a43c83ae575517dea0f2", "parents": [ "989bb312b021d66927db8e5f443503d63722b38d" ], "author": { "name": "Zhao Liu", "email": "zhao1.liu@intel.com", "time": "Wed Apr 24 23:49:12 2024 +0800" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/core: Support module-id in numa configuration\n\nModule is a level above the core, thereby supporting numa\nconfiguration on the module level can bring user more numa flexibility.\n\nThis is the natural further support for module level.\n\nAdd module level support in numa configuration.\n\nTested-by: Yongwei Ma \u003cyongwei.ma@intel.com\u003e\nSigned-off-by: Zhao Liu \u003czhao1.liu@intel.com\u003e\nTested-by: Babu Moger \u003cbabu.moger@amd.com\u003e\nMessage-ID: \u003c20240424154929.1487382-5-zhao1.liu@intel.com\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n" }, { "commit": "989bb312b021d66927db8e5f443503d63722b38d", "tree": "4263be0374b860972471d0b8f958cabe3b706c2a", "parents": [ "8ec0a46347987c74464fe67c42030d074fe8c0f0" ], "author": { "name": "Zhao Liu", "email": "zhao1.liu@intel.com", "time": "Wed Apr 24 23:49:11 2024 +0800" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/core: Introduce module-id as the topology subindex\n\nAdd module-id in CpuInstanceProperties, to locate the CPU with module\nlevel.\n\nSuggested-by: Xiaoyao Li \u003cxiaoyao.li@intel.com\u003e\nTested-by: Yongwei Ma \u003cyongwei.ma@intel.com\u003e\nSigned-off-by: Zhao Liu \u003czhao1.liu@intel.com\u003e\nTested-by: Babu Moger \u003cbabu.moger@amd.com\u003e\nAcked-by: Markus Armbruster \u003carmbru@redhat.com\u003e\nMessage-ID: \u003c20240424154929.1487382-4-zhao1.liu@intel.com\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n" }, { "commit": "8ec0a46347987c74464fe67c42030d074fe8c0f0", "tree": "c2bef23fe8cf523af39a41489175cf8443514d63", "parents": [ "dcba73b4453b7ed74d2ae24c5c8b273431c4484c" ], "author": { "name": "Zhao Liu", "email": "zhao1.liu@intel.com", "time": "Wed Apr 24 23:49:10 2024 +0800" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/core/machine: Support modules in -smp\n\nAdd \"modules\" parameter parsing support in -smp.\n\nSuggested-by: Xiaoyao Li \u003cxiaoyao.li@intel.com\u003e\nTested-by: Yongwei Ma \u003cyongwei.ma@intel.com\u003e\nSigned-off-by: Zhao Liu \u003czhao1.liu@intel.com\u003e\nTested-by: Babu Moger \u003cbabu.moger@amd.com\u003e\nAcked-by: Markus Armbruster \u003carmbru@redhat.com\u003e\nMessage-ID: \u003c20240424154929.1487382-3-zhao1.liu@intel.com\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n" }, { "commit": "dcba73b4453b7ed74d2ae24c5c8b273431c4484c", "tree": "5e8491f43471ee9633342f190a891374dfa10bf9", "parents": [ "f4b63768b91811cdcf1fb7b270587123251dfea5" ], "author": { "name": "Zhao Liu", "email": "zhao1.liu@intel.com", "time": "Wed Apr 24 23:49:09 2024 +0800" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/core/machine: Introduce the module as a CPU topology level\n\nIn x86, module is the topology level above core, which contains a set\nof cores that share certain resources (in current products, the resource\nusually includes L2 cache, as well as module scoped features and MSRs).\n\nThough smp.clusters could also share the L2 cache resource [1], there\nare following reasons that drive us to introduce the new smp.modules:\n\n * As the CPU topology abstraction in device tree [2], cluster supports\n nesting (though currently QEMU hasn\u0027t support that). In contrast,\n (x86) module does not support nesting.\n\n * Due to nesting, there is great flexibility in sharing resources\n on cluster, rather than narrowing cluster down to sharing L2 (and\n L3 tags) as the lowest topology level that contains cores.\n\n * Flexible nesting of cluster allows it to correspond to any level\n between the x86 package and core.\n\n * In Linux kernel, x86\u0027s cluster only represents the L2 cache domain\n but QEMU\u0027s smp.clusters is the CPU topology level. Linux kernel will\n also expose module level topology information in sysfs for x86. To\n avoid cluster ambiguity and keep a consistent CPU topology naming\n style with the Linux kernel, we introduce module level for x86.\n\nThe module is, in existing hardware practice, the lowest layer that\ncontains the core, while the cluster is able to have a higher\ntopological scope than the module due to its nesting.\n\nTherefore, place the module between the cluster and the core:\n\n drawer/book/socket/die/cluster/module/core/thread\n\nWith the above topological hierarchy order, introduce module level\nsupport in MachineState and MachineClass.\n\n[1]: https://lore.kernel.org/qemu-devel/c3d68005-54e0-b8fe-8dc1-5989fe3c7e69@huawei.com/\n[2]: https://www.kernel.org/doc/Documentation/devicetree/bindings/cpu/cpu-topology.txt\n\nSuggested-by: Xiaoyao Li \u003cxiaoyao.li@intel.com\u003e\nTested-by: Yongwei Ma \u003cyongwei.ma@intel.com\u003e\nSigned-off-by: Zhao Liu \u003czhao1.liu@intel.com\u003e\nTested-by: Babu Moger \u003cbabu.moger@amd.com\u003e\nMessage-ID: \u003c20240424154929.1487382-2-zhao1.liu@intel.com\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n" }, { "commit": "f4b63768b91811cdcf1fb7b270587123251dfea5", "tree": "f96dfd905177f3732accba1772f0d0e95e2fa9fc", "parents": [ "4f88e5215a74a97563c958d63634b107eff30c9f" ], "author": { "name": "Bernhard Beschow", "email": "shentey@gmail.com", "time": "Mon Apr 22 22:06:22 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/i386/pc_sysfw: Remove unused parameter from pc_isa_bios_init()\n\nSigned-off-by: Bernhard Beschow \u003cshentey@gmail.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nMessage-ID: \u003c20240422200625.2768-2-shentey@gmail.com\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n" }, { "commit": "4f88e5215a74a97563c958d63634b107eff30c9f", "tree": "e453b1f8210caba62a7224ede7ddaa23f83cc031", "parents": [ "206e562c5aa5db55362bff0e88ba220250858f35" ], "author": { "name": "Inès Varhol", "email": "ines.varhol@telecom-paris.fr", "time": "Sun Apr 21 16:14:23 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/misc : Correct 5 spaces indents in stm32l4x5_exti\n\nSigned-off-by: Inès Varhol \u003cines.varhol@telecom-paris.fr\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nMessage-ID: \u003c20240421141455.116548-1-ines.varhol@telecom-paris.fr\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n" }, { "commit": "206e562c5aa5db55362bff0e88ba220250858f35", "tree": "b46e713f226d14efa553605360d41c0b6f4d9d1f", "parents": [ "159fb790e48992f74644b0b0876615e8caacbfe4" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 18 17:07:03 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/xtensa: Include missing \u0027exec/cpu-common.h\u0027 in \u0027bootparam.h\u0027\n\ncpu_physical_memory_write() is declared in \"exec/cpu-common.h\".\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Anton Johansson \u003canjo@rev.ng\u003e\nMessage-Id: \u003c20240418192525.97451-21-philmd@linaro.org\u003e\n" }, { "commit": "159fb790e48992f74644b0b0876615e8caacbfe4", "tree": "794e80ccfd24b6819899721d1fa7c290c7aa003c", "parents": [ "e0ddabc6d4cfef4a5c7f154f0b0ad00dbf9a18d0" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 18 16:49:16 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/elf_ops: Rename elf_ops.h -\u003e elf_ops.h.inc\n\nSince commit 139c1837db (\"meson: rename included C source files\nto .c.inc\"), QEMU standard procedure for included C files is to\nuse *.c.inc.\n\nBesides, since commit 6a0057aa22 (\"docs/devel: make a statement\nabout includes\") this is documented in the Coding Style:\n\n If you do use template header files they should be named with\n the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are\n being included for expansion.\n\nTherefore rename \"hw/elf_ops.h\" as \"hw/elf_ops.h.inc\".\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nAcked-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240424173333.96148-2-philmd@linaro.org\u003e\n" }, { "commit": "e0ddabc6d4cfef4a5c7f154f0b0ad00dbf9a18d0", "tree": "f846f108e6961b91f994551cf4f2643001f9e9b6", "parents": [ "a133d207a8fefe934eb808c2b1ee8f2c695cb528" ], "author": { "name": "Zhao Liu", "email": "zhao1.liu@intel.com", "time": "Thu Apr 18 18:04:33 2024 +0800" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return boolean\n\nAs error.h suggested, the best practice for callee is to return\nsomething to indicate success / failure.\n\nWith returned boolean, there\u0027s no need to dereference @errp to check\nfailure case.\n\nSuggested-by: Markus Armbruster \u003carmbru@redhat.com\u003e\nSigned-off-by: Zhao Liu \u003czhao1.liu@intel.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nAcked-by: Jonathan Cameron \u003cJonathan.Cameron@huawei.com\u003e\nMessage-ID: \u003c20240418100433.1085447-4-zhao1.liu@linux.intel.com\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n" }, { "commit": "a133d207a8fefe934eb808c2b1ee8f2c695cb528", "tree": "f4adb830936aa0448de99da4ce7f7594db38710e", "parents": [ "2c5b2d9128b22fa5b8eccc3993170cc49b414d29" ], "author": { "name": "Zhao Liu", "email": "zhao1.liu@intel.com", "time": "Thu Apr 18 18:04:32 2024 +0800" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/cxl/cxl-cdat: Make ct3_build_cdat() return boolean\n\nAs error.h suggested, the best practice for callee is to return\nsomething to indicate success / failure.\n\nSo make ct3_build_cdat() return boolean, and this is the preparation for\ncxl_doe_cdat_init() returning boolean.\n\nSuggested-by: Markus Armbruster \u003carmbru@redhat.com\u003e\nSigned-off-by: Zhao Liu \u003czhao1.liu@intel.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nAcked-by: Jonathan Cameron \u003cJonathan.Cameron@huawei.com\u003e\nMessage-ID: \u003c20240418100433.1085447-3-zhao1.liu@linux.intel.com\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n" }, { "commit": "2c5b2d9128b22fa5b8eccc3993170cc49b414d29", "tree": "0559f36ac5835b46e3c0ffe9887b099d023b3db8", "parents": [ "259181d29f81aa72a489dddc7d59517894b51e0f" ], "author": { "name": "Zhao Liu", "email": "zhao1.liu@intel.com", "time": "Thu Apr 18 18:04:31 2024 +0800" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/cxl/cxl-cdat: Make ct3_load_cdat() return boolean\n\nAs error.h suggested, the best practice for callee is to return\nsomething to indicate success / failure.\n\nSo make ct3_load_cdat() return boolean, and this is the preparation for\ncxl_doe_cdat_init() returning boolean.\n\nSuggested-by: Markus Armbruster \u003carmbru@redhat.com\u003e\nSigned-off-by: Zhao Liu \u003czhao1.liu@intel.com\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nAcked-by: Jonathan Cameron \u003cJonathan.Cameron@huawei.com\u003e\nMessage-ID: \u003c20240418100433.1085447-2-zhao1.liu@linux.intel.com\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n" }, { "commit": "259181d29f81aa72a489dddc7d59517894b51e0f", "tree": "1995d1ab91d6f7771a1d561a9b66a6d2a010249d", "parents": [ "c1c350dc2ccbf92524754694547909e1455e4eef" ], "author": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Apr 15 08:56:55 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw: Add a Kconfig switch for the TYPE_CPU_CLUSTER device\n\nThe cpu-cluster device is only needed for some few arm and riscv\nmachines. Let\u0027s avoid compiling and linking it if it is not really\nnecessary.\n\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\nMessage-ID: \u003c20240415065655.130099-3-thuth@redhat.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n" }, { "commit": "c1c350dc2ccbf92524754694547909e1455e4eef", "tree": "385cc0bed9b4146ec8c826a7bbe72e7a557cd95d", "parents": [ "b8ff846ec88513112008bff3a4001c839fd50f03" ], "author": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Apr 15 08:56:54 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw: Fix problem with the A*MPCORE switches in the Kconfig files\n\nA9MPCORE, ARM11MPCORE and A15MPCORE are defined twice, once in\nhw/cpu/Kconfig and once in hw/arm/Kconfig. This is only possible\nby accident, since hw/cpu/Kconfig is never included from hw/Kconfig.\nFix it by declaring the switches only in hw/cpu/Kconfig (since the\nrelated files reside in the hw/cpu/ folder) and by making sure that\nthe file hw/cpu/Kconfig is now properly included from hw/Kconfig.\n\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\nMessage-ID: \u003c20240415065655.130099-2-thuth@redhat.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n" }, { "commit": "b8ff846ec88513112008bff3a4001c839fd50f03", "tree": "f92ec97f4f0f6a6dd2d0df3dd314ff65a6197dfe", "parents": [ "ca4af17c5e4a55b73850163dfc64a7d3c69378be" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 11 12:33:31 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/riscv/virt: Replace sprintf by g_strdup_printf\n\nsprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1.\nUse g_strdup_printf instead.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\n[rth: Use g_strdup_printf]\nSigned-off-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-Id: \u003c20240412073346.458116-26-richard.henderson@linaro.org\u003e\n" }, { "commit": "ca4af17c5e4a55b73850163dfc64a7d3c69378be", "tree": "995a5a65ccdd9efdc03040ed18541091d839c540", "parents": [ "a6ab7a98c9a8106cb8ef86cbc88a27fe69963423" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 11 12:31:14 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/misc/imx: Replace sprintf() by snprintf()\n\nsprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1,\nresulting in painful developer experience. Use snprintf() instead.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-Id: \u003c20240411104340.6617-6-philmd@linaro.org\u003e\nSigned-off-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n" }, { "commit": "a6ab7a98c9a8106cb8ef86cbc88a27fe69963423", "tree": "c0ce9fe28344489fe3ba9c912b2dbb1d91009cf1", "parents": [ "63073574e8d5551dc31a30b59830b886e9f9dbfe" ], "author": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Mon Apr 08 13:15:44 2024 +0200" }, "committer": { "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org", "time": "Thu Apr 25 12:48:12 2024 +0200" }, "message": "hw/misc/applesmc: Simplify DeviceReset handler\n\nHave applesmc_find_key() return a const pointer.\nSince the returned buffers are not modified in\napplesmc_io_data_write(), it is pointless to\ndelete and re-add the keys in the DeviceReset\nhandler. Add them once in DeviceRealize, and\ndiscard them in the DeviceUnrealize handler.\n\nSigned-off-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-Id: \u003c20240410180819.92332-1-philmd@linaro.org\u003e\n" }, { "commit": "214652da123e3821657a64691ee556281e9f6238", "tree": "a6a189029136fdfdaae85e4f1c81f92d07328adb", "parents": [ "92741432ed6f98ab01bdace5baaf2894c7855563" ], "author": { "name": "Arnaud Minier", "email": "arnaud.minier@telecom-paris.fr", "time": "Fri Mar 29 18:44:02 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:59 2024 +0100" }, "message": "tests/qtest: Add tests for the STM32L4x5 USART\n\nTest:\n- read/write from/to the usart registers\n- send/receive a character/string over the serial port\n\nSigned-off-by: Arnaud Minier \u003carnaud.minier@telecom-paris.fr\u003e\nSigned-off-by: Inès Varhol \u003cines.varhol@telecom-paris.fr\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240329174402.60382-6-arnaud.minier@telecom-paris.fr\n[PMM: fix checkpatch nits, remove commented out code]\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "92741432ed6f98ab01bdace5baaf2894c7855563", "tree": "6ed359600f9a15521ec0f9fc9c99f53490e522fa", "parents": [ "c4c12ee48709aeb896ebb60163e8eb26cdaa3d65" ], "author": { "name": "Arnaud Minier", "email": "arnaud.minier@telecom-paris.fr", "time": "Fri Mar 29 18:44:01 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:59 2024 +0100" }, "message": "hw/arm: Add the USART to the stm32l4x5 SoC\n\nAdd the USART to the SoC and connect it to the other implemented devices.\n\nSigned-off-by: Arnaud Minier \u003carnaud.minier@telecom-paris.fr\u003e\nSigned-off-by: Inès Varhol \u003cines.varhol@telecom-paris.fr\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240329174402.60382-5-arnaud.minier@telecom-paris.fr\n[PMM: fixed a few checkpatch nits]\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "c4c12ee48709aeb896ebb60163e8eb26cdaa3d65", "tree": "87276b3d960a781876d64d485507d04e7dcaa4ee", "parents": [ "87b77e6e01cad9a6cbdc3532a5bb3c674e34d089" ], "author": { "name": "Arnaud Minier", "email": "arnaud.minier@telecom-paris.fr", "time": "Fri Mar 29 18:44:00 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:59 2024 +0100" }, "message": "hw/char/stm32l4x5_usart: Add options for serial parameters setting\n\nAdd a function to change the settings of the\nserial connection.\n\nSigned-off-by: Arnaud Minier \u003carnaud.minier@telecom-paris.fr\u003e\nSigned-off-by: Inès Varhol \u003cines.varhol@telecom-paris.fr\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240329174402.60382-4-arnaud.minier@telecom-paris.fr\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "87b77e6e01cad9a6cbdc3532a5bb3c674e34d089", "tree": "99387faac2ae8d257d39f0162a62c984535c1202", "parents": [ "4fb37aea7e01679db44758eb9407d5a49e3dbd7a" ], "author": { "name": "Arnaud Minier", "email": "arnaud.minier@telecom-paris.fr", "time": "Fri Mar 29 18:43:59 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:59 2024 +0100" }, "message": "hw/char/stm32l4x5_usart: Enable serial read and write\n\nImplement the ability to read and write characters to the\nusart using the serial port.\n\nThe character transmission is based on the\ncmsdk-apb-uart implementation.\n\nSigned-off-by: Arnaud Minier \u003carnaud.minier@telecom-paris.fr\u003e\nSigned-off-by: Inès Varhol \u003cines.varhol@telecom-paris.fr\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240329174402.60382-3-arnaud.minier@telecom-paris.fr\n[PMM: fixed a few checkpatch nits]\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "4fb37aea7e01679db44758eb9407d5a49e3dbd7a", "tree": "e9d4ffe2caecd64d47eed9e5ebcd9fad71e07d1f", "parents": [ "631f46d4ea7cb7ac0e529aacc1e7d832473f96c3" ], "author": { "name": "Arnaud Minier", "email": "arnaud.minier@telecom-paris.fr", "time": "Fri Mar 29 18:43:58 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:59 2024 +0100" }, "message": "hw/char: Implement STM32L4x5 USART skeleton\n\nAdd the basic infrastructure (register read/write, type...)\nto implement the STM32L4x5 USART.\n\nAlso create different types for the USART, UART and LPUART\nof the STM32L4x5 to deduplicate code and enable the\nimplementation of different behaviors depending on the type.\n\nSigned-off-by: Arnaud Minier \u003carnaud.minier@telecom-paris.fr\u003e\nSigned-off-by: Inès Varhol \u003cines.varhol@telecom-paris.fr\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240329174402.60382-2-arnaud.minier@telecom-paris.fr\n[PMM: update to new reset hold method signature;\n fixed a few checkpatch nits]\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "631f46d4ea7cb7ac0e529aacc1e7d832473f96c3", "tree": "9fb50b1412c0c4a12ec3d371b30d65c3556630b5", "parents": [ "41d49ec190db9171d2ebb158fd4d5daad06ed8e1" ], "author": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Fri Apr 12 17:08:09 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:59 2024 +0100" }, "message": "reset: Add RESET_TYPE_SNAPSHOT_LOAD\n\nSome devices and machines need to handle the reset before a vmsave\nsnapshot is loaded differently -- the main user is the handling of\nRNG seed information, which does not want to put a new RNG seed into\na ROM blob when we are doing a snapshot load.\n\nCurrently this kind of reset handling is supported only for:\n * TYPE_MACHINE reset methods, which take a ShutdownCause argument\n * reset functions registered with qemu_register_reset_nosnapshotload\n\nTo allow a three-phase-reset device to also distinguish \"snapshot\nload\" reset from the normal kind, add a new ResetType\nRESET_TYPE_SNAPSHOT_LOAD. All our existing reset methods ignore\nthe reset type, so we don\u0027t need to update any device code.\n\nAdd the enum type, and make qemu_devices_reset() use the\nright reset type for the ShutdownCause it is passed. This\nallows us to get rid of the device_reset_reason global we\nwere using to implement qemu_register_reset_nosnapshotload().\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Luc Michel \u003cluc.michel@amd.com\u003e\nMessage-id: 20240412160809.1260625-7-peter.maydell@linaro.org\n" }, { "commit": "41d49ec190db9171d2ebb158fd4d5daad06ed8e1", "tree": "31e6ba81b225fec4c9e344a6a382bdc42c7d5f6f", "parents": [ "ad80e36744785fe9326d4104d98e976822e90cc2" ], "author": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Fri Apr 12 17:08:08 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:58 2024 +0100" }, "message": "docs/devel/reset: Update to new API for hold and exit phase methods\n\nUpdate the reset documentation\u0027s example code to match the new API\nfor the hold and exit phase method APIs where they take a ResetType\nargument.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Luc Michel \u003cluc.michel@amd.com\u003e\nMessage-id: 20240412160809.1260625-6-peter.maydell@linaro.org\n" }, { "commit": "ad80e36744785fe9326d4104d98e976822e90cc2", "tree": "99c22bd64e751d16bb2438664641baaa9a93a680", "parents": [ "aadea887f4429fcc96429b126c254de94317b474" ], "author": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Fri Apr 12 17:08:07 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:06 2024 +0100" }, "message": "hw, target: Add ResetType argument to hold and exit phase methods\n\nWe pass a ResetType argument to the Resettable class enter\nphase method, but we don\u0027t pass it to hold and exit, even though\nthe callsites have it readily available. This means that if\na device cared about the ResetType it would need to record it\nin the enter phase method to use later on. Pass the type to\nall three of the phase methods to avoid having to do that.\n\nCommit created with\n\n for dir in hw target include; do \\\n spatch --macro-file scripts/cocci-macro-file.h \\\n --sp-file scripts/coccinelle/reset-type.cocci \\\n --keep-comments --smpl-spacing --in-place \\\n --include-headers --dir $dir; done\n\nand no manual edits.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Edgar E. Iglesias \u003cedgar.iglesias@amd.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Luc Michel \u003cluc.michel@amd.com\u003e\nMessage-id: 20240412160809.1260625-5-peter.maydell@linaro.org\n" }, { "commit": "aadea887f4429fcc96429b126c254de94317b474", "tree": "34957bb70596faaa4a6dea5302a3c09e92cb2d07", "parents": [ "ef6ab2922fc94956c0b28c55ec2abe61f71446a9" ], "author": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Fri Apr 12 17:08:06 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:06 2024 +0100" }, "message": "scripts/coccinelle: New script to add ResetType to hold and exit phases\n\nWe pass a ResetType argument to the Resettable class enter phase\nmethod, but we don\u0027t pass it to hold and exit, even though the\ncallsites have it readily available. This means that if a device\ncared about the ResetType it would need to record it in the enter\nphase method to use later on. We should pass the type to all three\nof the phase methods to avoid having to do that.\n\nThis coccinelle script adds the ResetType argument to the hold and\nexit phases of the Resettable interface.\n\nThe first part of the script (rules holdfn_assigned, holdfn_defined,\nexitfn_assigned, exitfn_defined) update implementations of the\ninterface within device models, both to change the signature of their\nmethod implementations and to pass on the reset type when they invoke\nreset on some other device.\n\nThe second part of the script is various special cases:\n * method callsites in resettable_phase_hold(), resettable_phase_exit()\n and device_phases_reset()\n * updating the typedefs for the methods\n * isl_pmbus_vr.c has some code where one device\u0027s reset method directly\n calls the implementation of a different device\u0027s method\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Luc Michel \u003cluc.michel@amd.com\u003e\nMessage-id: 20240412160809.1260625-4-peter.maydell@linaro.org\n" }, { "commit": "ef6ab2922fc94956c0b28c55ec2abe61f71446a9", "tree": "4847b39c3acdd423175126b551852d94d41ce0d1", "parents": [ "1e0f2b38ac104ec3606750cce847cc9d8e4f66ac" ], "author": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Fri Apr 12 17:08:05 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:06 2024 +0100" }, "message": "allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset\n\nRather than directly calling the device\u0027s implementation of its \u0027hold\u0027\nreset phase, call device_cold_reset(). This means we don\u0027t have to\nadjust this callsite when we add another argument to the function\nsignature for the hold and exit reset methods.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Luc Michel \u003cluc.michel@amd.com\u003e\nMessage-id: 20240412160809.1260625-3-peter.maydell@linaro.org\n" }, { "commit": "1e0f2b38ac104ec3606750cce847cc9d8e4f66ac", "tree": "a71e4bc64668da22cfe27c4c629124f368d7c578", "parents": [ "a6819c1bd0b76d7fa0c8f4ae19e4e80dd61a1502" ], "author": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Fri Apr 12 17:08:04 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:06 2024 +0100" }, "message": "hw/misc: Don\u0027t special case RESET_TYPE_COLD in npcm7xx_clk, gcr\n\nThe npcm7xx_clk and npcm7xx_gcr device reset methods look at\nthe ResetType argument and only handle RESET_TYPE_COLD,\nproducing a warning if another reset type is passed. This\nis different from how every other three-phase-reset method\nwe have works, and makes it difficult to add new reset types.\n\nA better pattern is \"assume that any reset type you don\u0027t know\nabout should be handled like RESET_TYPE_COLD\"; switch these\ndevices to do that. Then adding a new reset type will only\nneed to touch those devices where its behaviour really needs\nto be different from the standard cold reset.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nReviewed-by: Luc Michel \u003cluc.michel@amd.com\u003e\nMessage-id: 20240412160809.1260625-2-peter.maydell@linaro.org\n" }, { "commit": "a6819c1bd0b76d7fa0c8f4ae19e4e80dd61a1502", "tree": "baea8d718cb365b231cc98b83b4748c698eaf3d2", "parents": [ "c3a68dfd191682b140951e423b72866102097df9" ], "author": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 11 12:53:13 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:06 2024 +0100" }, "message": "linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code\n\nEver since the bFLT format support was added in 2006, there has been\na chunk of code in the file guarded by CONFIG_BINFMT_SHARED_FLAT\nwhich is supposedly for shared library support. This is not enabled\nand it\u0027s not possible to enable it, because if you do you\u0027ll run into\nthe \"#error needs checking\" in the calc_reloc() function.\n\nSimilarly, CONFIG_BINFMT_ZFLAT exists but can\u0027t be enabled because of\nan \"#error code needs checking\" in load_flat_file().\n\nThis code is obviously unfinished and has never been used; nobody in\nthe intervening 18 years has complained about this or fixed it, so\njust delete the dead code. If anybody ever wants the feature they\ncan always pull it out of git, or (perhaps better) write it from\nscratch based on the current Linux bFLT loader rather than the one of\n18 years ago.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Philippe Mathieu-Daudé \u003cphilmd@linaro.org\u003e\nMessage-id: 20240411115313.680433-1-peter.maydell@linaro.org\n" }, { "commit": "c3a68dfd191682b140951e423b72866102097df9", "tree": "d0bc686df8ef914c999b8dc94005571499e99ac1", "parents": [ "5ae47f7aece19c5a6efbf99d000f389278e93c1d" ], "author": { "name": "Anastasia Belova", "email": "abelova@astralinux.ru", "time": "Tue Apr 09 14:53:01 2024 +0300" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:06 2024 +0100" }, "message": "hw/dma: avoid apparent overflow in soc_dma_set_request\n\nIn soc_dma_set_request() we try to set a bit in a uint64_t, but we\ndo it with \"1 \u003c\u003c ch-\u003enum\", which can\u0027t set any bits past 31;\nany use for a channel number of 32 or more would fail due to\ninteger overflow.\n\nThis doesn\u0027t happen in practice for our current use of this code,\nbecause the worst case is when we call soc_dma_init() with an\nargument of 32 for the number of channels, and QEMU builds with\n-fwrapv so the shift into the sign bit is well-defined. However,\nit\u0027s obviously not the intended behaviour of the code.\n\nAdd casts to force the shift to be done as 64-bit arithmetic,\nallowing up to 64 channels.\n\nFound by Linux Verification Center (linuxtesting.org) with SVACE.\n\nFixes: afbb5194d4 (\"Handle on-chip DMA controllers in one place, convert OMAP DMA to use it.\")\nSigned-off-by: Anastasia Belova \u003cabelova@astralinux.ru\u003e\nMessage-id: 20240409115301.21829-1-abelova@astralinux.ru\n[PMM: Edit commit message to clarify that this doesn\u0027t actually\n bite us in our current usage of this code.]\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "5ae47f7aece19c5a6efbf99d000f389278e93c1d", "tree": "7f5a023be0e8fb56198dde722982a68b45b9b135", "parents": [ "14a164030ada5c5d6f346e152521cb878b142b2a" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:06 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:06 2024 +0100" }, "message": "hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI\n\nIf the CPU implements FEAT_NMI, then turn on the NMI support in the\nGICv3 too. It\u0027s permitted to have a configuration with FEAT_NMI in\nthe CPU (and thus NMI support in the CPU interfaces too) but no NMI\nsupport in the distributor and redistributor, but this isn\u0027t a very\nuseful setup as it\u0027s close to having no NMI support at all.\n\nWe don\u0027t need to gate the enabling of NMI in the GIC behind a\nmachine version property, because none of our current CPUs\nimplement FEAT_NMI, and \u0027-cpu max\u0027 is not something we maintain\nmigration compatibility across versions for. So we can always\nenable the GIC NMI support when the CPU has it.\n\nNeither hvf nor KVM support NMI in the GIC yet, so we don\u0027t enable\nit unless we\u0027re using TCG.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-id: 20240407081733.3231820-25-ruanjinjie@huawei.com\n[PMM: Update comment and commit message]\nSuggested-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "14a164030ada5c5d6f346e152521cb878b142b2a", "tree": "7a64bfa9bdae3d805fa78dd95014cfba146b0976", "parents": [ "c57e81889faa5823d0d47c14a4dfc45914205d71" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:06 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "target/arm: Add FEAT_NMI to max\n\nEnable FEAT_NMI on the \u0027max\u0027 CPU.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-24-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "c57e81889faa5823d0d47c14a4dfc45914205d71", "tree": "2487c8c3c2c7939241407d7f03e970361c46d666", "parents": [ "f3c26a44fe3dc27988f07b7e1c4155b9a55818fc" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:05 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "hw/intc/arm_gicv3: Report the VINMI interrupt\n\nIn vCPU Interface, if the vIRQ has the non-maskable property, report\nvINMI to the corresponding vPE.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-23-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "f3c26a44fe3dc27988f07b7e1c4155b9a55818fc", "tree": "7415670dc4f1a71042bbc3a832b6dc47f8cd744c", "parents": [ "d89daa893f51280652032640d77a8bc1dea95bdd" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:05 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()\n\nIn CPU Interface, if the IRQ has the non-maskable property, report NMI to\nthe corresponding PE.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-22-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "d89daa893f51280652032640d77a8bc1dea95bdd", "tree": "d3bac7181c238c7f9a7269a2deb118be0d70fca7", "parents": [ "d2c0c6aab6c6748726149c37159a75751ec6ac92" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:05 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "hw/intc/arm_gicv3: Implement NMI interrupt priority\n\nIf GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI priority is\nhigher than 0x80, otherwise it is higher than 0x0. And save the interrupt\nnon-maskable property in hppi.nmi to deliver NMI exception. Since both GICR\nand GICD can deliver NMI, it is both necessary to check whether the pending\nirq is NMI in gicv3_redist_update_noirqset and gicv3_update_noirqset.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-21-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "d2c0c6aab6c6748726149c37159a75751ec6ac92", "tree": "41f74d548f2e380b4155aa16ad279e77a0a61ada", "parents": [ "28cca59c469b16f1352e784b566fd36ace2be4b4" ], "author": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Fri Apr 19 14:36:33 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()\n\nImplement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for\nICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit.\n\nIf FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1.NMI\nbit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit\nshould be set or clear according to the Non-maskable property. And the RPR\npriority should also update the NMI bit according to the APR priority NMI bit.\n\nBy the way, add gicv3_icv_nmiar1_read trace event.\n\nIf the hpp irq is a NMI, the icv iar read should return 1022 and trap for\nNMI again\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n[PMM: use cs-\u003enmi_support instead of cs-\u003egic-\u003enmi_support]\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-20-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "28cca59c469b16f1352e784b566fd36ace2be4b4", "tree": "981d70617b07e41128872ef2f5db5ac084b319b5", "parents": [ "44ed1e4b9a4df256bb56487ae5150b6807536703" ], "author": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Fri Apr 19 14:36:00 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "hw/intc/arm_gicv3: Add NMI handling CPU interface registers\n\nAdd the NMIAR CPU interface registers which deal with acknowledging NMI.\n\nWhen introduce NMI interrupt, there are some updates to the semantics for the\nregister ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it\nshould return 1022 if the intid has non-maskable property. And for\nICC_NMIAR1_EL1 register, it should return 1023 if the intid do not have\nnon-maskable property. Howerever, these are not necessary for ICC_HPPIR1_EL1\nregister.\n\nAnd the APR and RPR has NMI bits which should be handled correctly.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\n[PMM: Separate out whether cpuif supports NMI from whether the\n GIC proper (IRI) supports NMI]\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-19-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "44ed1e4b9a4df256bb56487ae5150b6807536703", "tree": "c4e00d1f43dd65a0abbd14061c830fdecfc673bc", "parents": [ "7c79d98d2e4de5b8c919002e6ead6bae7f46003d" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:03 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "hw/intc/arm_gicv3: Implement GICD_INMIR\n\nAdd GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-18-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "7c79d98d2e4de5b8c919002e6ead6bae7f46003d", "tree": "9cc9d82234dffaccb76120fd680ae02f16def59f", "parents": [ "0e9f4e8e7b9e3bde8b8c0a84c577f64c679b535c" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:02 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "hw/intc/arm_gicv3_redist: Implement GICR_INMIR0\n\nAdd GICR_INMIR0 register and support access GICR_INMIR0.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-17-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "0e9f4e8e7b9e3bde8b8c0a84c577f64c679b535c", "tree": "b28564457fa1f56fa01d5fe719adf144e9ac3475", "parents": [ "67d74e4c54236b53917edfa9f52efb4207064014" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:02 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "hw/intc/arm_gicv3: Add irq non-maskable property\n\nA SPI, PPI or SGI interrupt can have non-maskable property. So maintain\nnon-maskable property in PendingIrq and GICR/GICD. Since add new device\nstate, it also needs to be migrated, so also save NMI info in\nvmstate_gicv3_cpu and vmstate_gicv3.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nAcked-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-16-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "67d74e4c54236b53917edfa9f52efb4207064014", "tree": "bebd6e810f12d75e48e785bb4ef63df9ce094c87", "parents": [ "c9e86cbd3400032dc818bf24e823959e565b8b41" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:01 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "hw/intc/arm_gicv3_kvm: Not set has-nmi\u003dtrue for the KVM GICv3\n\nSo far, there is no FEAT_GICv3_NMI support in the in-kernel GIC, so make it\nan error to try to set has-nmi\u003dtrue for the KVM GICv3.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nMessage-id: 20240407081733.3231820-15-ruanjinjie@huawei.com\nSuggested-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "c9e86cbd3400032dc818bf24e823959e565b8b41", "tree": "e3d814800eade504912ed2e164cfd87d73ed1546", "parents": [ "e4eb290571606c5e6dc7739547b5056389cd92fb" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:01 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "hw/intc/arm_gicv3: Add has-nmi property to GICv3 device\n\nAdd a property has-nmi to the GICv3 device, and use this to set\nthe NMI bit in the GICD_TYPER register. This isn\u0027t visible to\nguests yet because the property defaults to false and we won\u0027t\nset it in the board code until we\u0027ve landed all of the changes\nneeded to implement FEAT_GICV3_NMI.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-14-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "e4eb290571606c5e6dc7739547b5056389cd92fb", "tree": "ad04e8c0fe42b2fe0e7d157897a592a1da77d797", "parents": [ "34d94b7af9f1dc4cae550ecc7b825c9567741a12" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:01 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()\n\nAccording to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt\nwith superpriority is always IRQ, never FIQ, so the NMI exception trap entry\nbehave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the\nGIC or come from the hcrx_el2.HCRX_VINMI bit, VFNMI(vFIQ with Superpriority)\ncome from the hcrx_el2.HCRX_VFNMI bit.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-13-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "34d94b7af9f1dc4cae550ecc7b825c9567741a12", "tree": "a8bd90f20c96e361383cf40d7e6b85e858a85bb2", "parents": [ "83f320753827da6bd381b46b8f3e6736046c86cd" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:00 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU\n\nWire the new NMI and VINMI interrupt line from the GIC to each CPU if it\nis not GICv2.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nMessage-id: 20240407081733.3231820-12-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "83f320753827da6bd381b46b8f3e6736046c86cd", "tree": "7da497c74450c92ca42fdbcd47ce4f6008196041", "parents": [ "167f2631df98c5b1af622a9afe3afe00867ef080" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:33:00 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "hw/intc/arm_gicv3: Add external IRQ lines for NMI\n\nAugment the GICv3\u0027s QOM device interface by adding one\nnew set of sysbus IRQ line, to signal NMI to each CPU.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-11-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "167f2631df98c5b1af622a9afe3afe00867ef080", "tree": "ab3326950b993b63d85983ad48302e1ae973b965", "parents": [ "2e0be5f6b122e3dca53b926514287ffcead2689c" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:32:59 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "target/arm: Handle PSTATE.ALLINT on taking an exception\n\nSet or clear PSTATE.ALLINT on taking an exception to ELx according to the\nSCTLR_ELx.SPINTMASK bit.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-10-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "2e0be5f6b122e3dca53b926514287ffcead2689c", "tree": "14ec2a9a8f167556eaec5b5eff5f0a86405c8636", "parents": [ "963e4e3648e0601a8f0b288edaf524b3c98fffbd" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:32:59 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI\n\nAdd IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or\nCPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With\nCPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-9-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "963e4e3648e0601a8f0b288edaf524b3c98fffbd", "tree": "7aadd79606fd1b440b2e1bc975847fd5e7ce06f9", "parents": [ "b36a32ead1596929b1fa5436593d49cac20c20e6" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:32:58 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:05 2024 +0100" }, "message": "target/arm: Add support for NMI in arm_phys_excp_target_el()\n\nAccording to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt\nwith superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in\narm_phys_excp_target_el().\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-8-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "b36a32ead1596929b1fa5436593d49cac20c20e6", "tree": "1f88bca12ff814315bb573fe5088cd01a79f9acc", "parents": [ "5c2169746136ffc93bf1e18c294a05e8446d8af7" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:32:58 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:04 2024 +0100" }, "message": "target/arm: Add support for Non-maskable Interrupt\n\nThis only implements the external delivery method via the GICv3.\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-7-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" }, { "commit": "5c2169746136ffc93bf1e18c294a05e8446d8af7", "tree": "2f12e57d71afaa20d5c689bd15db5e7153202713", "parents": [ "cbf817a2ff7dc12b62e0bccc15ae93369ea5829e" ], "author": { "name": "Jinjie Ruan", "email": "ruanjinjie@huawei.com", "time": "Fri Apr 19 14:32:57 2024 +0100" }, "committer": { "name": "Peter Maydell", "email": "peter.maydell@linaro.org", "time": "Thu Apr 25 10:21:04 2024 +0100" }, "message": "target/arm: Support MSR access to ALLINT\n\nSupport ALLINT msr access as follow:\n\tmrs \u003cxt\u003e, ALLINT\t// read allint\n\tmsr ALLINT, \u003cxt\u003e\t// write allint with imm\n\nSigned-off-by: Jinjie Ruan \u003cruanjinjie@huawei.com\u003e\nReviewed-by: Richard Henderson \u003crichard.henderson@linaro.org\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 20240407081733.3231820-6-ruanjinjie@huawei.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n" } ], "next": "cbf817a2ff7dc12b62e0bccc15ae93369ea5829e" }