)]}'
{
  "commit": "e10de314287c2c14b0e6f0e3e961975ce2f4a83d",
  "tree": "0ae4a1c256c6da2acf8bd5bcc6cd81e575fa1a65",
  "parents": [
    "635de956a7f5a6ffcb04f29d70630c64c717b56b"
  ],
  "author": {
    "name": "Suravee Suthikulpanit",
    "email": "suravee.suthikulpanit@amd.com",
    "time": "Tue May 04 01:52:36 2021 -0500"
  },
  "committer": {
    "name": "Peter Zijlstra",
    "email": "peterz@infradead.org",
    "time": "Thu May 06 15:33:37 2021 +0200"
  },
  "message": "x86/events/amd/iommu: Fix invalid Perf result due to IOMMU PMC power-gating\n\nOn certain AMD platforms, when the IOMMU performance counter source\n(csource) field is zero, power-gating for the counter is enabled, which\nprevents write access and returns zero for read access.\n\nThis can cause invalid perf result especially when event multiplexing\nis needed (i.e. more number of events than available counters) since\nthe current logic keeps track of the previously read counter value,\nand subsequently re-program the counter to continue counting the event.\nWith power-gating enabled, we cannot gurantee successful re-programming\nof the counter.\n\nWorkaround this issue by :\n\n1. Modifying the ordering of setting/reading counters and enabing/\n   disabling csources to only access the counter when the csource\n   is set to non-zero.\n\n2. Since AMD IOMMU PMU does not support interrupt mode, the logic\n   can be simplified to always start counting with value zero,\n   and accumulate the counter value when stopping without the need\n   to keep track and reprogram the counter with the previously read\n   counter value.\n\nThis has been tested on systems with and without power-gating.\n\nFixes: 994d6608efe4 (\"iommu/amd: Remove performance counter pre-initialization test\")\nSuggested-by: Alexander Monakov \u003camonakov@ispras.ru\u003e\nSigned-off-by: Suravee Suthikulpanit \u003csuravee.suthikulpanit@amd.com\u003e\nSigned-off-by: Peter Zijlstra (Intel) \u003cpeterz@infradead.org\u003e\nLink: https://lkml.kernel.org/r/20210504065236.4415-1-suravee.suthikulpanit@amd.com\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6a98a7651621428d46190e5845d38b8829966161",
      "old_mode": 33188,
      "old_path": "arch/x86/events/amd/iommu.c",
      "new_id": "2da6139b0977fc986a0647aee60859a3bfe1b29b",
      "new_mode": 33188,
      "new_path": "arch/x86/events/amd/iommu.c"
    }
  ]
}