)]}'
{
  "commit": "827751b699b79a6e569983359c02dce67f81b94c",
  "tree": "bb42ac375bb79d1ad6f73c5c6ef1bec0fae21e7b",
  "parents": [
    "1235ff329981ecde9ccbf49b83bd4d71e827d541",
    "b94cec5761d22624d109d859467d7d4ce0a1b88b"
  ],
  "author": {
    "name": "Linus Torvalds",
    "email": "torvalds@linux-foundation.org",
    "time": "Fri Sep 11 13:15:13 2026 -0700"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@linux-foundation.org",
    "time": "Fri Sep 11 13:15:13 2026 -0700"
  },
  "message": "Merge tag \u0027riscv-for-linus-7.3-rc3\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux\n\nPull RISC-V fixes from Paul Walmsley:\n \"From a RISC-V point of view, there\u0027s one notable fix here, reverting\n  an earlier bogus fix to the pointer masking code. Fortunately the\n  practical impact appears to be small.\n\n   - Revert a bad fix, likely LLM-generated, in the pointer masking code\n     that confused the RISC-V hardware pointer masking implementation\n     with the Linux kernel tagged address feature\n\n   - Fix unexpected faults caused by kprobe instruction slot writes when\n     !CONFIG_STRICT_MODULE_RWX\n\n   - Fix unexpected faults on minimal configurations during runtime code\n     patching on !CONFIG_STRICT_MODULE_RWX systems\n\n   - Fix a misplaced variable clear causing incorrect reuse of previous\n     values in the RISC-V hardware feature probing code\n\n   - Fix two bugs in the PMU SBI perf code on rv32: use BIT_ULL rather\n     than BIT on 64-bit masks; and use a bitmap rather than an unsigned\n     long on a quantity that can exceed 32 bits\n\n  And a few miscellaneous cleanups:\n\n   - Avoid a potential dereference-before-NULL-pointer-check bug in the\n     PMU SBI perf driver\n\n   - Use CONFIG_GENERIC_BUG_RELATIVE_POINTERS to simplify the rv32 bug\n     table code (like x86 and PPC)\n\n   - Report the RISC-V standard ISA extensions Z[v]fhmin when support is\n     claimed for the superset RISC-V standard ISA extensions Z[v]fh; and\n     simplify our FPU test code to only check for the presence of the D\n     extension\n\n   - Use an existing kernel string helper in place of some open-coded\n     code in kernel/usercfi.c\n\n   - Fix some yamllint issues in the RISC-V DT bindings for CPUs\n\n   - Convert one use of __ASSEMBLY__ to __ASSEMBLER__ that snuck into\n     the RISC-V CFI selftest code\n\n   - Update the translation for the simplified Chinese translation of\n     the RISC-V kernel patch acceptance policy\"\n\n* tag \u0027riscv-for-linus-7.3-rc3\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:\n  riscv: skip software algning code for HAVE_EFFICIENT_UNALIGNED_ACCESS\n  kselftest/riscv: Replace __ASSEMBLY__ with __ASSEMBLER__\n  docs/zh_CN: Update arch/riscv/patch-acceptance.rst translation\n  dt-bindings: riscv: cpus: Fix yamllint style issues\n  riscv: hwprobe: simplify has_fpu() to check D extension only\n  perf: RISC-V: check cpu_hw_evt before dereference in overflow IRQ\n  riscv: report Zfhmin/Zvfhmin when Zfh/Zvfh are present\n  perf: RISC-V: store available counter mask as bitmap\n  perf: RISC-V: use BIT_ULL for u64 overflow masks\n  riscv: bug: Make RV32 use GENERIC_BUG_RELATIVE_POINTERS\n  riscv: hwprobe: initialize pair-\u003evalue in hwprobe_one_pair()\n  riscv: use string helper in setup_global_riscv_enable()\n  Revert \"riscv: Reset pmm when PR_TAGGED_ADDR_ENABLE is not set\"\n  riscv: patch: skip fixmap mapping when kernel text is already writable\n  riscv: mm: make EXECMEM_KPROBES writable without CONFIG_STRICT_MODULE_RWX\n",
  "tree_diff": []
}