)]}'
{
  "commit": "dc44abd6aad22411f7f9890e39fd4753dabf0d03",
  "tree": "59b781f47746712e02890d0b3917b9581e0320a3",
  "parents": [
    "0ae3abcda2dc5fe0130e3261da8a89489fff3e0e"
  ],
  "author": {
    "name": "James Hogan",
    "email": "james.hogan@imgtec.com",
    "time": "Tue Mar 14 17:00:08 2017 +0000"
  },
  "committer": {
    "name": "James Hogan",
    "email": "james.hogan@imgtec.com",
    "time": "Tue Mar 28 16:31:37 2017 +0100"
  },
  "message": "KVM: MIPS/Emulate: Properly implement TLBR for T\u0026E\n\nProperly implement emulation of the TLBR instruction for Trap \u0026 Emulate.\nThis instruction reads the TLB entry pointed at by the CP0_Index\nregister into the other TLB registers, which may have the side effect of\nchanging the current ASID. Therefore abstract the CP0_EntryHi and ASID\nchanging code into a common function in the process.\n\nA comment indicated that Linux doesn\u0027t use TLBR, which is true during\nnormal use, however dumping of the TLB does use it (for example with the\nrelatively recent \u0027x\u0027 magic sysrq key), as does a wired TLB entries test\ncase in my KVM tests.\n\nSigned-off-by: James Hogan \u003cjames.hogan@imgtec.com\u003e\nAcked-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nCc: \"Radim Krčmář\" \u003crkrcmar@redhat.com\u003e\nCc: linux-mips@linux-mips.org\nCc: kvm@vger.kernel.org\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4833ebad89d9b875971c19e47256fb599f605a99",
      "old_mode": 33188,
      "old_path": "arch/mips/kvm/emulate.c",
      "new_id": "34e78a3ee9d79ece862574274f4ce11fcf3e6d7a",
      "new_mode": 33188,
      "new_path": "arch/mips/kvm/emulate.c"
    }
  ]
}