/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * Device Tree file for Marvell Armada CP110 Slave.
 */

#define ICU_GRP_NSR 0x0

/ {
	cp110-slave {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&cps_icu>;
		ranges;

		config-space@f4000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0x0 0x0 0xf4000000 0x2000000>;

			cps_ethernet: ethernet@0 {
				compatible = "marvell,armada-7k-pp22";
				reg = <0x0 0x100000>, <0x129000 0xb000>;
				clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
				clock-names = "pp_clk", "gop_clk", "mg_clk";
				marvell,system-controller = <&cps_syscon0>;
				status = "disabled";
				dma-coherent;

				cps_eth0: eth0 {
					interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
							  "tx-cpu3", "rx-shared";
					port-id = <0>;
					gop-port-id = <0>;
					status = "disabled";
				};

				cps_eth1: eth1 {
					interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
							  "tx-cpu3", "rx-shared";
					port-id = <1>;
					gop-port-id = <2>;
					status = "disabled";
				};

				cps_eth2: eth2 {
					interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
					interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
							  "tx-cpu3", "rx-shared";
					port-id = <2>;
					gop-port-id = <3>;
					status = "disabled";
				};
			};

			cps_mdio: mdio@12a200 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x12a200 0x10>;
				clocks = <&cps_clk 1 9>, <&cps_clk 1 5>;
				status = "disabled";
			};

			cps_xmdio: mdio@12a600 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,xmdio";
				reg = <0x12a600 0x10>;
				status = "disabled";
			};

			cps_icu: interrupt-controller@1e0000 {
				compatible = "marvell,cp110-icu";
				reg = <0x1e0000 0x10>;
				#interrupt-cells = <3>;
				interrupt-controller;
				msi-parent = <&gicp>;
			};

			cps_rtc: rtc@284000 {
				compatible = "marvell,armada-8k-rtc";
				reg = <0x284000 0x20>, <0x284080 0x24>;
				reg-names = "rtc", "rtc-soc";
				interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
			};

			cps_syscon0: system-controller@440000 {
				compatible = "syscon", "simple-mfd";
				reg = <0x440000 0x1000>;

				cps_clk: clock {
					compatible = "marvell,cp110-clock";
					#clock-cells = <2>;
				};

				cps_gpio1: gpio@100 {
					compatible = "marvell,armada-8k-gpio";
					offset = <0x100>;
					ngpios = <32>;
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&cps_pinctrl 0 0 32>;
					interrupt-controller;
					interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
					status = "disabled";
				};

				cps_gpio2: gpio@140 {
					compatible = "marvell,armada-8k-gpio";
					offset = <0x140>;
					ngpios = <31>;
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&cps_pinctrl 0 32 31>;
					interrupt-controller;
					interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
						     <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
					status = "disabled";
				};

			};

			cps_usb3_0: usb3@500000 {
				compatible = "marvell,armada-8k-xhci",
					     "generic-xhci";
				reg = <0x500000 0x4000>;
				dma-coherent;
				interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_clk 1 22>;
				status = "disabled";
			};

			cps_usb3_1: usb3@510000 {
				compatible = "marvell,armada-8k-xhci",
					     "generic-xhci";
				reg = <0x510000 0x4000>;
				dma-coherent;
				interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_clk 1 23>;
				status = "disabled";
			};

			cps_sata0: sata@540000 {
				compatible = "marvell,armada-8k-ahci",
					     "generic-ahci";
				reg = <0x540000 0x30000>;
				interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_clk 1 15>;
				status = "disabled";
			};

			cps_xor0: xor@6a0000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x6a0000 0x1000>,
				      <0x6b0000 0x1000>;
				dma-coherent;
				msi-parent = <&gic_v2m0>;
				clocks = <&cps_clk 1 8>;
			};

			cps_xor1: xor@6c0000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x6c0000 0x1000>,
				      <0x6d0000 0x1000>;
				dma-coherent;
				msi-parent = <&gic_v2m0>;
				clocks = <&cps_clk 1 7>;
			};

			cps_spi0: spi@700600 {
				compatible = "marvell,armada-380-spi";
				reg = <0x700600 0x50>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				cell-index = <3>;
				clocks = <&cps_clk 1 21>;
				status = "disabled";
			};

			cps_spi1: spi@700680 {
				compatible = "marvell,armada-380-spi";
				reg = <0x700680 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <4>;
				clocks = <&cps_clk 1 21>;
				status = "disabled";
			};

			cps_i2c0: i2c@701000 {
				compatible = "marvell,mv78230-i2c";
				reg = <0x701000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_clk 1 21>;
				status = "disabled";
			};

			cps_i2c1: i2c@701100 {
				compatible = "marvell,mv78230-i2c";
				reg = <0x701100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_clk 1 21>;
				status = "disabled";
			};

			cps_nand: nand@720000 {
				/*
				 * Due to the limiation of the pin available
				 * this controller is only usable on the CPM
				 * for A7K and on the CPS for A8K.
				 */
				compatible = "marvell,armada370-nand";
				reg = <0x720000 0x54>;
				#address-cells = <1>;
				#size-cells = <1>;
				interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_clk 1 2>;
				status = "disabled";
			};

			cps_trng: trng@760000 {
				compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
				reg = <0x760000 0x7d>;
				interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_clk 1 25>;
				status = "okay";
			};

			cps_crypto: crypto@800000 {
				compatible = "inside-secure,safexcel-eip197";
				reg = <0x800000 0x200000>;
				interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
					     <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
					     <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
					     <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
					     <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
					     <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "mem", "ring0", "ring1",
						  "ring2", "ring3", "eip";
				clocks = <&cps_clk 1 26>;
				dma-coherent;
				/*
				 * The cryptographic engine found on the cp110
				 * master is enabled by default at the SoC
				 * level. Because it is not possible as of now
				 * to enable two cryptographic engines in
				 * parallel, disable this one by default.
				 */
				status = "disabled";
			};
		};

		cps_pcie0: pcie@f4600000 {
			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
			reg = <0 0xf4600000 0 0x10000>,
			      <0 0xfaf00000 0 0x80000>;
			reg-names = "ctrl", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			dma-coherent;
			msi-parent = <&gic_v2m0>;

			bus-range = <0 0xff>;
			ranges =
				/* downstream I/O */
				<0x81000000 0 0xfd000000 0  0xfd000000 0 0x10000
				/* non-prefetchable memory */
				0x82000000 0 0xfa000000 0  0xfa000000 0 0xf00000>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
			num-lanes = <1>;
			clocks = <&cps_clk 1 13>;
			status = "disabled";
		};

		cps_pcie1: pcie@f4620000 {
			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
			reg = <0 0xf4620000 0 0x10000>,
			      <0 0xfbf00000 0 0x80000>;
			reg-names = "ctrl", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			dma-coherent;
			msi-parent = <&gic_v2m0>;

			bus-range = <0 0xff>;
			ranges =
				/* downstream I/O */
				<0x81000000 0 0xfd010000 0  0xfd010000 0 0x10000
				/* non-prefetchable memory */
				0x82000000 0 0xfb000000 0  0xfb000000 0 0xf00000>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;

			num-lanes = <1>;
			clocks = <&cps_clk 1 11>;
			status = "disabled";
		};

		cps_pcie2: pcie@f4640000 {
			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
			reg = <0 0xf4640000 0 0x10000>,
			      <0 0xfcf00000 0 0x80000>;
			reg-names = "ctrl", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			dma-coherent;
			msi-parent = <&gic_v2m0>;

			bus-range = <0 0xff>;
			ranges =
				/* downstream I/O */
				<0x81000000 0 0xfd020000 0  0xfd020000 0 0x10000
				/* non-prefetchable memory */
				0x82000000 0 0xfc000000 0  0xfc000000 0 0xf00000>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;

			num-lanes = <1>;
			clocks = <&cps_clk 1 12>;
			status = "disabled";
		};
	};
};