| /* |
| !* This file was automatically generated by /n/asic/bin/reg_macro_gen |
| !* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'. |
| !* Editing within this file is thus not recommended, |
| !* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead. |
| !*/ |
| |
| |
| /* |
| !* Bus interface configuration registers |
| !*/ |
| |
| #define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000) |
| #define R_WAITSTATES__pcs4_7_zw__BITNR 30 |
| #define R_WAITSTATES__pcs4_7_zw__WIDTH 2 |
| #define R_WAITSTATES__pcs4_7_ew__BITNR 28 |
| #define R_WAITSTATES__pcs4_7_ew__WIDTH 2 |
| #define R_WAITSTATES__pcs4_7_lw__BITNR 24 |
| #define R_WAITSTATES__pcs4_7_lw__WIDTH 4 |
| #define R_WAITSTATES__pcs0_3_zw__BITNR 22 |
| #define R_WAITSTATES__pcs0_3_zw__WIDTH 2 |
| #define R_WAITSTATES__pcs0_3_ew__BITNR 20 |
| #define R_WAITSTATES__pcs0_3_ew__WIDTH 2 |
| #define R_WAITSTATES__pcs0_3_lw__BITNR 16 |
| #define R_WAITSTATES__pcs0_3_lw__WIDTH 4 |
| #define R_WAITSTATES__sram_zw__BITNR 14 |
| #define R_WAITSTATES__sram_zw__WIDTH 2 |
| #define R_WAITSTATES__sram_ew__BITNR 12 |
| #define R_WAITSTATES__sram_ew__WIDTH 2 |
| #define R_WAITSTATES__sram_lw__BITNR 8 |
| #define R_WAITSTATES__sram_lw__WIDTH 4 |
| #define R_WAITSTATES__flash_zw__BITNR 6 |
| #define R_WAITSTATES__flash_zw__WIDTH 2 |
| #define R_WAITSTATES__flash_ew__BITNR 4 |
| #define R_WAITSTATES__flash_ew__WIDTH 2 |
| #define R_WAITSTATES__flash_lw__BITNR 0 |
| #define R_WAITSTATES__flash_lw__WIDTH 4 |
| |
| #define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004) |
| #define R_BUS_CONFIG__sram_type__BITNR 9 |
| #define R_BUS_CONFIG__sram_type__WIDTH 1 |
| #define R_BUS_CONFIG__sram_type__cwe 1 |
| #define R_BUS_CONFIG__sram_type__bwe 0 |
| #define R_BUS_CONFIG__dma_burst__BITNR 8 |
| #define R_BUS_CONFIG__dma_burst__WIDTH 1 |
| #define R_BUS_CONFIG__dma_burst__burst16 1 |
| #define R_BUS_CONFIG__dma_burst__burst32 0 |
| #define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 |
| #define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1 |
| #define R_BUS_CONFIG__pcs4_7_wr__ext 1 |
| #define R_BUS_CONFIG__pcs4_7_wr__norm 0 |
| #define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 |
| #define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1 |
| #define R_BUS_CONFIG__pcs0_3_wr__ext 1 |
| #define R_BUS_CONFIG__pcs0_3_wr__norm 0 |
| #define R_BUS_CONFIG__sram_wr__BITNR 5 |
| #define R_BUS_CONFIG__sram_wr__WIDTH 1 |
| #define R_BUS_CONFIG__sram_wr__ext 1 |
| #define R_BUS_CONFIG__sram_wr__norm 0 |
| #define R_BUS_CONFIG__flash_wr__BITNR 4 |
| #define R_BUS_CONFIG__flash_wr__WIDTH 1 |
| #define R_BUS_CONFIG__flash_wr__ext 1 |
| #define R_BUS_CONFIG__flash_wr__norm 0 |
| #define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 |
| #define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1 |
| #define R_BUS_CONFIG__pcs4_7_bw__bw32 1 |
| #define R_BUS_CONFIG__pcs4_7_bw__bw16 0 |
| #define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 |
| #define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1 |
| #define R_BUS_CONFIG__pcs0_3_bw__bw32 1 |
| #define R_BUS_CONFIG__pcs0_3_bw__bw16 0 |
| #define R_BUS_CONFIG__sram_bw__BITNR 1 |
| #define R_BUS_CONFIG__sram_bw__WIDTH 1 |
| #define R_BUS_CONFIG__sram_bw__bw32 1 |
| #define R_BUS_CONFIG__sram_bw__bw16 0 |
| #define R_BUS_CONFIG__flash_bw__BITNR 0 |
| #define R_BUS_CONFIG__flash_bw__WIDTH 1 |
| #define R_BUS_CONFIG__flash_bw__bw32 1 |
| #define R_BUS_CONFIG__flash_bw__bw16 0 |
| |
| #define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004) |
| #define R_BUS_STATUS__pll_lock_tm__BITNR 5 |
| #define R_BUS_STATUS__pll_lock_tm__WIDTH 1 |
| #define R_BUS_STATUS__pll_lock_tm__expired 0 |
| #define R_BUS_STATUS__pll_lock_tm__counting 1 |
| #define R_BUS_STATUS__both_faults__BITNR 4 |
| #define R_BUS_STATUS__both_faults__WIDTH 1 |
| #define R_BUS_STATUS__both_faults__no 0 |
| #define R_BUS_STATUS__both_faults__yes 1 |
| #define R_BUS_STATUS__bsen___BITNR 3 |
| #define R_BUS_STATUS__bsen___WIDTH 1 |
| #define R_BUS_STATUS__bsen___enable 0 |
| #define R_BUS_STATUS__bsen___disable 1 |
| #define R_BUS_STATUS__boot__BITNR 1 |
| #define R_BUS_STATUS__boot__WIDTH 2 |
| #define R_BUS_STATUS__boot__uncached 0 |
| #define R_BUS_STATUS__boot__serial 1 |
| #define R_BUS_STATUS__boot__network 2 |
| #define R_BUS_STATUS__boot__parallel 3 |
| #define R_BUS_STATUS__flashw__BITNR 0 |
| #define R_BUS_STATUS__flashw__WIDTH 1 |
| #define R_BUS_STATUS__flashw__bw32 1 |
| #define R_BUS_STATUS__flashw__bw16 0 |
| |
| #define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) |
| #define R_DRAM_TIMING__sdram__BITNR 31 |
| #define R_DRAM_TIMING__sdram__WIDTH 1 |
| #define R_DRAM_TIMING__sdram__enable 1 |
| #define R_DRAM_TIMING__sdram__disable 0 |
| #define R_DRAM_TIMING__ref__BITNR 14 |
| #define R_DRAM_TIMING__ref__WIDTH 2 |
| #define R_DRAM_TIMING__ref__e52us 0 |
| #define R_DRAM_TIMING__ref__e13us 1 |
| #define R_DRAM_TIMING__ref__e8700ns 2 |
| #define R_DRAM_TIMING__ref__disable 3 |
| #define R_DRAM_TIMING__rp__BITNR 12 |
| #define R_DRAM_TIMING__rp__WIDTH 2 |
| #define R_DRAM_TIMING__rs__BITNR 10 |
| #define R_DRAM_TIMING__rs__WIDTH 2 |
| #define R_DRAM_TIMING__rh__BITNR 8 |
| #define R_DRAM_TIMING__rh__WIDTH 2 |
| #define R_DRAM_TIMING__w__BITNR 7 |
| #define R_DRAM_TIMING__w__WIDTH 1 |
| #define R_DRAM_TIMING__w__norm 0 |
| #define R_DRAM_TIMING__w__ext 1 |
| #define R_DRAM_TIMING__c__BITNR 6 |
| #define R_DRAM_TIMING__c__WIDTH 1 |
| #define R_DRAM_TIMING__c__norm 0 |
| #define R_DRAM_TIMING__c__ext 1 |
| #define R_DRAM_TIMING__cz__BITNR 4 |
| #define R_DRAM_TIMING__cz__WIDTH 2 |
| #define R_DRAM_TIMING__cp__BITNR 2 |
| #define R_DRAM_TIMING__cp__WIDTH 2 |
| #define R_DRAM_TIMING__cw__BITNR 0 |
| #define R_DRAM_TIMING__cw__WIDTH 2 |
| |
| #define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) |
| #define R_SDRAM_TIMING__sdram__BITNR 31 |
| #define R_SDRAM_TIMING__sdram__WIDTH 1 |
| #define R_SDRAM_TIMING__sdram__enable 1 |
| #define R_SDRAM_TIMING__sdram__disable 0 |
| #define R_SDRAM_TIMING__mrs_data__BITNR 16 |
| #define R_SDRAM_TIMING__mrs_data__WIDTH 15 |
| #define R_SDRAM_TIMING__ref__BITNR 14 |
| #define R_SDRAM_TIMING__ref__WIDTH 2 |
| #define R_SDRAM_TIMING__ref__e52us 0 |
| #define R_SDRAM_TIMING__ref__e13us 1 |
| #define R_SDRAM_TIMING__ref__e6500ns 2 |
| #define R_SDRAM_TIMING__ref__disable 3 |
| #define R_SDRAM_TIMING__ddr__BITNR 13 |
| #define R_SDRAM_TIMING__ddr__WIDTH 1 |
| #define R_SDRAM_TIMING__ddr__on 1 |
| #define R_SDRAM_TIMING__ddr__off 0 |
| #define R_SDRAM_TIMING__clk100__BITNR 12 |
| #define R_SDRAM_TIMING__clk100__WIDTH 1 |
| #define R_SDRAM_TIMING__clk100__on 1 |
| #define R_SDRAM_TIMING__clk100__off 0 |
| #define R_SDRAM_TIMING__ps__BITNR 11 |
| #define R_SDRAM_TIMING__ps__WIDTH 1 |
| #define R_SDRAM_TIMING__ps__on 1 |
| #define R_SDRAM_TIMING__ps__off 0 |
| #define R_SDRAM_TIMING__cmd__BITNR 9 |
| #define R_SDRAM_TIMING__cmd__WIDTH 2 |
| #define R_SDRAM_TIMING__cmd__pre 3 |
| #define R_SDRAM_TIMING__cmd__ref 2 |
| #define R_SDRAM_TIMING__cmd__mrs 1 |
| #define R_SDRAM_TIMING__cmd__nop 0 |
| #define R_SDRAM_TIMING__pde__BITNR 8 |
| #define R_SDRAM_TIMING__pde__WIDTH 1 |
| #define R_SDRAM_TIMING__rc__BITNR 6 |
| #define R_SDRAM_TIMING__rc__WIDTH 2 |
| #define R_SDRAM_TIMING__rp__BITNR 4 |
| #define R_SDRAM_TIMING__rp__WIDTH 2 |
| #define R_SDRAM_TIMING__rcd__BITNR 2 |
| #define R_SDRAM_TIMING__rcd__WIDTH 2 |
| #define R_SDRAM_TIMING__cl__BITNR 0 |
| #define R_SDRAM_TIMING__cl__WIDTH 2 |
| |
| #define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) |
| #define R_DRAM_CONFIG__wmm1__BITNR 31 |
| #define R_DRAM_CONFIG__wmm1__WIDTH 1 |
| #define R_DRAM_CONFIG__wmm1__wmm 1 |
| #define R_DRAM_CONFIG__wmm1__norm 0 |
| #define R_DRAM_CONFIG__wmm0__BITNR 30 |
| #define R_DRAM_CONFIG__wmm0__WIDTH 1 |
| #define R_DRAM_CONFIG__wmm0__wmm 1 |
| #define R_DRAM_CONFIG__wmm0__norm 0 |
| #define R_DRAM_CONFIG__sh1__BITNR 27 |
| #define R_DRAM_CONFIG__sh1__WIDTH 3 |
| #define R_DRAM_CONFIG__sh0__BITNR 24 |
| #define R_DRAM_CONFIG__sh0__WIDTH 3 |
| #define R_DRAM_CONFIG__w__BITNR 23 |
| #define R_DRAM_CONFIG__w__WIDTH 1 |
| #define R_DRAM_CONFIG__w__bw16 0 |
| #define R_DRAM_CONFIG__w__bw32 1 |
| #define R_DRAM_CONFIG__c__BITNR 22 |
| #define R_DRAM_CONFIG__c__WIDTH 1 |
| #define R_DRAM_CONFIG__c__byte 0 |
| #define R_DRAM_CONFIG__c__bank 1 |
| #define R_DRAM_CONFIG__e__BITNR 21 |
| #define R_DRAM_CONFIG__e__WIDTH 1 |
| #define R_DRAM_CONFIG__e__fast 0 |
| #define R_DRAM_CONFIG__e__edo 1 |
| #define R_DRAM_CONFIG__group_sel__BITNR 16 |
| #define R_DRAM_CONFIG__group_sel__WIDTH 5 |
| #define R_DRAM_CONFIG__group_sel__grp0 0 |
| #define R_DRAM_CONFIG__group_sel__grp1 1 |
| #define R_DRAM_CONFIG__group_sel__bit9 9 |
| #define R_DRAM_CONFIG__group_sel__bit10 10 |
| #define R_DRAM_CONFIG__group_sel__bit11 11 |
| #define R_DRAM_CONFIG__group_sel__bit12 12 |
| #define R_DRAM_CONFIG__group_sel__bit13 13 |
| #define R_DRAM_CONFIG__group_sel__bit14 14 |
| #define R_DRAM_CONFIG__group_sel__bit15 15 |
| #define R_DRAM_CONFIG__group_sel__bit16 16 |
| #define R_DRAM_CONFIG__group_sel__bit17 17 |
| #define R_DRAM_CONFIG__group_sel__bit18 18 |
| #define R_DRAM_CONFIG__group_sel__bit19 19 |
| #define R_DRAM_CONFIG__group_sel__bit20 20 |
| #define R_DRAM_CONFIG__group_sel__bit21 21 |
| #define R_DRAM_CONFIG__group_sel__bit22 22 |
| #define R_DRAM_CONFIG__group_sel__bit23 23 |
| #define R_DRAM_CONFIG__group_sel__bit24 24 |
| #define R_DRAM_CONFIG__group_sel__bit25 25 |
| #define R_DRAM_CONFIG__group_sel__bit26 26 |
| #define R_DRAM_CONFIG__group_sel__bit27 27 |
| #define R_DRAM_CONFIG__group_sel__bit28 28 |
| #define R_DRAM_CONFIG__group_sel__bit29 29 |
| #define R_DRAM_CONFIG__ca1__BITNR 13 |
| #define R_DRAM_CONFIG__ca1__WIDTH 3 |
| #define R_DRAM_CONFIG__bank23sel__BITNR 8 |
| #define R_DRAM_CONFIG__bank23sel__WIDTH 5 |
| #define R_DRAM_CONFIG__bank23sel__bank0 0 |
| #define R_DRAM_CONFIG__bank23sel__bank1 1 |
| #define R_DRAM_CONFIG__bank23sel__bit9 9 |
| #define R_DRAM_CONFIG__bank23sel__bit10 10 |
| #define R_DRAM_CONFIG__bank23sel__bit11 11 |
| #define R_DRAM_CONFIG__bank23sel__bit12 12 |
| #define R_DRAM_CONFIG__bank23sel__bit13 13 |
| #define R_DRAM_CONFIG__bank23sel__bit14 14 |
| #define R_DRAM_CONFIG__bank23sel__bit15 15 |
| #define R_DRAM_CONFIG__bank23sel__bit16 16 |
| #define R_DRAM_CONFIG__bank23sel__bit17 17 |
| #define R_DRAM_CONFIG__bank23sel__bit18 18 |
| #define R_DRAM_CONFIG__bank23sel__bit19 19 |
| #define R_DRAM_CONFIG__bank23sel__bit20 20 |
| #define R_DRAM_CONFIG__bank23sel__bit21 21 |
| #define R_DRAM_CONFIG__bank23sel__bit22 22 |
| #define R_DRAM_CONFIG__bank23sel__bit23 23 |
| #define R_DRAM_CONFIG__bank23sel__bit24 24 |
| #define R_DRAM_CONFIG__bank23sel__bit25 25 |
| #define R_DRAM_CONFIG__bank23sel__bit26 26 |
| #define R_DRAM_CONFIG__bank23sel__bit27 27 |
| #define R_DRAM_CONFIG__bank23sel__bit28 28 |
| #define R_DRAM_CONFIG__bank23sel__bit29 29 |
| #define R_DRAM_CONFIG__ca0__BITNR 5 |
| #define R_DRAM_CONFIG__ca0__WIDTH 3 |
| #define R_DRAM_CONFIG__bank01sel__BITNR 0 |
| #define R_DRAM_CONFIG__bank01sel__WIDTH 5 |
| #define R_DRAM_CONFIG__bank01sel__bank0 0 |
| #define R_DRAM_CONFIG__bank01sel__bank1 1 |
| #define R_DRAM_CONFIG__bank01sel__bit9 9 |
| #define R_DRAM_CONFIG__bank01sel__bit10 10 |
| #define R_DRAM_CONFIG__bank01sel__bit11 11 |
| #define R_DRAM_CONFIG__bank01sel__bit12 12 |
| #define R_DRAM_CONFIG__bank01sel__bit13 13 |
| #define R_DRAM_CONFIG__bank01sel__bit14 14 |
| #define R_DRAM_CONFIG__bank01sel__bit15 15 |
| #define R_DRAM_CONFIG__bank01sel__bit16 16 |
| #define R_DRAM_CONFIG__bank01sel__bit17 17 |
| #define R_DRAM_CONFIG__bank01sel__bit18 18 |
| #define R_DRAM_CONFIG__bank01sel__bit19 19 |
| #define R_DRAM_CONFIG__bank01sel__bit20 20 |
| #define R_DRAM_CONFIG__bank01sel__bit21 21 |
| #define R_DRAM_CONFIG__bank01sel__bit22 22 |
| #define R_DRAM_CONFIG__bank01sel__bit23 23 |
| #define R_DRAM_CONFIG__bank01sel__bit24 24 |
| #define R_DRAM_CONFIG__bank01sel__bit25 25 |
| #define R_DRAM_CONFIG__bank01sel__bit26 26 |
| #define R_DRAM_CONFIG__bank01sel__bit27 27 |
| #define R_DRAM_CONFIG__bank01sel__bit28 28 |
| #define R_DRAM_CONFIG__bank01sel__bit29 29 |
| |
| #define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) |
| #define R_SDRAM_CONFIG__wmm1__BITNR 31 |
| #define R_SDRAM_CONFIG__wmm1__WIDTH 1 |
| #define R_SDRAM_CONFIG__wmm1__wmm 1 |
| #define R_SDRAM_CONFIG__wmm1__norm 0 |
| #define R_SDRAM_CONFIG__wmm0__BITNR 30 |
| #define R_SDRAM_CONFIG__wmm0__WIDTH 1 |
| #define R_SDRAM_CONFIG__wmm0__wmm 1 |
| #define R_SDRAM_CONFIG__wmm0__norm 0 |
| #define R_SDRAM_CONFIG__sh1__BITNR 27 |
| #define R_SDRAM_CONFIG__sh1__WIDTH 3 |
| #define R_SDRAM_CONFIG__sh0__BITNR 24 |
| #define R_SDRAM_CONFIG__sh0__WIDTH 3 |
| #define R_SDRAM_CONFIG__w__BITNR 23 |
| #define R_SDRAM_CONFIG__w__WIDTH 1 |
| #define R_SDRAM_CONFIG__w__bw16 0 |
| #define R_SDRAM_CONFIG__w__bw32 1 |
| #define R_SDRAM_CONFIG__type1__BITNR 22 |
| #define R_SDRAM_CONFIG__type1__WIDTH 1 |
| #define R_SDRAM_CONFIG__type1__bank2 0 |
| #define R_SDRAM_CONFIG__type1__bank4 1 |
| #define R_SDRAM_CONFIG__type0__BITNR 21 |
| #define R_SDRAM_CONFIG__type0__WIDTH 1 |
| #define R_SDRAM_CONFIG__type0__bank2 0 |
| #define R_SDRAM_CONFIG__type0__bank4 1 |
| #define R_SDRAM_CONFIG__group_sel__BITNR 16 |
| #define R_SDRAM_CONFIG__group_sel__WIDTH 5 |
| #define R_SDRAM_CONFIG__group_sel__grp0 0 |
| #define R_SDRAM_CONFIG__group_sel__grp1 1 |
| #define R_SDRAM_CONFIG__group_sel__bit9 9 |
| #define R_SDRAM_CONFIG__group_sel__bit10 10 |
| #define R_SDRAM_CONFIG__group_sel__bit11 11 |
| #define R_SDRAM_CONFIG__group_sel__bit12 12 |
| #define R_SDRAM_CONFIG__group_sel__bit13 13 |
| #define R_SDRAM_CONFIG__group_sel__bit14 14 |
| #define R_SDRAM_CONFIG__group_sel__bit15 15 |
| #define R_SDRAM_CONFIG__group_sel__bit16 16 |
| #define R_SDRAM_CONFIG__group_sel__bit17 17 |
| #define R_SDRAM_CONFIG__group_sel__bit18 18 |
| #define R_SDRAM_CONFIG__group_sel__bit19 19 |
| #define R_SDRAM_CONFIG__group_sel__bit20 20 |
| #define R_SDRAM_CONFIG__group_sel__bit21 21 |
| #define R_SDRAM_CONFIG__group_sel__bit22 22 |
| #define R_SDRAM_CONFIG__group_sel__bit23 23 |
| #define R_SDRAM_CONFIG__group_sel__bit24 24 |
| #define R_SDRAM_CONFIG__group_sel__bit25 25 |
| #define R_SDRAM_CONFIG__group_sel__bit26 26 |
| #define R_SDRAM_CONFIG__group_sel__bit27 27 |
| #define R_SDRAM_CONFIG__group_sel__bit28 28 |
| #define R_SDRAM_CONFIG__group_sel__bit29 29 |
| #define R_SDRAM_CONFIG__ca1__BITNR 13 |
| #define R_SDRAM_CONFIG__ca1__WIDTH 3 |
| #define R_SDRAM_CONFIG__bank_sel1__BITNR 8 |
| #define R_SDRAM_CONFIG__bank_sel1__WIDTH 5 |
| #define R_SDRAM_CONFIG__bank_sel1__bit9 9 |
| #define R_SDRAM_CONFIG__bank_sel1__bit10 10 |
| #define R_SDRAM_CONFIG__bank_sel1__bit11 11 |
| #define R_SDRAM_CONFIG__bank_sel1__bit12 12 |
| #define R_SDRAM_CONFIG__bank_sel1__bit13 13 |
| #define R_SDRAM_CONFIG__bank_sel1__bit14 14 |
| #define R_SDRAM_CONFIG__bank_sel1__bit15 15 |
| #define R_SDRAM_CONFIG__bank_sel1__bit16 16 |
| #define R_SDRAM_CONFIG__bank_sel1__bit17 17 |
| #define R_SDRAM_CONFIG__bank_sel1__bit18 18 |
| #define R_SDRAM_CONFIG__bank_sel1__bit19 19 |
| #define R_SDRAM_CONFIG__bank_sel1__bit20 20 |
| #define R_SDRAM_CONFIG__bank_sel1__bit21 21 |
| #define R_SDRAM_CONFIG__bank_sel1__bit22 22 |
| #define R_SDRAM_CONFIG__bank_sel1__bit23 23 |
| #define R_SDRAM_CONFIG__bank_sel1__bit24 24 |
| #define R_SDRAM_CONFIG__bank_sel1__bit25 25 |
| #define R_SDRAM_CONFIG__bank_sel1__bit26 26 |
| #define R_SDRAM_CONFIG__bank_sel1__bit27 27 |
| #define R_SDRAM_CONFIG__bank_sel1__bit28 28 |
| #define R_SDRAM_CONFIG__bank_sel1__bit29 29 |
| #define R_SDRAM_CONFIG__ca0__BITNR 5 |
| #define R_SDRAM_CONFIG__ca0__WIDTH 3 |
| #define R_SDRAM_CONFIG__bank_sel0__BITNR 0 |
| #define R_SDRAM_CONFIG__bank_sel0__WIDTH 5 |
| #define R_SDRAM_CONFIG__bank_sel0__bit9 9 |
| #define R_SDRAM_CONFIG__bank_sel0__bit10 10 |
| #define R_SDRAM_CONFIG__bank_sel0__bit11 11 |
| #define R_SDRAM_CONFIG__bank_sel0__bit12 12 |
| #define R_SDRAM_CONFIG__bank_sel0__bit13 13 |
| #define R_SDRAM_CONFIG__bank_sel0__bit14 14 |
| #define R_SDRAM_CONFIG__bank_sel0__bit15 15 |
| #define R_SDRAM_CONFIG__bank_sel0__bit16 16 |
| #define R_SDRAM_CONFIG__bank_sel0__bit17 17 |
| #define R_SDRAM_CONFIG__bank_sel0__bit18 18 |
| #define R_SDRAM_CONFIG__bank_sel0__bit19 19 |
| #define R_SDRAM_CONFIG__bank_sel0__bit20 20 |
| #define R_SDRAM_CONFIG__bank_sel0__bit21 21 |
| #define R_SDRAM_CONFIG__bank_sel0__bit22 22 |
| #define R_SDRAM_CONFIG__bank_sel0__bit23 23 |
| #define R_SDRAM_CONFIG__bank_sel0__bit24 24 |
| #define R_SDRAM_CONFIG__bank_sel0__bit25 25 |
| #define R_SDRAM_CONFIG__bank_sel0__bit26 26 |
| #define R_SDRAM_CONFIG__bank_sel0__bit27 27 |
| #define R_SDRAM_CONFIG__bank_sel0__bit28 28 |
| #define R_SDRAM_CONFIG__bank_sel0__bit29 29 |
| |
| /* |
| !* External DMA registers |
| !*/ |
| |
| #define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010) |
| #define R_EXT_DMA_0_CMD__cnt__BITNR 23 |
| #define R_EXT_DMA_0_CMD__cnt__WIDTH 1 |
| #define R_EXT_DMA_0_CMD__cnt__enable 1 |
| #define R_EXT_DMA_0_CMD__cnt__disable 0 |
| #define R_EXT_DMA_0_CMD__rqpol__BITNR 22 |
| #define R_EXT_DMA_0_CMD__rqpol__WIDTH 1 |
| #define R_EXT_DMA_0_CMD__rqpol__ahigh 0 |
| #define R_EXT_DMA_0_CMD__rqpol__alow 1 |
| #define R_EXT_DMA_0_CMD__apol__BITNR 21 |
| #define R_EXT_DMA_0_CMD__apol__WIDTH 1 |
| #define R_EXT_DMA_0_CMD__apol__ahigh 0 |
| #define R_EXT_DMA_0_CMD__apol__alow 1 |
| #define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 |
| #define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1 |
| #define R_EXT_DMA_0_CMD__rq_ack__burst 0 |
| #define R_EXT_DMA_0_CMD__rq_ack__handsh 1 |
| #define R_EXT_DMA_0_CMD__wid__BITNR 18 |
| #define R_EXT_DMA_0_CMD__wid__WIDTH 2 |
| #define R_EXT_DMA_0_CMD__wid__byte 0 |
| #define R_EXT_DMA_0_CMD__wid__word 1 |
| #define R_EXT_DMA_0_CMD__wid__dword 2 |
| #define R_EXT_DMA_0_CMD__dir__BITNR 17 |
| #define R_EXT_DMA_0_CMD__dir__WIDTH 1 |
| #define R_EXT_DMA_0_CMD__dir__input 0 |
| #define R_EXT_DMA_0_CMD__dir__output 1 |
| #define R_EXT_DMA_0_CMD__run__BITNR 16 |
| #define R_EXT_DMA_0_CMD__run__WIDTH 1 |
| #define R_EXT_DMA_0_CMD__run__start 1 |
| #define R_EXT_DMA_0_CMD__run__stop 0 |
| #define R_EXT_DMA_0_CMD__trf_count__BITNR 0 |
| #define R_EXT_DMA_0_CMD__trf_count__WIDTH 16 |
| |
| #define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010) |
| #define R_EXT_DMA_0_STAT__run__BITNR 16 |
| #define R_EXT_DMA_0_STAT__run__WIDTH 1 |
| #define R_EXT_DMA_0_STAT__run__start 1 |
| #define R_EXT_DMA_0_STAT__run__stop 0 |
| #define R_EXT_DMA_0_STAT__trf_count__BITNR 0 |
| #define R_EXT_DMA_0_STAT__trf_count__WIDTH 16 |
| |
| #define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014) |
| #define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 |
| #define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28 |
| |
| #define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018) |
| #define R_EXT_DMA_1_CMD__cnt__BITNR 23 |
| #define R_EXT_DMA_1_CMD__cnt__WIDTH 1 |
| #define R_EXT_DMA_1_CMD__cnt__enable 1 |
| #define R_EXT_DMA_1_CMD__cnt__disable 0 |
| #define R_EXT_DMA_1_CMD__rqpol__BITNR 22 |
| #define R_EXT_DMA_1_CMD__rqpol__WIDTH 1 |
| #define R_EXT_DMA_1_CMD__rqpol__ahigh 0 |
| #define R_EXT_DMA_1_CMD__rqpol__alow 1 |
| #define R_EXT_DMA_1_CMD__apol__BITNR 21 |
| #define R_EXT_DMA_1_CMD__apol__WIDTH 1 |
| #define R_EXT_DMA_1_CMD__apol__ahigh 0 |
| #define R_EXT_DMA_1_CMD__apol__alow 1 |
| #define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 |
| #define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1 |
| #define R_EXT_DMA_1_CMD__rq_ack__burst 0 |
| #define R_EXT_DMA_1_CMD__rq_ack__handsh 1 |
| #define R_EXT_DMA_1_CMD__wid__BITNR 18 |
| #define R_EXT_DMA_1_CMD__wid__WIDTH 2 |
| #define R_EXT_DMA_1_CMD__wid__byte 0 |
| #define R_EXT_DMA_1_CMD__wid__word 1 |
| #define R_EXT_DMA_1_CMD__wid__dword 2 |
| #define R_EXT_DMA_1_CMD__dir__BITNR 17 |
| #define R_EXT_DMA_1_CMD__dir__WIDTH 1 |
| #define R_EXT_DMA_1_CMD__dir__input 0 |
| #define R_EXT_DMA_1_CMD__dir__output 1 |
| #define R_EXT_DMA_1_CMD__run__BITNR 16 |
| #define R_EXT_DMA_1_CMD__run__WIDTH 1 |
| #define R_EXT_DMA_1_CMD__run__start 1 |
| #define R_EXT_DMA_1_CMD__run__stop 0 |
| #define R_EXT_DMA_1_CMD__trf_count__BITNR 0 |
| #define R_EXT_DMA_1_CMD__trf_count__WIDTH 16 |
| |
| #define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018) |
| #define R_EXT_DMA_1_STAT__run__BITNR 16 |
| #define R_EXT_DMA_1_STAT__run__WIDTH 1 |
| #define R_EXT_DMA_1_STAT__run__start 1 |
| #define R_EXT_DMA_1_STAT__run__stop 0 |
| #define R_EXT_DMA_1_STAT__trf_count__BITNR 0 |
| #define R_EXT_DMA_1_STAT__trf_count__WIDTH 16 |
| |
| #define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c) |
| #define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 |
| #define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28 |
| |
| /* |
| !* Timer registers |
| !*/ |
| |
| #define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020) |
| #define R_TIMER_CTRL__timerdiv1__BITNR 24 |
| #define R_TIMER_CTRL__timerdiv1__WIDTH 8 |
| #define R_TIMER_CTRL__timerdiv0__BITNR 16 |
| #define R_TIMER_CTRL__timerdiv0__WIDTH 8 |
| #define R_TIMER_CTRL__presc_timer1__BITNR 15 |
| #define R_TIMER_CTRL__presc_timer1__WIDTH 1 |
| #define R_TIMER_CTRL__presc_timer1__normal 0 |
| #define R_TIMER_CTRL__presc_timer1__prescale 1 |
| #define R_TIMER_CTRL__i1__BITNR 14 |
| #define R_TIMER_CTRL__i1__WIDTH 1 |
| #define R_TIMER_CTRL__i1__clr 1 |
| #define R_TIMER_CTRL__i1__nop 0 |
| #define R_TIMER_CTRL__tm1__BITNR 12 |
| #define R_TIMER_CTRL__tm1__WIDTH 2 |
| #define R_TIMER_CTRL__tm1__stop_ld 0 |
| #define R_TIMER_CTRL__tm1__freeze 1 |
| #define R_TIMER_CTRL__tm1__run 2 |
| #define R_TIMER_CTRL__tm1__reserved 3 |
| #define R_TIMER_CTRL__clksel1__BITNR 8 |
| #define R_TIMER_CTRL__clksel1__WIDTH 4 |
| #define R_TIMER_CTRL__clksel1__c300Hz 0 |
| #define R_TIMER_CTRL__clksel1__c600Hz 1 |
| #define R_TIMER_CTRL__clksel1__c1200Hz 2 |
| #define R_TIMER_CTRL__clksel1__c2400Hz 3 |
| #define R_TIMER_CTRL__clksel1__c4800Hz 4 |
| #define R_TIMER_CTRL__clksel1__c9600Hz 5 |
| #define R_TIMER_CTRL__clksel1__c19k2Hz 6 |
| #define R_TIMER_CTRL__clksel1__c38k4Hz 7 |
| #define R_TIMER_CTRL__clksel1__c57k6Hz 8 |
| #define R_TIMER_CTRL__clksel1__c115k2Hz 9 |
| #define R_TIMER_CTRL__clksel1__c230k4Hz 10 |
| #define R_TIMER_CTRL__clksel1__c460k8Hz 11 |
| #define R_TIMER_CTRL__clksel1__c921k6Hz 12 |
| #define R_TIMER_CTRL__clksel1__c1843k2Hz 13 |
| #define R_TIMER_CTRL__clksel1__c6250kHz 14 |
| #define R_TIMER_CTRL__clksel1__cascade0 15 |
| #define R_TIMER_CTRL__presc_ext__BITNR 7 |
| #define R_TIMER_CTRL__presc_ext__WIDTH 1 |
| #define R_TIMER_CTRL__presc_ext__prescale 0 |
| #define R_TIMER_CTRL__presc_ext__external 1 |
| #define R_TIMER_CTRL__i0__BITNR 6 |
| #define R_TIMER_CTRL__i0__WIDTH 1 |
| #define R_TIMER_CTRL__i0__clr 1 |
| #define R_TIMER_CTRL__i0__nop 0 |
| #define R_TIMER_CTRL__tm0__BITNR 4 |
| #define R_TIMER_CTRL__tm0__WIDTH 2 |
| #define R_TIMER_CTRL__tm0__stop_ld 0 |
| #define R_TIMER_CTRL__tm0__freeze 1 |
| #define R_TIMER_CTRL__tm0__run 2 |
| #define R_TIMER_CTRL__tm0__reserved 3 |
| #define R_TIMER_CTRL__clksel0__BITNR 0 |
| #define R_TIMER_CTRL__clksel0__WIDTH 4 |
| #define R_TIMER_CTRL__clksel0__c300Hz 0 |
| #define R_TIMER_CTRL__clksel0__c600Hz 1 |
| #define R_TIMER_CTRL__clksel0__c1200Hz 2 |
| #define R_TIMER_CTRL__clksel0__c2400Hz 3 |
| #define R_TIMER_CTRL__clksel0__c4800Hz 4 |
| #define R_TIMER_CTRL__clksel0__c9600Hz 5 |
| #define R_TIMER_CTRL__clksel0__c19k2Hz 6 |
| #define R_TIMER_CTRL__clksel0__c38k4Hz 7 |
| #define R_TIMER_CTRL__clksel0__c57k6Hz 8 |
| #define R_TIMER_CTRL__clksel0__c115k2Hz 9 |
| #define R_TIMER_CTRL__clksel0__c230k4Hz 10 |
| #define R_TIMER_CTRL__clksel0__c460k8Hz 11 |
| #define R_TIMER_CTRL__clksel0__c921k6Hz 12 |
| #define R_TIMER_CTRL__clksel0__c1843k2Hz 13 |
| #define R_TIMER_CTRL__clksel0__c6250kHz 14 |
| #define R_TIMER_CTRL__clksel0__flexible 15 |
| |
| #define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020) |
| #define R_TIMER_DATA__timer1__BITNR 24 |
| #define R_TIMER_DATA__timer1__WIDTH 8 |
| #define R_TIMER_DATA__timer0__BITNR 16 |
| #define R_TIMER_DATA__timer0__WIDTH 8 |
| #define R_TIMER_DATA__clkdiv_high__BITNR 8 |
| #define R_TIMER_DATA__clkdiv_high__WIDTH 8 |
| #define R_TIMER_DATA__clkdiv_low__BITNR 0 |
| #define R_TIMER_DATA__clkdiv_low__WIDTH 8 |
| |
| #define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022) |
| #define R_TIMER01_DATA__count__BITNR 0 |
| #define R_TIMER01_DATA__count__WIDTH 16 |
| |
| #define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022) |
| #define R_TIMER0_DATA__count__BITNR 0 |
| #define R_TIMER0_DATA__count__WIDTH 8 |
| |
| #define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023) |
| #define R_TIMER1_DATA__count__BITNR 0 |
| #define R_TIMER1_DATA__count__WIDTH 8 |
| |
| #define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024) |
| #define R_WATCHDOG__key__BITNR 1 |
| #define R_WATCHDOG__key__WIDTH 3 |
| #define R_WATCHDOG__enable__BITNR 0 |
| #define R_WATCHDOG__enable__WIDTH 1 |
| #define R_WATCHDOG__enable__stop 0 |
| #define R_WATCHDOG__enable__start 1 |
| |
| #define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0) |
| #define R_CLOCK_PRESCALE__ser_presc__BITNR 16 |
| #define R_CLOCK_PRESCALE__ser_presc__WIDTH 16 |
| #define R_CLOCK_PRESCALE__tim_presc__BITNR 0 |
| #define R_CLOCK_PRESCALE__tim_presc__WIDTH 16 |
| |
| #define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2) |
| #define R_SERIAL_PRESCALE__ser_presc__BITNR 0 |
| #define R_SERIAL_PRESCALE__ser_presc__WIDTH 16 |
| |
| #define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0) |
| #define R_TIMER_PRESCALE__tim_presc__BITNR 0 |
| #define R_TIMER_PRESCALE__tim_presc__WIDTH 16 |
| |
| #define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0) |
| #define R_PRESCALE_STATUS__ser_status__BITNR 16 |
| #define R_PRESCALE_STATUS__ser_status__WIDTH 16 |
| #define R_PRESCALE_STATUS__tim_status__BITNR 0 |
| #define R_PRESCALE_STATUS__tim_status__WIDTH 16 |
| |
| #define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2) |
| #define R_SER_PRESC_STATUS__ser_status__BITNR 0 |
| #define R_SER_PRESC_STATUS__ser_status__WIDTH 16 |
| |
| #define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0) |
| #define R_TIM_PRESC_STATUS__tim_status__BITNR 0 |
| #define R_TIM_PRESC_STATUS__tim_status__WIDTH 16 |
| |
| #define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4) |
| #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 |
| #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1 |
| #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0 |
| #define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1 |
| #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 |
| #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1 |
| #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0 |
| #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1 |
| #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 |
| #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1 |
| #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0 |
| #define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1 |
| #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 |
| #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1 |
| #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0 |
| #define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1 |
| #define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 |
| #define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3 |
| #define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0 |
| #define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1 |
| #define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2 |
| #define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3 |
| #define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4 |
| #define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5 |
| #define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6 |
| #define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7 |
| #define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 |
| #define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1 |
| #define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0 |
| #define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1 |
| #define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 |
| #define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4 |
| #define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 |
| #define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10 |
| |
| /* |
| !* Shared RAM interface registers |
| !*/ |
| |
| #define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040) |
| #define R_SHARED_RAM_CONFIG__width__BITNR 3 |
| #define R_SHARED_RAM_CONFIG__width__WIDTH 1 |
| #define R_SHARED_RAM_CONFIG__width__byte 0 |
| #define R_SHARED_RAM_CONFIG__width__word 1 |
| #define R_SHARED_RAM_CONFIG__enable__BITNR 2 |
| #define R_SHARED_RAM_CONFIG__enable__WIDTH 1 |
| #define R_SHARED_RAM_CONFIG__enable__yes 1 |
| #define R_SHARED_RAM_CONFIG__enable__no 0 |
| #define R_SHARED_RAM_CONFIG__pint__BITNR 1 |
| #define R_SHARED_RAM_CONFIG__pint__WIDTH 1 |
| #define R_SHARED_RAM_CONFIG__pint__int 1 |
| #define R_SHARED_RAM_CONFIG__pint__nop 0 |
| #define R_SHARED_RAM_CONFIG__clri__BITNR 0 |
| #define R_SHARED_RAM_CONFIG__clri__WIDTH 1 |
| #define R_SHARED_RAM_CONFIG__clri__clr 1 |
| #define R_SHARED_RAM_CONFIG__clri__nop 0 |
| |
| #define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044) |
| #define R_SHARED_RAM_ADDR__base_addr__BITNR 8 |
| #define R_SHARED_RAM_ADDR__base_addr__WIDTH 22 |
| |
| /* |
| !* General config registers |
| !*/ |
| |
| #define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c) |
| #define R_GEN_CONFIG__par_w__BITNR 31 |
| #define R_GEN_CONFIG__par_w__WIDTH 1 |
| #define R_GEN_CONFIG__par_w__select 1 |
| #define R_GEN_CONFIG__par_w__disable 0 |
| #define R_GEN_CONFIG__usb2__BITNR 30 |
| #define R_GEN_CONFIG__usb2__WIDTH 1 |
| #define R_GEN_CONFIG__usb2__select 1 |
| #define R_GEN_CONFIG__usb2__disable 0 |
| #define R_GEN_CONFIG__usb1__BITNR 29 |
| #define R_GEN_CONFIG__usb1__WIDTH 1 |
| #define R_GEN_CONFIG__usb1__select 1 |
| #define R_GEN_CONFIG__usb1__disable 0 |
| #define R_GEN_CONFIG__g24dir__BITNR 27 |
| #define R_GEN_CONFIG__g24dir__WIDTH 1 |
| #define R_GEN_CONFIG__g24dir__in 0 |
| #define R_GEN_CONFIG__g24dir__out 1 |
| #define R_GEN_CONFIG__g16_23dir__BITNR 26 |
| #define R_GEN_CONFIG__g16_23dir__WIDTH 1 |
| #define R_GEN_CONFIG__g16_23dir__in 0 |
| #define R_GEN_CONFIG__g16_23dir__out 1 |
| #define R_GEN_CONFIG__g8_15dir__BITNR 25 |
| #define R_GEN_CONFIG__g8_15dir__WIDTH 1 |
| #define R_GEN_CONFIG__g8_15dir__in 0 |
| #define R_GEN_CONFIG__g8_15dir__out 1 |
| #define R_GEN_CONFIG__g0dir__BITNR 24 |
| #define R_GEN_CONFIG__g0dir__WIDTH 1 |
| #define R_GEN_CONFIG__g0dir__in 0 |
| #define R_GEN_CONFIG__g0dir__out 1 |
| #define R_GEN_CONFIG__dma9__BITNR 23 |
| #define R_GEN_CONFIG__dma9__WIDTH 1 |
| #define R_GEN_CONFIG__dma9__usb 0 |
| #define R_GEN_CONFIG__dma9__serial1 1 |
| #define R_GEN_CONFIG__dma8__BITNR 22 |
| #define R_GEN_CONFIG__dma8__WIDTH 1 |
| #define R_GEN_CONFIG__dma8__usb 0 |
| #define R_GEN_CONFIG__dma8__serial1 1 |
| #define R_GEN_CONFIG__dma7__BITNR 20 |
| #define R_GEN_CONFIG__dma7__WIDTH 2 |
| #define R_GEN_CONFIG__dma7__unused 0 |
| #define R_GEN_CONFIG__dma7__serial0 1 |
| #define R_GEN_CONFIG__dma7__extdma1 2 |
| #define R_GEN_CONFIG__dma7__intdma6 3 |
| #define R_GEN_CONFIG__dma6__BITNR 18 |
| #define R_GEN_CONFIG__dma6__WIDTH 2 |
| #define R_GEN_CONFIG__dma6__unused 0 |
| #define R_GEN_CONFIG__dma6__serial0 1 |
| #define R_GEN_CONFIG__dma6__extdma1 2 |
| #define R_GEN_CONFIG__dma6__intdma7 3 |
| #define R_GEN_CONFIG__dma5__BITNR 16 |
| #define R_GEN_CONFIG__dma5__WIDTH 2 |
| #define R_GEN_CONFIG__dma5__par1 0 |
| #define R_GEN_CONFIG__dma5__scsi1 1 |
| #define R_GEN_CONFIG__dma5__serial3 2 |
| #define R_GEN_CONFIG__dma5__extdma0 3 |
| #define R_GEN_CONFIG__dma4__BITNR 14 |
| #define R_GEN_CONFIG__dma4__WIDTH 2 |
| #define R_GEN_CONFIG__dma4__par1 0 |
| #define R_GEN_CONFIG__dma4__scsi1 1 |
| #define R_GEN_CONFIG__dma4__serial3 2 |
| #define R_GEN_CONFIG__dma4__extdma0 3 |
| #define R_GEN_CONFIG__dma3__BITNR 12 |
| #define R_GEN_CONFIG__dma3__WIDTH 2 |
| #define R_GEN_CONFIG__dma3__par0 0 |
| #define R_GEN_CONFIG__dma3__scsi0 1 |
| #define R_GEN_CONFIG__dma3__serial2 2 |
| #define R_GEN_CONFIG__dma3__ata 3 |
| #define R_GEN_CONFIG__dma2__BITNR 10 |
| #define R_GEN_CONFIG__dma2__WIDTH 2 |
| #define R_GEN_CONFIG__dma2__par0 0 |
| #define R_GEN_CONFIG__dma2__scsi0 1 |
| #define R_GEN_CONFIG__dma2__serial2 2 |
| #define R_GEN_CONFIG__dma2__ata 3 |
| #define R_GEN_CONFIG__mio_w__BITNR 9 |
| #define R_GEN_CONFIG__mio_w__WIDTH 1 |
| #define R_GEN_CONFIG__mio_w__select 1 |
| #define R_GEN_CONFIG__mio_w__disable 0 |
| #define R_GEN_CONFIG__ser3__BITNR 8 |
| #define R_GEN_CONFIG__ser3__WIDTH 1 |
| #define R_GEN_CONFIG__ser3__select 1 |
| #define R_GEN_CONFIG__ser3__disable 0 |
| #define R_GEN_CONFIG__par1__BITNR 7 |
| #define R_GEN_CONFIG__par1__WIDTH 1 |
| #define R_GEN_CONFIG__par1__select 1 |
| #define R_GEN_CONFIG__par1__disable 0 |
| #define R_GEN_CONFIG__scsi0w__BITNR 6 |
| #define R_GEN_CONFIG__scsi0w__WIDTH 1 |
| #define R_GEN_CONFIG__scsi0w__select 1 |
| #define R_GEN_CONFIG__scsi0w__disable 0 |
| #define R_GEN_CONFIG__scsi1__BITNR 5 |
| #define R_GEN_CONFIG__scsi1__WIDTH 1 |
| #define R_GEN_CONFIG__scsi1__select 1 |
| #define R_GEN_CONFIG__scsi1__disable 0 |
| #define R_GEN_CONFIG__mio__BITNR 4 |
| #define R_GEN_CONFIG__mio__WIDTH 1 |
| #define R_GEN_CONFIG__mio__select 1 |
| #define R_GEN_CONFIG__mio__disable 0 |
| #define R_GEN_CONFIG__ser2__BITNR 3 |
| #define R_GEN_CONFIG__ser2__WIDTH 1 |
| #define R_GEN_CONFIG__ser2__select 1 |
| #define R_GEN_CONFIG__ser2__disable 0 |
| #define R_GEN_CONFIG__par0__BITNR 2 |
| #define R_GEN_CONFIG__par0__WIDTH 1 |
| #define R_GEN_CONFIG__par0__select 1 |
| #define R_GEN_CONFIG__par0__disable 0 |
| #define R_GEN_CONFIG__ata__BITNR 1 |
| #define R_GEN_CONFIG__ata__WIDTH 1 |
| #define R_GEN_CONFIG__ata__select 1 |
| #define R_GEN_CONFIG__ata__disable 0 |
| #define R_GEN_CONFIG__scsi0__BITNR 0 |
| #define R_GEN_CONFIG__scsi0__WIDTH 1 |
| #define R_GEN_CONFIG__scsi0__select 1 |
| #define R_GEN_CONFIG__scsi0__disable 0 |
| |
| #define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034) |
| #define R_GEN_CONFIG_II__sermode3__BITNR 6 |
| #define R_GEN_CONFIG_II__sermode3__WIDTH 1 |
| #define R_GEN_CONFIG_II__sermode3__async 0 |
| #define R_GEN_CONFIG_II__sermode3__sync 1 |
| #define R_GEN_CONFIG_II__sermode1__BITNR 4 |
| #define R_GEN_CONFIG_II__sermode1__WIDTH 1 |
| #define R_GEN_CONFIG_II__sermode1__async 0 |
| #define R_GEN_CONFIG_II__sermode1__sync 1 |
| #define R_GEN_CONFIG_II__ext_clk__BITNR 2 |
| #define R_GEN_CONFIG_II__ext_clk__WIDTH 1 |
| #define R_GEN_CONFIG_II__ext_clk__select 1 |
| #define R_GEN_CONFIG_II__ext_clk__disable 0 |
| #define R_GEN_CONFIG_II__ser2__BITNR 1 |
| #define R_GEN_CONFIG_II__ser2__WIDTH 1 |
| #define R_GEN_CONFIG_II__ser2__select 1 |
| #define R_GEN_CONFIG_II__ser2__disable 0 |
| #define R_GEN_CONFIG_II__ser3__BITNR 0 |
| #define R_GEN_CONFIG_II__ser3__WIDTH 1 |
| #define R_GEN_CONFIG_II__ser3__select 1 |
| #define R_GEN_CONFIG_II__ser3__disable 0 |
| |
| #define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028) |
| #define R_PORT_G_DATA__data__BITNR 0 |
| #define R_PORT_G_DATA__data__WIDTH 32 |
| |
| /* |
| !* General port configuration registers |
| !*/ |
| |
| #define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030) |
| #define R_PORT_PA_SET__dir7__BITNR 15 |
| #define R_PORT_PA_SET__dir7__WIDTH 1 |
| #define R_PORT_PA_SET__dir7__input 0 |
| #define R_PORT_PA_SET__dir7__output 1 |
| #define R_PORT_PA_SET__dir6__BITNR 14 |
| #define R_PORT_PA_SET__dir6__WIDTH 1 |
| #define R_PORT_PA_SET__dir6__input 0 |
| #define R_PORT_PA_SET__dir6__output 1 |
| #define R_PORT_PA_SET__dir5__BITNR 13 |
| #define R_PORT_PA_SET__dir5__WIDTH 1 |
| #define R_PORT_PA_SET__dir5__input 0 |
| #define R_PORT_PA_SET__dir5__output 1 |
| #define R_PORT_PA_SET__dir4__BITNR 12 |
| #define R_PORT_PA_SET__dir4__WIDTH 1 |
| #define R_PORT_PA_SET__dir4__input 0 |
| #define R_PORT_PA_SET__dir4__output 1 |
| #define R_PORT_PA_SET__dir3__BITNR 11 |
| #define R_PORT_PA_SET__dir3__WIDTH 1 |
| #define R_PORT_PA_SET__dir3__input 0 |
| #define R_PORT_PA_SET__dir3__output 1 |
| #define R_PORT_PA_SET__dir2__BITNR 10 |
| #define R_PORT_PA_SET__dir2__WIDTH 1 |
| #define R_PORT_PA_SET__dir2__input 0 |
| #define R_PORT_PA_SET__dir2__output 1 |
| #define R_PORT_PA_SET__dir1__BITNR 9 |
| #define R_PORT_PA_SET__dir1__WIDTH 1 |
| #define R_PORT_PA_SET__dir1__input 0 |
| #define R_PORT_PA_SET__dir1__output 1 |
| #define R_PORT_PA_SET__dir0__BITNR 8 |
| #define R_PORT_PA_SET__dir0__WIDTH 1 |
| #define R_PORT_PA_SET__dir0__input 0 |
| #define R_PORT_PA_SET__dir0__output 1 |
| #define R_PORT_PA_SET__data_out__BITNR 0 |
| #define R_PORT_PA_SET__data_out__WIDTH 8 |
| |
| #define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030) |
| #define R_PORT_PA_DATA__data_out__BITNR 0 |
| #define R_PORT_PA_DATA__data_out__WIDTH 8 |
| |
| #define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031) |
| #define R_PORT_PA_DIR__dir7__BITNR 7 |
| #define R_PORT_PA_DIR__dir7__WIDTH 1 |
| #define R_PORT_PA_DIR__dir7__input 0 |
| #define R_PORT_PA_DIR__dir7__output 1 |
| #define R_PORT_PA_DIR__dir6__BITNR 6 |
| #define R_PORT_PA_DIR__dir6__WIDTH 1 |
| #define R_PORT_PA_DIR__dir6__input 0 |
| #define R_PORT_PA_DIR__dir6__output 1 |
| #define R_PORT_PA_DIR__dir5__BITNR 5 |
| #define R_PORT_PA_DIR__dir5__WIDTH 1 |
| #define R_PORT_PA_DIR__dir5__input 0 |
| #define R_PORT_PA_DIR__dir5__output 1 |
| #define R_PORT_PA_DIR__dir4__BITNR 4 |
| #define R_PORT_PA_DIR__dir4__WIDTH 1 |
| #define R_PORT_PA_DIR__dir4__input 0 |
| #define R_PORT_PA_DIR__dir4__output 1 |
| #define R_PORT_PA_DIR__dir3__BITNR 3 |
| #define R_PORT_PA_DIR__dir3__WIDTH 1 |
| #define R_PORT_PA_DIR__dir3__input 0 |
| #define R_PORT_PA_DIR__dir3__output 1 |
| #define R_PORT_PA_DIR__dir2__BITNR 2 |
| #define R_PORT_PA_DIR__dir2__WIDTH 1 |
| #define R_PORT_PA_DIR__dir2__input 0 |
| #define R_PORT_PA_DIR__dir2__output 1 |
| #define R_PORT_PA_DIR__dir1__BITNR 1 |
| #define R_PORT_PA_DIR__dir1__WIDTH 1 |
| #define R_PORT_PA_DIR__dir1__input 0 |
| #define R_PORT_PA_DIR__dir1__output 1 |
| #define R_PORT_PA_DIR__dir0__BITNR 0 |
| #define R_PORT_PA_DIR__dir0__WIDTH 1 |
| #define R_PORT_PA_DIR__dir0__input 0 |
| #define R_PORT_PA_DIR__dir0__output 1 |
| |
| #define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030) |
| #define R_PORT_PA_READ__data_in__BITNR 0 |
| #define R_PORT_PA_READ__data_in__WIDTH 8 |
| |
| #define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038) |
| #define R_PORT_PB_SET__syncser3__BITNR 29 |
| #define R_PORT_PB_SET__syncser3__WIDTH 1 |
| #define R_PORT_PB_SET__syncser3__port_cs 0 |
| #define R_PORT_PB_SET__syncser3__ss3extra 1 |
| #define R_PORT_PB_SET__syncser1__BITNR 28 |
| #define R_PORT_PB_SET__syncser1__WIDTH 1 |
| #define R_PORT_PB_SET__syncser1__port_cs 0 |
| #define R_PORT_PB_SET__syncser1__ss1extra 1 |
| #define R_PORT_PB_SET__i2c_en__BITNR 27 |
| #define R_PORT_PB_SET__i2c_en__WIDTH 1 |
| #define R_PORT_PB_SET__i2c_en__off 0 |
| #define R_PORT_PB_SET__i2c_en__on 1 |
| #define R_PORT_PB_SET__i2c_d__BITNR 26 |
| #define R_PORT_PB_SET__i2c_d__WIDTH 1 |
| #define R_PORT_PB_SET__i2c_clk__BITNR 25 |
| #define R_PORT_PB_SET__i2c_clk__WIDTH 1 |
| #define R_PORT_PB_SET__i2c_oe___BITNR 24 |
| #define R_PORT_PB_SET__i2c_oe___WIDTH 1 |
| #define R_PORT_PB_SET__i2c_oe___enable 0 |
| #define R_PORT_PB_SET__i2c_oe___disable 1 |
| #define R_PORT_PB_SET__cs7__BITNR 23 |
| #define R_PORT_PB_SET__cs7__WIDTH 1 |
| #define R_PORT_PB_SET__cs7__port 0 |
| #define R_PORT_PB_SET__cs7__cs 1 |
| #define R_PORT_PB_SET__cs6__BITNR 22 |
| #define R_PORT_PB_SET__cs6__WIDTH 1 |
| #define R_PORT_PB_SET__cs6__port 0 |
| #define R_PORT_PB_SET__cs6__cs 1 |
| #define R_PORT_PB_SET__cs5__BITNR 21 |
| #define R_PORT_PB_SET__cs5__WIDTH 1 |
| #define R_PORT_PB_SET__cs5__port 0 |
| #define R_PORT_PB_SET__cs5__cs 1 |
| #define R_PORT_PB_SET__cs4__BITNR 20 |
| #define R_PORT_PB_SET__cs4__WIDTH 1 |
| #define R_PORT_PB_SET__cs4__port 0 |
| #define R_PORT_PB_SET__cs4__cs 1 |
| #define R_PORT_PB_SET__cs3__BITNR 19 |
| #define R_PORT_PB_SET__cs3__WIDTH 1 |
| #define R_PORT_PB_SET__cs3__port 0 |
| #define R_PORT_PB_SET__cs3__cs 1 |
| #define R_PORT_PB_SET__cs2__BITNR 18 |
| #define R_PORT_PB_SET__cs2__WIDTH 1 |
| #define R_PORT_PB_SET__cs2__port 0 |
| #define R_PORT_PB_SET__cs2__cs 1 |
| #define R_PORT_PB_SET__scsi1__BITNR 17 |
| #define R_PORT_PB_SET__scsi1__WIDTH 1 |
| #define R_PORT_PB_SET__scsi1__port_cs 0 |
| #define R_PORT_PB_SET__scsi1__enph 1 |
| #define R_PORT_PB_SET__scsi0__BITNR 16 |
| #define R_PORT_PB_SET__scsi0__WIDTH 1 |
| #define R_PORT_PB_SET__scsi0__port_cs 0 |
| #define R_PORT_PB_SET__scsi0__enph 1 |
| #define R_PORT_PB_SET__dir7__BITNR 15 |
| #define R_PORT_PB_SET__dir7__WIDTH 1 |
| #define R_PORT_PB_SET__dir7__input 0 |
| #define R_PORT_PB_SET__dir7__output 1 |
| #define R_PORT_PB_SET__dir6__BITNR 14 |
| #define R_PORT_PB_SET__dir6__WIDTH 1 |
| #define R_PORT_PB_SET__dir6__input 0 |
| #define R_PORT_PB_SET__dir6__output 1 |
| #define R_PORT_PB_SET__dir5__BITNR 13 |
| #define R_PORT_PB_SET__dir5__WIDTH 1 |
| #define R_PORT_PB_SET__dir5__input 0 |
| #define R_PORT_PB_SET__dir5__output 1 |
| #define R_PORT_PB_SET__dir4__BITNR 12 |
| #define R_PORT_PB_SET__dir4__WIDTH 1 |
| #define R_PORT_PB_SET__dir4__input 0 |
| #define R_PORT_PB_SET__dir4__output 1 |
| #define R_PORT_PB_SET__dir3__BITNR 11 |
| #define R_PORT_PB_SET__dir3__WIDTH 1 |
| #define R_PORT_PB_SET__dir3__input 0 |
| #define R_PORT_PB_SET__dir3__output 1 |
| #define R_PORT_PB_SET__dir2__BITNR 10 |
| #define R_PORT_PB_SET__dir2__WIDTH 1 |
| #define R_PORT_PB_SET__dir2__input 0 |
| #define R_PORT_PB_SET__dir2__output 1 |
| #define R_PORT_PB_SET__dir1__BITNR 9 |
| #define R_PORT_PB_SET__dir1__WIDTH 1 |
| #define R_PORT_PB_SET__dir1__input 0 |
| #define R_PORT_PB_SET__dir1__output 1 |
| #define R_PORT_PB_SET__dir0__BITNR 8 |
| #define R_PORT_PB_SET__dir0__WIDTH 1 |
| #define R_PORT_PB_SET__dir0__input 0 |
| #define R_PORT_PB_SET__dir0__output 1 |
| #define R_PORT_PB_SET__data_out__BITNR 0 |
| #define R_PORT_PB_SET__data_out__WIDTH 8 |
| |
| #define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038) |
| #define R_PORT_PB_DATA__data_out__BITNR 0 |
| #define R_PORT_PB_DATA__data_out__WIDTH 8 |
| |
| #define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039) |
| #define R_PORT_PB_DIR__dir7__BITNR 7 |
| #define R_PORT_PB_DIR__dir7__WIDTH 1 |
| #define R_PORT_PB_DIR__dir7__input 0 |
| #define R_PORT_PB_DIR__dir7__output 1 |
| #define R_PORT_PB_DIR__dir6__BITNR 6 |
| #define R_PORT_PB_DIR__dir6__WIDTH 1 |
| #define R_PORT_PB_DIR__dir6__input 0 |
| #define R_PORT_PB_DIR__dir6__output 1 |
| #define R_PORT_PB_DIR__dir5__BITNR 5 |
| #define R_PORT_PB_DIR__dir5__WIDTH 1 |
| #define R_PORT_PB_DIR__dir5__input 0 |
| #define R_PORT_PB_DIR__dir5__output 1 |
| #define R_PORT_PB_DIR__dir4__BITNR 4 |
| #define R_PORT_PB_DIR__dir4__WIDTH 1 |
| #define R_PORT_PB_DIR__dir4__input 0 |
| #define R_PORT_PB_DIR__dir4__output 1 |
| #define R_PORT_PB_DIR__dir3__BITNR 3 |
| #define R_PORT_PB_DIR__dir3__WIDTH 1 |
| #define R_PORT_PB_DIR__dir3__input 0 |
| #define R_PORT_PB_DIR__dir3__output 1 |
| #define R_PORT_PB_DIR__dir2__BITNR 2 |
| #define R_PORT_PB_DIR__dir2__WIDTH 1 |
| #define R_PORT_PB_DIR__dir2__input 0 |
| #define R_PORT_PB_DIR__dir2__output 1 |
| #define R_PORT_PB_DIR__dir1__BITNR 1 |
| #define R_PORT_PB_DIR__dir1__WIDTH 1 |
| #define R_PORT_PB_DIR__dir1__input 0 |
| #define R_PORT_PB_DIR__dir1__output 1 |
| #define R_PORT_PB_DIR__dir0__BITNR 0 |
| #define R_PORT_PB_DIR__dir0__WIDTH 1 |
| #define R_PORT_PB_DIR__dir0__input 0 |
| #define R_PORT_PB_DIR__dir0__output 1 |
| |
| #define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a) |
| #define R_PORT_PB_CONFIG__cs7__BITNR 7 |
| #define R_PORT_PB_CONFIG__cs7__WIDTH 1 |
| #define R_PORT_PB_CONFIG__cs7__port 0 |
| #define R_PORT_PB_CONFIG__cs7__cs 1 |
| #define R_PORT_PB_CONFIG__cs6__BITNR 6 |
| #define R_PORT_PB_CONFIG__cs6__WIDTH 1 |
| #define R_PORT_PB_CONFIG__cs6__port 0 |
| #define R_PORT_PB_CONFIG__cs6__cs 1 |
| #define R_PORT_PB_CONFIG__cs5__BITNR 5 |
| #define R_PORT_PB_CONFIG__cs5__WIDTH 1 |
| #define R_PORT_PB_CONFIG__cs5__port 0 |
| #define R_PORT_PB_CONFIG__cs5__cs 1 |
| #define R_PORT_PB_CONFIG__cs4__BITNR 4 |
| #define R_PORT_PB_CONFIG__cs4__WIDTH 1 |
| #define R_PORT_PB_CONFIG__cs4__port 0 |
| #define R_PORT_PB_CONFIG__cs4__cs 1 |
| #define R_PORT_PB_CONFIG__cs3__BITNR 3 |
| #define R_PORT_PB_CONFIG__cs3__WIDTH 1 |
| #define R_PORT_PB_CONFIG__cs3__port 0 |
| #define R_PORT_PB_CONFIG__cs3__cs 1 |
| #define R_PORT_PB_CONFIG__cs2__BITNR 2 |
| #define R_PORT_PB_CONFIG__cs2__WIDTH 1 |
| #define R_PORT_PB_CONFIG__cs2__port 0 |
| #define R_PORT_PB_CONFIG__cs2__cs 1 |
| #define R_PORT_PB_CONFIG__scsi1__BITNR 1 |
| #define R_PORT_PB_CONFIG__scsi1__WIDTH 1 |
| #define R_PORT_PB_CONFIG__scsi1__port_cs 0 |
| #define R_PORT_PB_CONFIG__scsi1__enph 1 |
| #define R_PORT_PB_CONFIG__scsi0__BITNR 0 |
| #define R_PORT_PB_CONFIG__scsi0__WIDTH 1 |
| #define R_PORT_PB_CONFIG__scsi0__port_cs 0 |
| #define R_PORT_PB_CONFIG__scsi0__enph 1 |
| |
| #define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b) |
| #define R_PORT_PB_I2C__syncser3__BITNR 5 |
| #define R_PORT_PB_I2C__syncser3__WIDTH 1 |
| #define R_PORT_PB_I2C__syncser3__port_cs 0 |
| #define R_PORT_PB_I2C__syncser3__ss3extra 1 |
| #define R_PORT_PB_I2C__syncser1__BITNR 4 |
| #define R_PORT_PB_I2C__syncser1__WIDTH 1 |
| #define R_PORT_PB_I2C__syncser1__port_cs 0 |
| #define R_PORT_PB_I2C__syncser1__ss1extra 1 |
| #define R_PORT_PB_I2C__i2c_en__BITNR 3 |
| #define R_PORT_PB_I2C__i2c_en__WIDTH 1 |
| #define R_PORT_PB_I2C__i2c_en__off 0 |
| #define R_PORT_PB_I2C__i2c_en__on 1 |
| #define R_PORT_PB_I2C__i2c_d__BITNR 2 |
| #define R_PORT_PB_I2C__i2c_d__WIDTH 1 |
| #define R_PORT_PB_I2C__i2c_clk__BITNR 1 |
| #define R_PORT_PB_I2C__i2c_clk__WIDTH 1 |
| #define R_PORT_PB_I2C__i2c_oe___BITNR 0 |
| #define R_PORT_PB_I2C__i2c_oe___WIDTH 1 |
| #define R_PORT_PB_I2C__i2c_oe___enable 0 |
| #define R_PORT_PB_I2C__i2c_oe___disable 1 |
| |
| #define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038) |
| #define R_PORT_PB_READ__data_in__BITNR 0 |
| #define R_PORT_PB_READ__data_in__WIDTH 8 |
| |
| /* |
| !* Serial port registers |
| !*/ |
| |
| #define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060) |
| #define R_SERIAL0_CTRL__tr_baud__BITNR 28 |
| #define R_SERIAL0_CTRL__tr_baud__WIDTH 4 |
| #define R_SERIAL0_CTRL__tr_baud__c300Hz 0 |
| #define R_SERIAL0_CTRL__tr_baud__c600Hz 1 |
| #define R_SERIAL0_CTRL__tr_baud__c1200Hz 2 |
| #define R_SERIAL0_CTRL__tr_baud__c2400Hz 3 |
| #define R_SERIAL0_CTRL__tr_baud__c4800Hz 4 |
| #define R_SERIAL0_CTRL__tr_baud__c9600Hz 5 |
| #define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6 |
| #define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7 |
| #define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8 |
| #define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9 |
| #define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10 |
| #define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11 |
| #define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12 |
| #define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13 |
| #define R_SERIAL0_CTRL__tr_baud__c6250kHz 14 |
| #define R_SERIAL0_CTRL__tr_baud__reserved 15 |
| #define R_SERIAL0_CTRL__rec_baud__BITNR 24 |
| #define R_SERIAL0_CTRL__rec_baud__WIDTH 4 |
| #define R_SERIAL0_CTRL__rec_baud__c300Hz 0 |
| #define R_SERIAL0_CTRL__rec_baud__c600Hz 1 |
| #define R_SERIAL0_CTRL__rec_baud__c1200Hz 2 |
| #define R_SERIAL0_CTRL__rec_baud__c2400Hz 3 |
| #define R_SERIAL0_CTRL__rec_baud__c4800Hz 4 |
| #define R_SERIAL0_CTRL__rec_baud__c9600Hz 5 |
| #define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6 |
| #define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7 |
| #define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8 |
| #define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9 |
| #define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10 |
| #define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11 |
| #define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12 |
| #define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13 |
| #define R_SERIAL0_CTRL__rec_baud__c6250kHz 14 |
| #define R_SERIAL0_CTRL__rec_baud__reserved 15 |
| #define R_SERIAL0_CTRL__dma_err__BITNR 23 |
| #define R_SERIAL0_CTRL__dma_err__WIDTH 1 |
| #define R_SERIAL0_CTRL__dma_err__stop 0 |
| #define R_SERIAL0_CTRL__dma_err__ignore 1 |
| #define R_SERIAL0_CTRL__rec_enable__BITNR 22 |
| #define R_SERIAL0_CTRL__rec_enable__WIDTH 1 |
| #define R_SERIAL0_CTRL__rec_enable__disable 0 |
| #define R_SERIAL0_CTRL__rec_enable__enable 1 |
| #define R_SERIAL0_CTRL__rts___BITNR 21 |
| #define R_SERIAL0_CTRL__rts___WIDTH 1 |
| #define R_SERIAL0_CTRL__rts___active 0 |
| #define R_SERIAL0_CTRL__rts___inactive 1 |
| #define R_SERIAL0_CTRL__sampling__BITNR 20 |
| #define R_SERIAL0_CTRL__sampling__WIDTH 1 |
| #define R_SERIAL0_CTRL__sampling__middle 0 |
| #define R_SERIAL0_CTRL__sampling__majority 1 |
| #define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 |
| #define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1 |
| #define R_SERIAL0_CTRL__rec_stick_par__normal 0 |
| #define R_SERIAL0_CTRL__rec_stick_par__stick 1 |
| #define R_SERIAL0_CTRL__rec_par__BITNR 18 |
| #define R_SERIAL0_CTRL__rec_par__WIDTH 1 |
| #define R_SERIAL0_CTRL__rec_par__even 0 |
| #define R_SERIAL0_CTRL__rec_par__odd 1 |
| #define R_SERIAL0_CTRL__rec_par_en__BITNR 17 |
| #define R_SERIAL0_CTRL__rec_par_en__WIDTH 1 |
| #define R_SERIAL0_CTRL__rec_par_en__disable 0 |
| #define R_SERIAL0_CTRL__rec_par_en__enable 1 |
| #define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 |
| #define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1 |
| #define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0 |
| #define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1 |
| #define R_SERIAL0_CTRL__txd__BITNR 15 |
| #define R_SERIAL0_CTRL__txd__WIDTH 1 |
| #define R_SERIAL0_CTRL__tr_enable__BITNR 14 |
| #define R_SERIAL0_CTRL__tr_enable__WIDTH 1 |
| #define R_SERIAL0_CTRL__tr_enable__disable 0 |
| #define R_SERIAL0_CTRL__tr_enable__enable 1 |
| #define R_SERIAL0_CTRL__auto_cts__BITNR 13 |
| #define R_SERIAL0_CTRL__auto_cts__WIDTH 1 |
| #define R_SERIAL0_CTRL__auto_cts__disabled 0 |
| #define R_SERIAL0_CTRL__auto_cts__active 1 |
| #define R_SERIAL0_CTRL__stop_bits__BITNR 12 |
| #define R_SERIAL0_CTRL__stop_bits__WIDTH 1 |
| #define R_SERIAL0_CTRL__stop_bits__one_bit 0 |
| #define R_SERIAL0_CTRL__stop_bits__two_bits 1 |
| #define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 |
| #define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1 |
| #define R_SERIAL0_CTRL__tr_stick_par__normal 0 |
| #define R_SERIAL0_CTRL__tr_stick_par__stick 1 |
| #define R_SERIAL0_CTRL__tr_par__BITNR 10 |
| #define R_SERIAL0_CTRL__tr_par__WIDTH 1 |
| #define R_SERIAL0_CTRL__tr_par__even 0 |
| #define R_SERIAL0_CTRL__tr_par__odd 1 |
| #define R_SERIAL0_CTRL__tr_par_en__BITNR 9 |
| #define R_SERIAL0_CTRL__tr_par_en__WIDTH 1 |
| #define R_SERIAL0_CTRL__tr_par_en__disable 0 |
| #define R_SERIAL0_CTRL__tr_par_en__enable 1 |
| #define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 |
| #define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1 |
| #define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0 |
| #define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1 |
| #define R_SERIAL0_CTRL__data_out__BITNR 0 |
| #define R_SERIAL0_CTRL__data_out__WIDTH 8 |
| |
| #define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063) |
| #define R_SERIAL0_BAUD__tr_baud__BITNR 4 |
| #define R_SERIAL0_BAUD__tr_baud__WIDTH 4 |
| #define R_SERIAL0_BAUD__tr_baud__c300Hz 0 |
| #define R_SERIAL0_BAUD__tr_baud__c600Hz 1 |
| #define R_SERIAL0_BAUD__tr_baud__c1200Hz 2 |
| #define R_SERIAL0_BAUD__tr_baud__c2400Hz 3 |
| #define R_SERIAL0_BAUD__tr_baud__c4800Hz 4 |
| #define R_SERIAL0_BAUD__tr_baud__c9600Hz 5 |
| #define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6 |
| #define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7 |
| #define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8 |
| #define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9 |
| #define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10 |
| #define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11 |
| #define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12 |
| #define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13 |
| #define R_SERIAL0_BAUD__tr_baud__c6250kHz 14 |
| #define R_SERIAL0_BAUD__tr_baud__reserved 15 |
| #define R_SERIAL0_BAUD__rec_baud__BITNR 0 |
| #define R_SERIAL0_BAUD__rec_baud__WIDTH 4 |
| #define R_SERIAL0_BAUD__rec_baud__c300Hz 0 |
| #define R_SERIAL0_BAUD__rec_baud__c600Hz 1 |
| #define R_SERIAL0_BAUD__rec_baud__c1200Hz 2 |
| #define R_SERIAL0_BAUD__rec_baud__c2400Hz 3 |
| #define R_SERIAL0_BAUD__rec_baud__c4800Hz 4 |
| #define R_SERIAL0_BAUD__rec_baud__c9600Hz 5 |
| #define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6 |
| #define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7 |
| #define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8 |
| #define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9 |
| #define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10 |
| #define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11 |
| #define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12 |
| #define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13 |
| #define R_SERIAL0_BAUD__rec_baud__c6250kHz 14 |
| #define R_SERIAL0_BAUD__rec_baud__reserved 15 |
| |
| #define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062) |
| #define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 |
| #define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1 |
| #define R_SERIAL0_REC_CTRL__dma_err__stop 0 |
| #define R_SERIAL0_REC_CTRL__dma_err__ignore 1 |
| #define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 |
| #define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1 |
| #define R_SERIAL0_REC_CTRL__rec_enable__disable 0 |
| #define R_SERIAL0_REC_CTRL__rec_enable__enable 1 |
| #define R_SERIAL0_REC_CTRL__rts___BITNR 5 |
| #define R_SERIAL0_REC_CTRL__rts___WIDTH 1 |
| #define R_SERIAL0_REC_CTRL__rts___active 0 |
| #define R_SERIAL0_REC_CTRL__rts___inactive 1 |
| #define R_SERIAL0_REC_CTRL__sampling__BITNR 4 |
| #define R_SERIAL0_REC_CTRL__sampling__WIDTH 1 |
| #define R_SERIAL0_REC_CTRL__sampling__middle 0 |
| #define R_SERIAL0_REC_CTRL__sampling__majority 1 |
| #define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 |
| #define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1 |
| #define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0 |
| #define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1 |
| #define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 |
| #define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1 |
| #define R_SERIAL0_REC_CTRL__rec_par__even 0 |
| #define R_SERIAL0_REC_CTRL__rec_par__odd 1 |
| #define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 |
| #define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1 |
| #define R_SERIAL0_REC_CTRL__rec_par_en__disable 0 |
| #define R_SERIAL0_REC_CTRL__rec_par_en__enable 1 |
| #define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 |
| #define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1 |
| #define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0 |
| #define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1 |
| |
| #define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061) |
| #define R_SERIAL0_TR_CTRL__txd__BITNR 7 |
| #define R_SERIAL0_TR_CTRL__txd__WIDTH 1 |
| #define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 |
| #define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1 |
| #define R_SERIAL0_TR_CTRL__tr_enable__disable 0 |
| #define R_SERIAL0_TR_CTRL__tr_enable__enable 1 |
| #define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 |
| #define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1 |
| #define R_SERIAL0_TR_CTRL__auto_cts__disabled 0 |
| #define R_SERIAL0_TR_CTRL__auto_cts__active 1 |
| #define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 |
| #define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1 |
| #define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0 |
| #define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1 |
| #define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 |
| #define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1 |
| #define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0 |
| #define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1 |
| #define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 |
| #define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1 |
| #define R_SERIAL0_TR_CTRL__tr_par__even 0 |
| #define R_SERIAL0_TR_CTRL__tr_par__odd 1 |
| #define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 |
| #define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1 |
| #define R_SERIAL0_TR_CTRL__tr_par_en__disable 0 |
| #define R_SERIAL0_TR_CTRL__tr_par_en__enable 1 |
| #define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 |
| #define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1 |
| #define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0 |
| #define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1 |
| |
| #define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060) |
| #define R_SERIAL0_TR_DATA__data_out__BITNR 0 |
| #define R_SERIAL0_TR_DATA__data_out__WIDTH 8 |
| |
| #define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060) |
| #define R_SERIAL0_READ__xoff_detect__BITNR 15 |
| #define R_SERIAL0_READ__xoff_detect__WIDTH 1 |
| #define R_SERIAL0_READ__xoff_detect__no_xoff 0 |
| #define R_SERIAL0_READ__xoff_detect__xoff 1 |
| #define R_SERIAL0_READ__cts___BITNR 14 |
| #define R_SERIAL0_READ__cts___WIDTH 1 |
| #define R_SERIAL0_READ__cts___active 0 |
| #define R_SERIAL0_READ__cts___inactive 1 |
| #define R_SERIAL0_READ__tr_ready__BITNR 13 |
| #define R_SERIAL0_READ__tr_ready__WIDTH 1 |
| #define R_SERIAL0_READ__tr_ready__full 0 |
| #define R_SERIAL0_READ__tr_ready__ready 1 |
| #define R_SERIAL0_READ__rxd__BITNR 12 |
| #define R_SERIAL0_READ__rxd__WIDTH 1 |
| #define R_SERIAL0_READ__overrun__BITNR 11 |
| #define R_SERIAL0_READ__overrun__WIDTH 1 |
| #define R_SERIAL0_READ__overrun__no 0 |
| #define R_SERIAL0_READ__overrun__yes 1 |
| #define R_SERIAL0_READ__par_err__BITNR 10 |
| #define R_SERIAL0_READ__par_err__WIDTH 1 |
| #define R_SERIAL0_READ__par_err__no 0 |
| #define R_SERIAL0_READ__par_err__yes 1 |
| #define R_SERIAL0_READ__framing_err__BITNR 9 |
| #define R_SERIAL0_READ__framing_err__WIDTH 1 |
| #define R_SERIAL0_READ__framing_err__no 0 |
| #define R_SERIAL0_READ__framing_err__yes 1 |
| #define R_SERIAL0_READ__data_avail__BITNR 8 |
| #define R_SERIAL0_READ__data_avail__WIDTH 1 |
| #define R_SERIAL0_READ__data_avail__no 0 |
| #define R_SERIAL0_READ__data_avail__yes 1 |
| #define R_SERIAL0_READ__data_in__BITNR 0 |
| #define R_SERIAL0_READ__data_in__WIDTH 8 |
| |
| #define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061) |
| #define R_SERIAL0_STATUS__xoff_detect__BITNR 7 |
| #define R_SERIAL0_STATUS__xoff_detect__WIDTH 1 |
| #define R_SERIAL0_STATUS__xoff_detect__no_xoff 0 |
| #define R_SERIAL0_STATUS__xoff_detect__xoff 1 |
| #define R_SERIAL0_STATUS__cts___BITNR 6 |
| #define R_SERIAL0_STATUS__cts___WIDTH 1 |
| #define R_SERIAL0_STATUS__cts___active 0 |
| #define R_SERIAL0_STATUS__cts___inactive 1 |
| #define R_SERIAL0_STATUS__tr_ready__BITNR 5 |
| #define R_SERIAL0_STATUS__tr_ready__WIDTH 1 |
| #define R_SERIAL0_STATUS__tr_ready__full 0 |
| #define R_SERIAL0_STATUS__tr_ready__ready 1 |
| #define R_SERIAL0_STATUS__rxd__BITNR 4 |
| #define R_SERIAL0_STATUS__rxd__WIDTH 1 |
| #define R_SERIAL0_STATUS__overrun__BITNR 3 |
| #define R_SERIAL0_STATUS__overrun__WIDTH 1 |
| #define R_SERIAL0_STATUS__overrun__no 0 |
| #define R_SERIAL0_STATUS__overrun__yes 1 |
| #define R_SERIAL0_STATUS__par_err__BITNR 2 |
| #define R_SERIAL0_STATUS__par_err__WIDTH 1 |
| #define R_SERIAL0_STATUS__par_err__no 0 |
| #define R_SERIAL0_STATUS__par_err__yes 1 |
| #define R_SERIAL0_STATUS__framing_err__BITNR 1 |
| #define R_SERIAL0_STATUS__framing_err__WIDTH 1 |
| #define R_SERIAL0_STATUS__framing_err__no 0 |
| #define R_SERIAL0_STATUS__framing_err__yes 1 |
| #define R_SERIAL0_STATUS__data_avail__BITNR 0 |
| #define R_SERIAL0_STATUS__data_avail__WIDTH 1 |
| #define R_SERIAL0_STATUS__data_avail__no 0 |
| #define R_SERIAL0_STATUS__data_avail__yes 1 |
| |
| #define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060) |
| #define R_SERIAL0_REC_DATA__data_in__BITNR 0 |
| #define R_SERIAL0_REC_DATA__data_in__WIDTH 8 |
| |
| #define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064) |
| #define R_SERIAL0_XOFF__tx_stop__BITNR 9 |
| #define R_SERIAL0_XOFF__tx_stop__WIDTH 1 |
| #define R_SERIAL0_XOFF__tx_stop__enable 0 |
| #define R_SERIAL0_XOFF__tx_stop__stop 1 |
| #define R_SERIAL0_XOFF__auto_xoff__BITNR 8 |
| #define R_SERIAL0_XOFF__auto_xoff__WIDTH 1 |
| #define R_SERIAL0_XOFF__auto_xoff__disable 0 |
| #define R_SERIAL0_XOFF__auto_xoff__enable 1 |
| #define R_SERIAL0_XOFF__xoff_char__BITNR 0 |
| #define R_SERIAL0_XOFF__xoff_char__WIDTH 8 |
| |
| #define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) |
| #define R_SERIAL1_CTRL__tr_baud__BITNR 28 |
| #define R_SERIAL1_CTRL__tr_baud__WIDTH 4 |
| #define R_SERIAL1_CTRL__tr_baud__c300Hz 0 |
| #define R_SERIAL1_CTRL__tr_baud__c600Hz 1 |
| #define R_SERIAL1_CTRL__tr_baud__c1200Hz 2 |
| #define R_SERIAL1_CTRL__tr_baud__c2400Hz 3 |
| #define R_SERIAL1_CTRL__tr_baud__c4800Hz 4 |
| #define R_SERIAL1_CTRL__tr_baud__c9600Hz 5 |
| #define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6 |
| #define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7 |
| #define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8 |
| #define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9 |
| #define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10 |
| #define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11 |
| #define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12 |
| #define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13 |
| #define R_SERIAL1_CTRL__tr_baud__c6250kHz 14 |
| #define R_SERIAL1_CTRL__tr_baud__reserved 15 |
| #define R_SERIAL1_CTRL__rec_baud__BITNR 24 |
| #define R_SERIAL1_CTRL__rec_baud__WIDTH 4 |
| #define R_SERIAL1_CTRL__rec_baud__c300Hz 0 |
| #define R_SERIAL1_CTRL__rec_baud__c600Hz 1 |
| #define R_SERIAL1_CTRL__rec_baud__c1200Hz 2 |
| #define R_SERIAL1_CTRL__rec_baud__c2400Hz 3 |
| #define R_SERIAL1_CTRL__rec_baud__c4800Hz 4 |
| #define R_SERIAL1_CTRL__rec_baud__c9600Hz 5 |
| #define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6 |
| #define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7 |
| #define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8 |
| #define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9 |
| #define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10 |
| #define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11 |
| #define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12 |
| #define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13 |
| #define R_SERIAL1_CTRL__rec_baud__c6250kHz 14 |
| #define R_SERIAL1_CTRL__rec_baud__reserved 15 |
| #define R_SERIAL1_CTRL__dma_err__BITNR 23 |
| #define R_SERIAL1_CTRL__dma_err__WIDTH 1 |
| #define R_SERIAL1_CTRL__dma_err__stop 0 |
| #define R_SERIAL1_CTRL__dma_err__ignore 1 |
| #define R_SERIAL1_CTRL__rec_enable__BITNR 22 |
| #define R_SERIAL1_CTRL__rec_enable__WIDTH 1 |
| #define R_SERIAL1_CTRL__rec_enable__disable 0 |
| #define R_SERIAL1_CTRL__rec_enable__enable 1 |
| #define R_SERIAL1_CTRL__rts___BITNR 21 |
| #define R_SERIAL1_CTRL__rts___WIDTH 1 |
| #define R_SERIAL1_CTRL__rts___active 0 |
| #define R_SERIAL1_CTRL__rts___inactive 1 |
| #define R_SERIAL1_CTRL__sampling__BITNR 20 |
| #define R_SERIAL1_CTRL__sampling__WIDTH 1 |
| #define R_SERIAL1_CTRL__sampling__middle 0 |
| #define R_SERIAL1_CTRL__sampling__majority 1 |
| #define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 |
| #define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1 |
| #define R_SERIAL1_CTRL__rec_stick_par__normal 0 |
| #define R_SERIAL1_CTRL__rec_stick_par__stick 1 |
| #define R_SERIAL1_CTRL__rec_par__BITNR 18 |
| #define R_SERIAL1_CTRL__rec_par__WIDTH 1 |
| #define R_SERIAL1_CTRL__rec_par__even 0 |
| #define R_SERIAL1_CTRL__rec_par__odd 1 |
| #define R_SERIAL1_CTRL__rec_par_en__BITNR 17 |
| #define R_SERIAL1_CTRL__rec_par_en__WIDTH 1 |
| #define R_SERIAL1_CTRL__rec_par_en__disable 0 |
| #define R_SERIAL1_CTRL__rec_par_en__enable 1 |
| #define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 |
| #define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1 |
| #define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0 |
| #define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1 |
| #define R_SERIAL1_CTRL__txd__BITNR 15 |
| #define R_SERIAL1_CTRL__txd__WIDTH 1 |
| #define R_SERIAL1_CTRL__tr_enable__BITNR 14 |
| #define R_SERIAL1_CTRL__tr_enable__WIDTH 1 |
| #define R_SERIAL1_CTRL__tr_enable__disable 0 |
| #define R_SERIAL1_CTRL__tr_enable__enable 1 |
| #define R_SERIAL1_CTRL__auto_cts__BITNR 13 |
| #define R_SERIAL1_CTRL__auto_cts__WIDTH 1 |
| #define R_SERIAL1_CTRL__auto_cts__disabled 0 |
| #define R_SERIAL1_CTRL__auto_cts__active 1 |
| #define R_SERIAL1_CTRL__stop_bits__BITNR 12 |
| #define R_SERIAL1_CTRL__stop_bits__WIDTH 1 |
| #define R_SERIAL1_CTRL__stop_bits__one_bit 0 |
| #define R_SERIAL1_CTRL__stop_bits__two_bits 1 |
| #define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 |
| #define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1 |
| #define R_SERIAL1_CTRL__tr_stick_par__normal 0 |
| #define R_SERIAL1_CTRL__tr_stick_par__stick 1 |
| #define R_SERIAL1_CTRL__tr_par__BITNR 10 |
| #define R_SERIAL1_CTRL__tr_par__WIDTH 1 |
| #define R_SERIAL1_CTRL__tr_par__even 0 |
| #define R_SERIAL1_CTRL__tr_par__odd 1 |
| #define R_SERIAL1_CTRL__tr_par_en__BITNR 9 |
| #define R_SERIAL1_CTRL__tr_par_en__WIDTH 1 |
| #define R_SERIAL1_CTRL__tr_par_en__disable 0 |
| #define R_SERIAL1_CTRL__tr_par_en__enable 1 |
| #define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 |
| #define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1 |
| #define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0 |
| #define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1 |
| #define R_SERIAL1_CTRL__data_out__BITNR 0 |
| #define R_SERIAL1_CTRL__data_out__WIDTH 8 |
| |
| #define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b) |
| #define R_SERIAL1_BAUD__tr_baud__BITNR 4 |
| #define R_SERIAL1_BAUD__tr_baud__WIDTH 4 |
| #define R_SERIAL1_BAUD__tr_baud__c300Hz 0 |
| #define R_SERIAL1_BAUD__tr_baud__c600Hz 1 |
| #define R_SERIAL1_BAUD__tr_baud__c1200Hz 2 |
| #define R_SERIAL1_BAUD__tr_baud__c2400Hz 3 |
| #define R_SERIAL1_BAUD__tr_baud__c4800Hz 4 |
| #define R_SERIAL1_BAUD__tr_baud__c9600Hz 5 |
| #define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6 |
| #define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7 |
| #define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8 |
| #define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9 |
| #define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10 |
| #define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11 |
| #define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12 |
| #define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13 |
| #define R_SERIAL1_BAUD__tr_baud__c6250kHz 14 |
| #define R_SERIAL1_BAUD__tr_baud__reserved 15 |
| #define R_SERIAL1_BAUD__rec_baud__BITNR 0 |
| #define R_SERIAL1_BAUD__rec_baud__WIDTH 4 |
| #define R_SERIAL1_BAUD__rec_baud__c300Hz 0 |
| #define R_SERIAL1_BAUD__rec_baud__c600Hz 1 |
| #define R_SERIAL1_BAUD__rec_baud__c1200Hz 2 |
| #define R_SERIAL1_BAUD__rec_baud__c2400Hz 3 |
| #define R_SERIAL1_BAUD__rec_baud__c4800Hz 4 |
| #define R_SERIAL1_BAUD__rec_baud__c9600Hz 5 |
| #define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6 |
| #define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7 |
| #define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8 |
| #define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9 |
| #define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10 |
| #define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11 |
| #define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12 |
| #define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13 |
| #define R_SERIAL1_BAUD__rec_baud__c6250kHz 14 |
| #define R_SERIAL1_BAUD__rec_baud__reserved 15 |
| |
| #define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a) |
| #define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 |
| #define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1 |
| #define R_SERIAL1_REC_CTRL__dma_err__stop 0 |
| #define R_SERIAL1_REC_CTRL__dma_err__ignore 1 |
| #define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 |
| #define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1 |
| #define R_SERIAL1_REC_CTRL__rec_enable__disable 0 |
| #define R_SERIAL1_REC_CTRL__rec_enable__enable 1 |
| #define R_SERIAL1_REC_CTRL__rts___BITNR 5 |
| #define R_SERIAL1_REC_CTRL__rts___WIDTH 1 |
| #define R_SERIAL1_REC_CTRL__rts___active 0 |
| #define R_SERIAL1_REC_CTRL__rts___inactive 1 |
| #define R_SERIAL1_REC_CTRL__sampling__BITNR 4 |
| #define R_SERIAL1_REC_CTRL__sampling__WIDTH 1 |
| #define R_SERIAL1_REC_CTRL__sampling__middle 0 |
| #define R_SERIAL1_REC_CTRL__sampling__majority 1 |
| #define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 |
| #define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1 |
| #define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0 |
| #define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1 |
| #define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 |
| #define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1 |
| #define R_SERIAL1_REC_CTRL__rec_par__even 0 |
| #define R_SERIAL1_REC_CTRL__rec_par__odd 1 |
| #define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 |
| #define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1 |
| #define R_SERIAL1_REC_CTRL__rec_par_en__disable 0 |
| #define R_SERIAL1_REC_CTRL__rec_par_en__enable 1 |
| #define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 |
| #define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1 |
| #define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0 |
| #define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1 |
| |
| #define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069) |
| #define R_SERIAL1_TR_CTRL__txd__BITNR 7 |
| #define R_SERIAL1_TR_CTRL__txd__WIDTH 1 |
| #define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 |
| #define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1 |
| #define R_SERIAL1_TR_CTRL__tr_enable__disable 0 |
| #define R_SERIAL1_TR_CTRL__tr_enable__enable 1 |
| #define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 |
| #define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1 |
| #define R_SERIAL1_TR_CTRL__auto_cts__disabled 0 |
| #define R_SERIAL1_TR_CTRL__auto_cts__active 1 |
| #define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 |
| #define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1 |
| #define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0 |
| #define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1 |
| #define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 |
| #define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1 |
| #define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0 |
| #define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1 |
| #define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 |
| #define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1 |
| #define R_SERIAL1_TR_CTRL__tr_par__even 0 |
| #define R_SERIAL1_TR_CTRL__tr_par__odd 1 |
| #define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 |
| #define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1 |
| #define R_SERIAL1_TR_CTRL__tr_par_en__disable 0 |
| #define R_SERIAL1_TR_CTRL__tr_par_en__enable 1 |
| #define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 |
| #define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1 |
| #define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0 |
| #define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1 |
| |
| #define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068) |
| #define R_SERIAL1_TR_DATA__data_out__BITNR 0 |
| #define R_SERIAL1_TR_DATA__data_out__WIDTH 8 |
| |
| #define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068) |
| #define R_SERIAL1_READ__xoff_detect__BITNR 15 |
| #define R_SERIAL1_READ__xoff_detect__WIDTH 1 |
| #define R_SERIAL1_READ__xoff_detect__no_xoff 0 |
| #define R_SERIAL1_READ__xoff_detect__xoff 1 |
| #define R_SERIAL1_READ__cts___BITNR 14 |
| #define R_SERIAL1_READ__cts___WIDTH 1 |
| #define R_SERIAL1_READ__cts___active 0 |
| #define R_SERIAL1_READ__cts___inactive 1 |
| #define R_SERIAL1_READ__tr_ready__BITNR 13 |
| #define R_SERIAL1_READ__tr_ready__WIDTH 1 |
| #define R_SERIAL1_READ__tr_ready__full 0 |
| #define R_SERIAL1_READ__tr_ready__ready 1 |
| #define R_SERIAL1_READ__rxd__BITNR 12 |
| #define R_SERIAL1_READ__rxd__WIDTH 1 |
| #define R_SERIAL1_READ__overrun__BITNR 11 |
| #define R_SERIAL1_READ__overrun__WIDTH 1 |
| #define R_SERIAL1_READ__overrun__no 0 |
| #define R_SERIAL1_READ__overrun__yes 1 |
| #define R_SERIAL1_READ__par_err__BITNR 10 |
| #define R_SERIAL1_READ__par_err__WIDTH 1 |
| #define R_SERIAL1_READ__par_err__no 0 |
| #define R_SERIAL1_READ__par_err__yes 1 |
| #define R_SERIAL1_READ__framing_err__BITNR 9 |
| #define R_SERIAL1_READ__framing_err__WIDTH 1 |
| #define R_SERIAL1_READ__framing_err__no 0 |
| #define R_SERIAL1_READ__framing_err__yes 1 |
| #define R_SERIAL1_READ__data_avail__BITNR 8 |
| #define R_SERIAL1_READ__data_avail__WIDTH 1 |
| #define R_SERIAL1_READ__data_avail__no 0 |
| #define R_SERIAL1_READ__data_avail__yes 1 |
| #define R_SERIAL1_READ__data_in__BITNR 0 |
| #define R_SERIAL1_READ__data_in__WIDTH 8 |
| |
| #define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069) |
| #define R_SERIAL1_STATUS__xoff_detect__BITNR 7 |
| #define R_SERIAL1_STATUS__xoff_detect__WIDTH 1 |
| #define R_SERIAL1_STATUS__xoff_detect__no_xoff 0 |
| #define R_SERIAL1_STATUS__xoff_detect__xoff 1 |
| #define R_SERIAL1_STATUS__cts___BITNR 6 |
| #define R_SERIAL1_STATUS__cts___WIDTH 1 |
| #define R_SERIAL1_STATUS__cts___active 0 |
| #define R_SERIAL1_STATUS__cts___inactive 1 |
| #define R_SERIAL1_STATUS__tr_ready__BITNR 5 |
| #define R_SERIAL1_STATUS__tr_ready__WIDTH 1 |
| #define R_SERIAL1_STATUS__tr_ready__full 0 |
| #define R_SERIAL1_STATUS__tr_ready__ready 1 |
| #define R_SERIAL1_STATUS__rxd__BITNR 4 |
| #define R_SERIAL1_STATUS__rxd__WIDTH 1 |
| #define R_SERIAL1_STATUS__overrun__BITNR 3 |
| #define R_SERIAL1_STATUS__overrun__WIDTH 1 |
| #define R_SERIAL1_STATUS__overrun__no 0 |
| #define R_SERIAL1_STATUS__overrun__yes 1 |
| #define R_SERIAL1_STATUS__par_err__BITNR 2 |
| #define R_SERIAL1_STATUS__par_err__WIDTH 1 |
| #define R_SERIAL1_STATUS__par_err__no 0 |
| #define R_SERIAL1_STATUS__par_err__yes 1 |
| #define R_SERIAL1_STATUS__framing_err__BITNR 1 |
| #define R_SERIAL1_STATUS__framing_err__WIDTH 1 |
| #define R_SERIAL1_STATUS__framing_err__no 0 |
| #define R_SERIAL1_STATUS__framing_err__yes 1 |
| #define R_SERIAL1_STATUS__data_avail__BITNR 0 |
| #define R_SERIAL1_STATUS__data_avail__WIDTH 1 |
| #define R_SERIAL1_STATUS__data_avail__no 0 |
| #define R_SERIAL1_STATUS__data_avail__yes 1 |
| |
| #define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068) |
| #define R_SERIAL1_REC_DATA__data_in__BITNR 0 |
| #define R_SERIAL1_REC_DATA__data_in__WIDTH 8 |
| |
| #define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c) |
| #define R_SERIAL1_XOFF__tx_stop__BITNR 9 |
| #define R_SERIAL1_XOFF__tx_stop__WIDTH 1 |
| #define R_SERIAL1_XOFF__tx_stop__enable 0 |
| #define R_SERIAL1_XOFF__tx_stop__stop 1 |
| #define R_SERIAL1_XOFF__auto_xoff__BITNR 8 |
| #define R_SERIAL1_XOFF__auto_xoff__WIDTH 1 |
| #define R_SERIAL1_XOFF__auto_xoff__disable 0 |
| #define R_SERIAL1_XOFF__auto_xoff__enable 1 |
| #define R_SERIAL1_XOFF__xoff_char__BITNR 0 |
| #define R_SERIAL1_XOFF__xoff_char__WIDTH 8 |
| |
| #define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070) |
| #define R_SERIAL2_CTRL__tr_baud__BITNR 28 |
| #define R_SERIAL2_CTRL__tr_baud__WIDTH 4 |
| #define R_SERIAL2_CTRL__tr_baud__c300Hz 0 |
| #define R_SERIAL2_CTRL__tr_baud__c600Hz 1 |
| #define R_SERIAL2_CTRL__tr_baud__c1200Hz 2 |
| #define R_SERIAL2_CTRL__tr_baud__c2400Hz 3 |
| #define R_SERIAL2_CTRL__tr_baud__c4800Hz 4 |
| #define R_SERIAL2_CTRL__tr_baud__c9600Hz 5 |
| #define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6 |
| #define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7 |
| #define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8 |
| #define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9 |
| #define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10 |
| #define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11 |
| #define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12 |
| #define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13 |
| #define R_SERIAL2_CTRL__tr_baud__c6250kHz 14 |
| #define R_SERIAL2_CTRL__tr_baud__reserved 15 |
| #define R_SERIAL2_CTRL__rec_baud__BITNR 24 |
| #define R_SERIAL2_CTRL__rec_baud__WIDTH 4 |
| #define R_SERIAL2_CTRL__rec_baud__c300Hz 0 |
| #define R_SERIAL2_CTRL__rec_baud__c600Hz 1 |
| #define R_SERIAL2_CTRL__rec_baud__c1200Hz 2 |
| #define R_SERIAL2_CTRL__rec_baud__c2400Hz 3 |
| #define R_SERIAL2_CTRL__rec_baud__c4800Hz 4 |
| #define R_SERIAL2_CTRL__rec_baud__c9600Hz 5 |
| #define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6 |
| #define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7 |
| #define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8 |
| #define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9 |
| #define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10 |
| #define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11 |
| #define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12 |
| #define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13 |
| #define R_SERIAL2_CTRL__rec_baud__c6250kHz 14 |
| #define R_SERIAL2_CTRL__rec_baud__reserved 15 |
| #define R_SERIAL2_CTRL__dma_err__BITNR 23 |
| #define R_SERIAL2_CTRL__dma_err__WIDTH 1 |
| #define R_SERIAL2_CTRL__dma_err__stop 0 |
| #define R_SERIAL2_CTRL__dma_err__ignore 1 |
| #define R_SERIAL2_CTRL__rec_enable__BITNR 22 |
| #define R_SERIAL2_CTRL__rec_enable__WIDTH 1 |
| #define R_SERIAL2_CTRL__rec_enable__disable 0 |
| #define R_SERIAL2_CTRL__rec_enable__enable 1 |
| #define R_SERIAL2_CTRL__rts___BITNR 21 |
| #define R_SERIAL2_CTRL__rts___WIDTH 1 |
| #define R_SERIAL2_CTRL__rts___active 0 |
| #define R_SERIAL2_CTRL__rts___inactive 1 |
| #define R_SERIAL2_CTRL__sampling__BITNR 20 |
| #define R_SERIAL2_CTRL__sampling__WIDTH 1 |
| #define R_SERIAL2_CTRL__sampling__middle 0 |
| #define R_SERIAL2_CTRL__sampling__majority 1 |
| #define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 |
| #define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1 |
| #define R_SERIAL2_CTRL__rec_stick_par__normal 0 |
| #define R_SERIAL2_CTRL__rec_stick_par__stick 1 |
| #define R_SERIAL2_CTRL__rec_par__BITNR 18 |
| #define R_SERIAL2_CTRL__rec_par__WIDTH 1 |
| #define R_SERIAL2_CTRL__rec_par__even 0 |
| #define R_SERIAL2_CTRL__rec_par__odd 1 |
| #define R_SERIAL2_CTRL__rec_par_en__BITNR 17 |
| #define R_SERIAL2_CTRL__rec_par_en__WIDTH 1 |
| #define R_SERIAL2_CTRL__rec_par_en__disable 0 |
| #define R_SERIAL2_CTRL__rec_par_en__enable 1 |
| #define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 |
| #define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1 |
| #define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0 |
| #define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1 |
| #define R_SERIAL2_CTRL__txd__BITNR 15 |
| #define R_SERIAL2_CTRL__txd__WIDTH 1 |
| #define R_SERIAL2_CTRL__tr_enable__BITNR 14 |
| #define R_SERIAL2_CTRL__tr_enable__WIDTH 1 |
| #define R_SERIAL2_CTRL__tr_enable__disable 0 |
| #define R_SERIAL2_CTRL__tr_enable__enable 1 |
| #define R_SERIAL2_CTRL__auto_cts__BITNR 13 |
| #define R_SERIAL2_CTRL__auto_cts__WIDTH 1 |
| #define R_SERIAL2_CTRL__auto_cts__disabled 0 |
| #define R_SERIAL2_CTRL__auto_cts__active 1 |
| #define R_SERIAL2_CTRL__stop_bits__BITNR 12 |
| #define R_SERIAL2_CTRL__stop_bits__WIDTH 1 |
| #define R_SERIAL2_CTRL__stop_bits__one_bit 0 |
| #define R_SERIAL2_CTRL__stop_bits__two_bits 1 |
| #define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 |
| #define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1 |
| #define R_SERIAL2_CTRL__tr_stick_par__normal 0 |
| #define R_SERIAL2_CTRL__tr_stick_par__stick 1 |
| #define R_SERIAL2_CTRL__tr_par__BITNR 10 |
| #define R_SERIAL2_CTRL__tr_par__WIDTH 1 |
| #define R_SERIAL2_CTRL__tr_par__even 0 |
| #define R_SERIAL2_CTRL__tr_par__odd 1 |
| #define R_SERIAL2_CTRL__tr_par_en__BITNR 9 |
| #define R_SERIAL2_CTRL__tr_par_en__WIDTH 1 |
| #define R_SERIAL2_CTRL__tr_par_en__disable 0 |
| #define R_SERIAL2_CTRL__tr_par_en__enable 1 |
| #define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 |
| #define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1 |
| #define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0 |
| #define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1 |
| #define R_SERIAL2_CTRL__data_out__BITNR 0 |
| #define R_SERIAL2_CTRL__data_out__WIDTH 8 |
| |
| #define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073) |
| #define R_SERIAL2_BAUD__tr_baud__BITNR 4 |
| #define R_SERIAL2_BAUD__tr_baud__WIDTH 4 |
| #define R_SERIAL2_BAUD__tr_baud__c300Hz 0 |
| #define R_SERIAL2_BAUD__tr_baud__c600Hz 1 |
| #define R_SERIAL2_BAUD__tr_baud__c1200Hz 2 |
| #define R_SERIAL2_BAUD__tr_baud__c2400Hz 3 |
| #define R_SERIAL2_BAUD__tr_baud__c4800Hz 4 |
| #define R_SERIAL2_BAUD__tr_baud__c9600Hz 5 |
| #define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6 |
| #define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7 |
| #define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8 |
| #define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9 |
| #define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10 |
| #define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11 |
| #define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12 |
| #define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13 |
| #define R_SERIAL2_BAUD__tr_baud__c6250kHz 14 |
| #define R_SERIAL2_BAUD__tr_baud__reserved 15 |
| #define R_SERIAL2_BAUD__rec_baud__BITNR 0 |
| #define R_SERIAL2_BAUD__rec_baud__WIDTH 4 |
| #define R_SERIAL2_BAUD__rec_baud__c300Hz 0 |
| #define R_SERIAL2_BAUD__rec_baud__c600Hz 1 |
| #define R_SERIAL2_BAUD__rec_baud__c1200Hz 2 |
| #define R_SERIAL2_BAUD__rec_baud__c2400Hz 3 |
| #define R_SERIAL2_BAUD__rec_baud__c4800Hz 4 |
| #define R_SERIAL2_BAUD__rec_baud__c9600Hz 5 |
| #define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6 |
| #define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7 |
| #define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8 |
| #define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9 |
| #define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10 |
| #define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11 |
| #define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12 |
| #define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13 |
| #define R_SERIAL2_BAUD__rec_baud__c6250kHz 14 |
| #define R_SERIAL2_BAUD__rec_baud__reserved 15 |
| |
| #define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072) |
| #define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 |
| #define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1 |
| #define R_SERIAL2_REC_CTRL__dma_err__stop 0 |
| #define R_SERIAL2_REC_CTRL__dma_err__ignore 1 |
| #define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 |
| #define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1 |
| #define R_SERIAL2_REC_CTRL__rec_enable__disable 0 |
| #define R_SERIAL2_REC_CTRL__rec_enable__enable 1 |
| #define R_SERIAL2_REC_CTRL__rts___BITNR 5 |
| #define R_SERIAL2_REC_CTRL__rts___WIDTH 1 |
| #define R_SERIAL2_REC_CTRL__rts___active 0 |
| #define R_SERIAL2_REC_CTRL__rts___inactive 1 |
| #define R_SERIAL2_REC_CTRL__sampling__BITNR 4 |
| #define R_SERIAL2_REC_CTRL__sampling__WIDTH 1 |
| #define R_SERIAL2_REC_CTRL__sampling__middle 0 |
| #define R_SERIAL2_REC_CTRL__sampling__majority 1 |
| #define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 |
| #define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1 |
| #define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0 |
| #define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1 |
| #define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 |
| #define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1 |
| #define R_SERIAL2_REC_CTRL__rec_par__even 0 |
| #define R_SERIAL2_REC_CTRL__rec_par__odd 1 |
| #define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 |
| #define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1 |
| #define R_SERIAL2_REC_CTRL__rec_par_en__disable 0 |
| #define R_SERIAL2_REC_CTRL__rec_par_en__enable 1 |
| #define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 |
| #define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1 |
| #define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0 |
| #define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1 |
| |
| #define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071) |
| #define R_SERIAL2_TR_CTRL__txd__BITNR 7 |
| #define R_SERIAL2_TR_CTRL__txd__WIDTH 1 |
| #define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 |
| #define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1 |
| #define R_SERIAL2_TR_CTRL__tr_enable__disable 0 |
| #define R_SERIAL2_TR_CTRL__tr_enable__enable 1 |
| #define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 |
| #define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1 |
| #define R_SERIAL2_TR_CTRL__auto_cts__disabled 0 |
| #define R_SERIAL2_TR_CTRL__auto_cts__active 1 |
| #define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 |
| #define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1 |
| #define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0 |
| #define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1 |
| #define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 |
| #define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1 |
| #define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0 |
| #define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1 |
| #define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 |
| #define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1 |
| #define R_SERIAL2_TR_CTRL__tr_par__even 0 |
| #define R_SERIAL2_TR_CTRL__tr_par__odd 1 |
| #define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 |
| #define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1 |
| #define R_SERIAL2_TR_CTRL__tr_par_en__disable 0 |
| #define R_SERIAL2_TR_CTRL__tr_par_en__enable 1 |
| #define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 |
| #define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1 |
| #define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0 |
| #define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1 |
| |
| #define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070) |
| #define R_SERIAL2_TR_DATA__data_out__BITNR 0 |
| #define R_SERIAL2_TR_DATA__data_out__WIDTH 8 |
| |
| #define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070) |
| #define R_SERIAL2_READ__xoff_detect__BITNR 15 |
| #define R_SERIAL2_READ__xoff_detect__WIDTH 1 |
| #define R_SERIAL2_READ__xoff_detect__no_xoff 0 |
| #define R_SERIAL2_READ__xoff_detect__xoff 1 |
| #define R_SERIAL2_READ__cts___BITNR 14 |
| #define R_SERIAL2_READ__cts___WIDTH 1 |
| #define R_SERIAL2_READ__cts___active 0 |
| #define R_SERIAL2_READ__cts___inactive 1 |
| #define R_SERIAL2_READ__tr_ready__BITNR 13 |
| #define R_SERIAL2_READ__tr_ready__WIDTH 1 |
| #define R_SERIAL2_READ__tr_ready__full 0 |
| #define R_SERIAL2_READ__tr_ready__ready 1 |
| #define R_SERIAL2_READ__rxd__BITNR 12 |
| #define R_SERIAL2_READ__rxd__WIDTH 1 |
| #define R_SERIAL2_READ__overrun__BITNR 11 |
| #define R_SERIAL2_READ__overrun__WIDTH 1 |
| #define R_SERIAL2_READ__overrun__no 0 |
| #define R_SERIAL2_READ__overrun__yes 1 |
| #define R_SERIAL2_READ__par_err__BITNR 10 |
| #define R_SERIAL2_READ__par_err__WIDTH 1 |
| #define R_SERIAL2_READ__par_err__no 0 |
| #define R_SERIAL2_READ__par_err__yes 1 |
| #define R_SERIAL2_READ__framing_err__BITNR 9 |
| #define R_SERIAL2_READ__framing_err__WIDTH 1 |
| #define R_SERIAL2_READ__framing_err__no 0 |
| #define R_SERIAL2_READ__framing_err__yes 1 |
| #define R_SERIAL2_READ__data_avail__BITNR 8 |
| #define R_SERIAL2_READ__data_avail__WIDTH 1 |
| #define R_SERIAL2_READ__data_avail__no 0 |
| #define R_SERIAL2_READ__data_avail__yes 1 |
| #define R_SERIAL2_READ__data_in__BITNR 0 |
| #define R_SERIAL2_READ__data_in__WIDTH 8 |
| |
| #define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071) |
| #define R_SERIAL2_STATUS__xoff_detect__BITNR 7 |
| #define R_SERIAL2_STATUS__xoff_detect__WIDTH 1 |
| #define R_SERIAL2_STATUS__xoff_detect__no_xoff 0 |
| #define R_SERIAL2_STATUS__xoff_detect__xoff 1 |
| #define R_SERIAL2_STATUS__cts___BITNR 6 |
| #define R_SERIAL2_STATUS__cts___WIDTH 1 |
| #define R_SERIAL2_STATUS__cts___active 0 |
| #define R_SERIAL2_STATUS__cts___inactive 1 |
| #define R_SERIAL2_STATUS__tr_ready__BITNR 5 |
| #define R_SERIAL2_STATUS__tr_ready__WIDTH 1 |
| #define R_SERIAL2_STATUS__tr_ready__full 0 |
| #define R_SERIAL2_STATUS__tr_ready__ready 1 |
| #define R_SERIAL2_STATUS__rxd__BITNR 4 |
| #define R_SERIAL2_STATUS__rxd__WIDTH 1 |
| #define R_SERIAL2_STATUS__overrun__BITNR 3 |
| #define R_SERIAL2_STATUS__overrun__WIDTH 1 |
| #define R_SERIAL2_STATUS__overrun__no 0 |
| #define R_SERIAL2_STATUS__overrun__yes 1 |
| #define R_SERIAL2_STATUS__par_err__BITNR 2 |
| #define R_SERIAL2_STATUS__par_err__WIDTH 1 |
| #define R_SERIAL2_STATUS__par_err__no 0 |
| #define R_SERIAL2_STATUS__par_err__yes 1 |
| #define R_SERIAL2_STATUS__framing_err__BITNR 1 |
| #define R_SERIAL2_STATUS__framing_err__WIDTH 1 |
| #define R_SERIAL2_STATUS__framing_err__no 0 |
| #define R_SERIAL2_STATUS__framing_err__yes 1 |
| #define R_SERIAL2_STATUS__data_avail__BITNR 0 |
| #define R_SERIAL2_STATUS__data_avail__WIDTH 1 |
| #define R_SERIAL2_STATUS__data_avail__no 0 |
| #define R_SERIAL2_STATUS__data_avail__yes 1 |
| |
| #define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070) |
| #define R_SERIAL2_REC_DATA__data_in__BITNR 0 |
| #define R_SERIAL2_REC_DATA__data_in__WIDTH 8 |
| |
| #define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074) |
| #define R_SERIAL2_XOFF__tx_stop__BITNR 9 |
| #define R_SERIAL2_XOFF__tx_stop__WIDTH 1 |
| #define R_SERIAL2_XOFF__tx_stop__enable 0 |
| #define R_SERIAL2_XOFF__tx_stop__stop 1 |
| #define R_SERIAL2_XOFF__auto_xoff__BITNR 8 |
| #define R_SERIAL2_XOFF__auto_xoff__WIDTH 1 |
| #define R_SERIAL2_XOFF__auto_xoff__disable 0 |
| #define R_SERIAL2_XOFF__auto_xoff__enable 1 |
| #define R_SERIAL2_XOFF__xoff_char__BITNR 0 |
| #define R_SERIAL2_XOFF__xoff_char__WIDTH 8 |
| |
| #define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) |
| #define R_SERIAL3_CTRL__tr_baud__BITNR 28 |
| #define R_SERIAL3_CTRL__tr_baud__WIDTH 4 |
| #define R_SERIAL3_CTRL__tr_baud__c300Hz 0 |
| #define R_SERIAL3_CTRL__tr_baud__c600Hz 1 |
| #define R_SERIAL3_CTRL__tr_baud__c1200Hz 2 |
| #define R_SERIAL3_CTRL__tr_baud__c2400Hz 3 |
| #define R_SERIAL3_CTRL__tr_baud__c4800Hz 4 |
| #define R_SERIAL3_CTRL__tr_baud__c9600Hz 5 |
| #define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6 |
| #define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7 |
| #define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8 |
| #define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9 |
| #define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10 |
| #define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11 |
| #define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12 |
| #define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13 |
| #define R_SERIAL3_CTRL__tr_baud__c6250kHz 14 |
| #define R_SERIAL3_CTRL__tr_baud__reserved 15 |
| #define R_SERIAL3_CTRL__rec_baud__BITNR 24 |
| #define R_SERIAL3_CTRL__rec_baud__WIDTH 4 |
| #define R_SERIAL3_CTRL__rec_baud__c300Hz 0 |
| #define R_SERIAL3_CTRL__rec_baud__c600Hz 1 |
| #define R_SERIAL3_CTRL__rec_baud__c1200Hz 2 |
| #define R_SERIAL3_CTRL__rec_baud__c2400Hz 3 |
| #define R_SERIAL3_CTRL__rec_baud__c4800Hz 4 |
| #define R_SERIAL3_CTRL__rec_baud__c9600Hz 5 |
| #define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6 |
| #define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7 |
| #define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8 |
| #define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9 |
| #define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10 |
| #define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11 |
| #define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12 |
| #define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13 |
| #define R_SERIAL3_CTRL__rec_baud__c6250kHz 14 |
| #define R_SERIAL3_CTRL__rec_baud__reserved 15 |
| #define R_SERIAL3_CTRL__dma_err__BITNR 23 |
| #define R_SERIAL3_CTRL__dma_err__WIDTH 1 |
| #define R_SERIAL3_CTRL__dma_err__stop 0 |
| #define R_SERIAL3_CTRL__dma_err__ignore 1 |
| #define R_SERIAL3_CTRL__rec_enable__BITNR 22 |
| #define R_SERIAL3_CTRL__rec_enable__WIDTH 1 |
| #define R_SERIAL3_CTRL__rec_enable__disable 0 |
| #define R_SERIAL3_CTRL__rec_enable__enable 1 |
| #define R_SERIAL3_CTRL__rts___BITNR 21 |
| #define R_SERIAL3_CTRL__rts___WIDTH 1 |
| #define R_SERIAL3_CTRL__rts___active 0 |
| #define R_SERIAL3_CTRL__rts___inactive 1 |
| #define R_SERIAL3_CTRL__sampling__BITNR 20 |
| #define R_SERIAL3_CTRL__sampling__WIDTH 1 |
| #define R_SERIAL3_CTRL__sampling__middle 0 |
| #define R_SERIAL3_CTRL__sampling__majority 1 |
| #define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 |
| #define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1 |
| #define R_SERIAL3_CTRL__rec_stick_par__normal 0 |
| #define R_SERIAL3_CTRL__rec_stick_par__stick 1 |
| #define R_SERIAL3_CTRL__rec_par__BITNR 18 |
| #define R_SERIAL3_CTRL__rec_par__WIDTH 1 |
| #define R_SERIAL3_CTRL__rec_par__even 0 |
| #define R_SERIAL3_CTRL__rec_par__odd 1 |
| #define R_SERIAL3_CTRL__rec_par_en__BITNR 17 |
| #define R_SERIAL3_CTRL__rec_par_en__WIDTH 1 |
| #define R_SERIAL3_CTRL__rec_par_en__disable 0 |
| #define R_SERIAL3_CTRL__rec_par_en__enable 1 |
| #define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 |
| #define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1 |
| #define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0 |
| #define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1 |
| #define R_SERIAL3_CTRL__txd__BITNR 15 |
| #define R_SERIAL3_CTRL__txd__WIDTH 1 |
| #define R_SERIAL3_CTRL__tr_enable__BITNR 14 |
| #define R_SERIAL3_CTRL__tr_enable__WIDTH 1 |
| #define R_SERIAL3_CTRL__tr_enable__disable 0 |
| #define R_SERIAL3_CTRL__tr_enable__enable 1 |
| #define R_SERIAL3_CTRL__auto_cts__BITNR 13 |
| #define R_SERIAL3_CTRL__auto_cts__WIDTH 1 |
| #define R_SERIAL3_CTRL__auto_cts__disabled 0 |
| #define R_SERIAL3_CTRL__auto_cts__active 1 |
| #define R_SERIAL3_CTRL__stop_bits__BITNR 12 |
| #define R_SERIAL3_CTRL__stop_bits__WIDTH 1 |
| #define R_SERIAL3_CTRL__stop_bits__one_bit 0 |
| #define R_SERIAL3_CTRL__stop_bits__two_bits 1 |
| #define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 |
| #define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1 |
| #define R_SERIAL3_CTRL__tr_stick_par__normal 0 |
| #define R_SERIAL3_CTRL__tr_stick_par__stick 1 |
| #define R_SERIAL3_CTRL__tr_par__BITNR 10 |
| #define R_SERIAL3_CTRL__tr_par__WIDTH 1 |
| #define R_SERIAL3_CTRL__tr_par__even 0 |
| #define R_SERIAL3_CTRL__tr_par__odd 1 |
| #define R_SERIAL3_CTRL__tr_par_en__BITNR 9 |
| #define R_SERIAL3_CTRL__tr_par_en__WIDTH 1 |
| #define R_SERIAL3_CTRL__tr_par_en__disable 0 |
| #define R_SERIAL3_CTRL__tr_par_en__enable 1 |
| #define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 |
| #define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1 |
| #define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0 |
| #define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1 |
| #define R_SERIAL3_CTRL__data_out__BITNR 0 |
| #define R_SERIAL3_CTRL__data_out__WIDTH 8 |
| |
| #define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b) |
| #define R_SERIAL3_BAUD__tr_baud__BITNR 4 |
| #define R_SERIAL3_BAUD__tr_baud__WIDTH 4 |
| #define R_SERIAL3_BAUD__tr_baud__c300Hz 0 |
| #define R_SERIAL3_BAUD__tr_baud__c600Hz 1 |
| #define R_SERIAL3_BAUD__tr_baud__c1200Hz 2 |
| #define R_SERIAL3_BAUD__tr_baud__c2400Hz 3 |
| #define R_SERIAL3_BAUD__tr_baud__c4800Hz 4 |
| #define R_SERIAL3_BAUD__tr_baud__c9600Hz 5 |
| #define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6 |
| #define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7 |
| #define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8 |
| #define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9 |
| #define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10 |
| #define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11 |
| #define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12 |
| #define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13 |
| #define R_SERIAL3_BAUD__tr_baud__c6250kHz 14 |
| #define R_SERIAL3_BAUD__tr_baud__reserved 15 |
| #define R_SERIAL3_BAUD__rec_baud__BITNR 0 |
| #define R_SERIAL3_BAUD__rec_baud__WIDTH 4 |
| #define R_SERIAL3_BAUD__rec_baud__c300Hz 0 |
| #define R_SERIAL3_BAUD__rec_baud__c600Hz 1 |
| #define R_SERIAL3_BAUD__rec_baud__c1200Hz 2 |
| #define R_SERIAL3_BAUD__rec_baud__c2400Hz 3 |
| #define R_SERIAL3_BAUD__rec_baud__c4800Hz 4 |
| #define R_SERIAL3_BAUD__rec_baud__c9600Hz 5 |
| #define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6 |
| #define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7 |
| #define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8 |
| #define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9 |
| #define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10 |
| #define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11 |
| #define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12 |
| #define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13 |
| #define R_SERIAL3_BAUD__rec_baud__c6250kHz 14 |
| #define R_SERIAL3_BAUD__rec_baud__reserved 15 |
| |
| #define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a) |
| #define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 |
| #define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1 |
| #define R_SERIAL3_REC_CTRL__dma_err__stop 0 |
| #define R_SERIAL3_REC_CTRL__dma_err__ignore 1 |
| #define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 |
| #define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1 |
| #define R_SERIAL3_REC_CTRL__rec_enable__disable 0 |
| #define R_SERIAL3_REC_CTRL__rec_enable__enable 1 |
| #define R_SERIAL3_REC_CTRL__rts___BITNR 5 |
| #define R_SERIAL3_REC_CTRL__rts___WIDTH 1 |
| #define R_SERIAL3_REC_CTRL__rts___active 0 |
| #define R_SERIAL3_REC_CTRL__rts___inactive 1 |
| #define R_SERIAL3_REC_CTRL__sampling__BITNR 4 |
| #define R_SERIAL3_REC_CTRL__sampling__WIDTH 1 |
| #define R_SERIAL3_REC_CTRL__sampling__middle 0 |
| #define R_SERIAL3_REC_CTRL__sampling__majority 1 |
| #define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 |
| #define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1 |
| #define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0 |
| #define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1 |
| #define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 |
| #define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1 |
| #define R_SERIAL3_REC_CTRL__rec_par__even 0 |
| #define R_SERIAL3_REC_CTRL__rec_par__odd 1 |
| #define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 |
| #define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1 |
| #define R_SERIAL3_REC_CTRL__rec_par_en__disable 0 |
| #define R_SERIAL3_REC_CTRL__rec_par_en__enable 1 |
| #define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 |
| #define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1 |
| #define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0 |
| #define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1 |
| |
| #define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079) |
| #define R_SERIAL3_TR_CTRL__txd__BITNR 7 |
| #define R_SERIAL3_TR_CTRL__txd__WIDTH 1 |
| #define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 |
| #define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1 |
| #define R_SERIAL3_TR_CTRL__tr_enable__disable 0 |
| #define R_SERIAL3_TR_CTRL__tr_enable__enable 1 |
| #define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 |
| #define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1 |
| #define R_SERIAL3_TR_CTRL__auto_cts__disabled 0 |
| #define R_SERIAL3_TR_CTRL__auto_cts__active 1 |
| #define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 |
| #define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1 |
| #define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0 |
| #define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1 |
| #define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 |
| #define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1 |
| #define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0 |
| #define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1 |
| #define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 |
| #define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1 |
| #define R_SERIAL3_TR_CTRL__tr_par__even 0 |
| #define R_SERIAL3_TR_CTRL__tr_par__odd 1 |
| #define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 |
| #define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1 |
| #define R_SERIAL3_TR_CTRL__tr_par_en__disable 0 |
| #define R_SERIAL3_TR_CTRL__tr_par_en__enable 1 |
| #define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 |
| #define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1 |
| #define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0 |
| #define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1 |
| |
| #define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078) |
| #define R_SERIAL3_TR_DATA__data_out__BITNR 0 |
| #define R_SERIAL3_TR_DATA__data_out__WIDTH 8 |
| |
| #define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078) |
| #define R_SERIAL3_READ__xoff_detect__BITNR 15 |
| #define R_SERIAL3_READ__xoff_detect__WIDTH 1 |
| #define R_SERIAL3_READ__xoff_detect__no_xoff 0 |
| #define R_SERIAL3_READ__xoff_detect__xoff 1 |
| #define R_SERIAL3_READ__cts___BITNR 14 |
| #define R_SERIAL3_READ__cts___WIDTH 1 |
| #define R_SERIAL3_READ__cts___active 0 |
| #define R_SERIAL3_READ__cts___inactive 1 |
| #define R_SERIAL3_READ__tr_ready__BITNR 13 |
| #define R_SERIAL3_READ__tr_ready__WIDTH 1 |
| #define R_SERIAL3_READ__tr_ready__full 0 |
| #define R_SERIAL3_READ__tr_ready__ready 1 |
| #define R_SERIAL3_READ__rxd__BITNR 12 |
| #define R_SERIAL3_READ__rxd__WIDTH 1 |
| #define R_SERIAL3_READ__overrun__BITNR 11 |
| #define R_SERIAL3_READ__overrun__WIDTH 1 |
| #define R_SERIAL3_READ__overrun__no 0 |
| #define R_SERIAL3_READ__overrun__yes 1 |
| #define R_SERIAL3_READ__par_err__BITNR 10 |
| #define R_SERIAL3_READ__par_err__WIDTH 1 |
| #define R_SERIAL3_READ__par_err__no 0 |
| #define R_SERIAL3_READ__par_err__yes 1 |
| #define R_SERIAL3_READ__framing_err__BITNR 9 |
| #define R_SERIAL3_READ__framing_err__WIDTH 1 |
| #define R_SERIAL3_READ__framing_err__no 0 |
| #define R_SERIAL3_READ__framing_err__yes 1 |
| #define R_SERIAL3_READ__data_avail__BITNR 8 |
| #define R_SERIAL3_READ__data_avail__WIDTH 1 |
| #define R_SERIAL3_READ__data_avail__no 0 |
| #define R_SERIAL3_READ__data_avail__yes 1 |
| #define R_SERIAL3_READ__data_in__BITNR 0 |
| #define R_SERIAL3_READ__data_in__WIDTH 8 |
| |
| #define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079) |
| #define R_SERIAL3_STATUS__xoff_detect__BITNR 7 |
| #define R_SERIAL3_STATUS__xoff_detect__WIDTH 1 |
| #define R_SERIAL3_STATUS__xoff_detect__no_xoff 0 |
| #define R_SERIAL3_STATUS__xoff_detect__xoff 1 |
| #define R_SERIAL3_STATUS__cts___BITNR 6 |
| #define R_SERIAL3_STATUS__cts___WIDTH 1 |
| #define R_SERIAL3_STATUS__cts___active 0 |
| #define R_SERIAL3_STATUS__cts___inactive 1 |
| #define R_SERIAL3_STATUS__tr_ready__BITNR 5 |
| #define R_SERIAL3_STATUS__tr_ready__WIDTH 1 |
| #define R_SERIAL3_STATUS__tr_ready__full 0 |
| #define R_SERIAL3_STATUS__tr_ready__ready 1 |
| #define R_SERIAL3_STATUS__rxd__BITNR 4 |
| #define R_SERIAL3_STATUS__rxd__WIDTH 1 |
| #define R_SERIAL3_STATUS__overrun__BITNR 3 |
| #define R_SERIAL3_STATUS__overrun__WIDTH 1 |
| #define R_SERIAL3_STATUS__overrun__no 0 |
| #define R_SERIAL3_STATUS__overrun__yes 1 |
| #define R_SERIAL3_STATUS__par_err__BITNR 2 |
| #define R_SERIAL3_STATUS__par_err__WIDTH 1 |
| #define R_SERIAL3_STATUS__par_err__no 0 |
| #define R_SERIAL3_STATUS__par_err__yes 1 |
| #define R_SERIAL3_STATUS__framing_err__BITNR 1 |
| #define R_SERIAL3_STATUS__framing_err__WIDTH 1 |
| #define R_SERIAL3_STATUS__framing_err__no 0 |
| #define R_SERIAL3_STATUS__framing_err__yes 1 |
| #define R_SERIAL3_STATUS__data_avail__BITNR 0 |
| #define R_SERIAL3_STATUS__data_avail__WIDTH 1 |
| #define R_SERIAL3_STATUS__data_avail__no 0 |
| #define R_SERIAL3_STATUS__data_avail__yes 1 |
| |
| #define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078) |
| #define R_SERIAL3_REC_DATA__data_in__BITNR 0 |
| #define R_SERIAL3_REC_DATA__data_in__WIDTH 8 |
| |
| #define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c) |
| #define R_SERIAL3_XOFF__tx_stop__BITNR 9 |
| #define R_SERIAL3_XOFF__tx_stop__WIDTH 1 |
| #define R_SERIAL3_XOFF__tx_stop__enable 0 |
| #define R_SERIAL3_XOFF__tx_stop__stop 1 |
| #define R_SERIAL3_XOFF__auto_xoff__BITNR 8 |
| #define R_SERIAL3_XOFF__auto_xoff__WIDTH 1 |
| #define R_SERIAL3_XOFF__auto_xoff__disable 0 |
| #define R_SERIAL3_XOFF__auto_xoff__enable 1 |
| #define R_SERIAL3_XOFF__xoff_char__BITNR 0 |
| #define R_SERIAL3_XOFF__xoff_char__WIDTH 8 |
| |
| #define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c) |
| #define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 |
| #define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2 |
| #define R_ALT_SER_BAUDRATE__ser3_tr__normal 0 |
| #define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1 |
| #define R_ALT_SER_BAUDRATE__ser3_tr__extern 2 |
| #define R_ALT_SER_BAUDRATE__ser3_tr__timer 3 |
| #define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 |
| #define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2 |
| #define R_ALT_SER_BAUDRATE__ser3_rec__normal 0 |
| #define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1 |
| #define R_ALT_SER_BAUDRATE__ser3_rec__extern 2 |
| #define R_ALT_SER_BAUDRATE__ser3_rec__timer 3 |
| #define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 |
| #define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2 |
| #define R_ALT_SER_BAUDRATE__ser2_tr__normal 0 |
| #define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1 |
| #define R_ALT_SER_BAUDRATE__ser2_tr__extern 2 |
| #define R_ALT_SER_BAUDRATE__ser2_tr__timer 3 |
| #define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 |
| #define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2 |
| #define R_ALT_SER_BAUDRATE__ser2_rec__normal 0 |
| #define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1 |
| #define R_ALT_SER_BAUDRATE__ser2_rec__extern 2 |
| #define R_ALT_SER_BAUDRATE__ser2_rec__timer 3 |
| #define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 |
| #define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2 |
| #define R_ALT_SER_BAUDRATE__ser1_tr__normal 0 |
| #define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1 |
| #define R_ALT_SER_BAUDRATE__ser1_tr__extern 2 |
| #define R_ALT_SER_BAUDRATE__ser1_tr__timer 3 |
| #define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 |
| #define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2 |
| #define R_ALT_SER_BAUDRATE__ser1_rec__normal 0 |
| #define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1 |
| #define R_ALT_SER_BAUDRATE__ser1_rec__extern 2 |
| #define R_ALT_SER_BAUDRATE__ser1_rec__timer 3 |
| #define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 |
| #define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2 |
| #define R_ALT_SER_BAUDRATE__ser0_tr__normal 0 |
| #define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1 |
| #define R_ALT_SER_BAUDRATE__ser0_tr__extern 2 |
| #define R_ALT_SER_BAUDRATE__ser0_tr__timer 3 |
| #define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 |
| #define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2 |
| #define R_ALT_SER_BAUDRATE__ser0_rec__normal 0 |
| #define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1 |
| #define R_ALT_SER_BAUDRATE__ser0_rec__extern 2 |
| #define R_ALT_SER_BAUDRATE__ser0_rec__timer 3 |
| |
| /* |
| !* Network interface registers |
| !*/ |
| |
| #define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080) |
| #define R_NETWORK_SA_0__ma0_low__BITNR 0 |
| #define R_NETWORK_SA_0__ma0_low__WIDTH 32 |
| |
| #define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084) |
| #define R_NETWORK_SA_1__ma1_low__BITNR 16 |
| #define R_NETWORK_SA_1__ma1_low__WIDTH 16 |
| #define R_NETWORK_SA_1__ma0_high__BITNR 0 |
| #define R_NETWORK_SA_1__ma0_high__WIDTH 16 |
| |
| #define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088) |
| #define R_NETWORK_SA_2__ma1_high__BITNR 0 |
| #define R_NETWORK_SA_2__ma1_high__WIDTH 32 |
| |
| #define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c) |
| #define R_NETWORK_GA_0__ga_low__BITNR 0 |
| #define R_NETWORK_GA_0__ga_low__WIDTH 32 |
| |
| #define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090) |
| #define R_NETWORK_GA_1__ga_high__BITNR 0 |
| #define R_NETWORK_GA_1__ga_high__WIDTH 32 |
| |
| #define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094) |
| #define R_NETWORK_REC_CONFIG__max_size__BITNR 10 |
| #define R_NETWORK_REC_CONFIG__max_size__WIDTH 1 |
| #define R_NETWORK_REC_CONFIG__max_size__size1518 0 |
| #define R_NETWORK_REC_CONFIG__max_size__size1522 1 |
| #define R_NETWORK_REC_CONFIG__duplex__BITNR 9 |
| #define R_NETWORK_REC_CONFIG__duplex__WIDTH 1 |
| #define R_NETWORK_REC_CONFIG__duplex__full 1 |
| #define R_NETWORK_REC_CONFIG__duplex__half 0 |
| #define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 |
| #define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1 |
| #define R_NETWORK_REC_CONFIG__bad_crc__receive 1 |
| #define R_NETWORK_REC_CONFIG__bad_crc__discard 0 |
| #define R_NETWORK_REC_CONFIG__oversize__BITNR 7 |
| #define R_NETWORK_REC_CONFIG__oversize__WIDTH 1 |
| #define R_NETWORK_REC_CONFIG__oversize__receive 1 |
| #define R_NETWORK_REC_CONFIG__oversize__discard 0 |
| #define R_NETWORK_REC_CONFIG__undersize__BITNR 6 |
| #define R_NETWORK_REC_CONFIG__undersize__WIDTH 1 |
| #define R_NETWORK_REC_CONFIG__undersize__receive 1 |
| #define R_NETWORK_REC_CONFIG__undersize__discard 0 |
| #define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 |
| #define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1 |
| #define R_NETWORK_REC_CONFIG__all_roots__receive 1 |
| #define R_NETWORK_REC_CONFIG__all_roots__discard 0 |
| #define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 |
| #define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1 |
| #define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1 |
| #define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0 |
| #define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 |
| #define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1 |
| #define R_NETWORK_REC_CONFIG__broadcast__receive 1 |
| #define R_NETWORK_REC_CONFIG__broadcast__discard 0 |
| #define R_NETWORK_REC_CONFIG__individual__BITNR 2 |
| #define R_NETWORK_REC_CONFIG__individual__WIDTH 1 |
| #define R_NETWORK_REC_CONFIG__individual__receive 1 |
| #define R_NETWORK_REC_CONFIG__individual__discard 0 |
| #define R_NETWORK_REC_CONFIG__ma1__BITNR 1 |
| #define R_NETWORK_REC_CONFIG__ma1__WIDTH 1 |
| #define R_NETWORK_REC_CONFIG__ma1__enable 1 |
| #define R_NETWORK_REC_CONFIG__ma1__disable 0 |
| #define R_NETWORK_REC_CONFIG__ma0__BITNR 0 |
| #define R_NETWORK_REC_CONFIG__ma0__WIDTH 1 |
| #define R_NETWORK_REC_CONFIG__ma0__enable 1 |
| #define R_NETWORK_REC_CONFIG__ma0__disable 0 |
| |
| #define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098) |
| #define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 |
| #define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1 |
| #define R_NETWORK_GEN_CONFIG__loopback__on 1 |
| #define R_NETWORK_GEN_CONFIG__loopback__off 0 |
| #define R_NETWORK_GEN_CONFIG__frame__BITNR 4 |
| #define R_NETWORK_GEN_CONFIG__frame__WIDTH 1 |
| #define R_NETWORK_GEN_CONFIG__frame__tokenr 1 |
| #define R_NETWORK_GEN_CONFIG__frame__ether 0 |
| #define R_NETWORK_GEN_CONFIG__vg__BITNR 3 |
| #define R_NETWORK_GEN_CONFIG__vg__WIDTH 1 |
| #define R_NETWORK_GEN_CONFIG__vg__on 1 |
| #define R_NETWORK_GEN_CONFIG__vg__off 0 |
| #define R_NETWORK_GEN_CONFIG__phy__BITNR 1 |
| #define R_NETWORK_GEN_CONFIG__phy__WIDTH 2 |
| #define R_NETWORK_GEN_CONFIG__phy__sni 0 |
| #define R_NETWORK_GEN_CONFIG__phy__mii_clk 1 |
| #define R_NETWORK_GEN_CONFIG__phy__mii_err 2 |
| #define R_NETWORK_GEN_CONFIG__phy__mii_req 3 |
| #define R_NETWORK_GEN_CONFIG__enable__BITNR 0 |
| #define R_NETWORK_GEN_CONFIG__enable__WIDTH 1 |
| #define R_NETWORK_GEN_CONFIG__enable__on 1 |
| #define R_NETWORK_GEN_CONFIG__enable__off 0 |
| |
| #define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c) |
| #define R_NETWORK_TR_CTRL__clr_error__BITNR 8 |
| #define R_NETWORK_TR_CTRL__clr_error__WIDTH 1 |
| #define R_NETWORK_TR_CTRL__clr_error__clr 1 |
| #define R_NETWORK_TR_CTRL__clr_error__nop 0 |
| #define R_NETWORK_TR_CTRL__delay__BITNR 5 |
| #define R_NETWORK_TR_CTRL__delay__WIDTH 1 |
| #define R_NETWORK_TR_CTRL__delay__d2us 1 |
| #define R_NETWORK_TR_CTRL__delay__none 0 |
| #define R_NETWORK_TR_CTRL__cancel__BITNR 4 |
| #define R_NETWORK_TR_CTRL__cancel__WIDTH 1 |
| #define R_NETWORK_TR_CTRL__cancel__do 1 |
| #define R_NETWORK_TR_CTRL__cancel__dont 0 |
| #define R_NETWORK_TR_CTRL__cd__BITNR 3 |
| #define R_NETWORK_TR_CTRL__cd__WIDTH 1 |
| #define R_NETWORK_TR_CTRL__cd__enable 0 |
| #define R_NETWORK_TR_CTRL__cd__disable 1 |
| #define R_NETWORK_TR_CTRL__cd__ack_col 0 |
| #define R_NETWORK_TR_CTRL__cd__ack_crs 1 |
| #define R_NETWORK_TR_CTRL__retry__BITNR 2 |
| #define R_NETWORK_TR_CTRL__retry__WIDTH 1 |
| #define R_NETWORK_TR_CTRL__retry__enable 0 |
| #define R_NETWORK_TR_CTRL__retry__disable 1 |
| #define R_NETWORK_TR_CTRL__pad__BITNR 1 |
| #define R_NETWORK_TR_CTRL__pad__WIDTH 1 |
| #define R_NETWORK_TR_CTRL__pad__enable 1 |
| #define R_NETWORK_TR_CTRL__pad__disable 0 |
| #define R_NETWORK_TR_CTRL__crc__BITNR 0 |
| #define R_NETWORK_TR_CTRL__crc__WIDTH 1 |
| #define R_NETWORK_TR_CTRL__crc__enable 0 |
| #define R_NETWORK_TR_CTRL__crc__disable 1 |
| |
| #define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0) |
| #define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 |
| #define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4 |
| #define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 |
| #define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1 |
| #define R_NETWORK_MGM_CTRL__mdck__BITNR 2 |
| #define R_NETWORK_MGM_CTRL__mdck__WIDTH 1 |
| #define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 |
| #define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1 |
| #define R_NETWORK_MGM_CTRL__mdoe__enable 1 |
| #define R_NETWORK_MGM_CTRL__mdoe__disable 0 |
| #define R_NETWORK_MGM_CTRL__mdio__BITNR 0 |
| #define R_NETWORK_MGM_CTRL__mdio__WIDTH 1 |
| |
| #define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0) |
| #define R_NETWORK_STAT__rxd_pins__BITNR 4 |
| #define R_NETWORK_STAT__rxd_pins__WIDTH 4 |
| #define R_NETWORK_STAT__rxer__BITNR 3 |
| #define R_NETWORK_STAT__rxer__WIDTH 1 |
| #define R_NETWORK_STAT__underrun__BITNR 2 |
| #define R_NETWORK_STAT__underrun__WIDTH 1 |
| #define R_NETWORK_STAT__underrun__yes 1 |
| #define R_NETWORK_STAT__underrun__no 0 |
| #define R_NETWORK_STAT__exc_col__BITNR 1 |
| #define R_NETWORK_STAT__exc_col__WIDTH 1 |
| #define R_NETWORK_STAT__exc_col__yes 1 |
| #define R_NETWORK_STAT__exc_col__no 0 |
| #define R_NETWORK_STAT__mdio__BITNR 0 |
| #define R_NETWORK_STAT__mdio__WIDTH 1 |
| |
| #define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4) |
| #define R_REC_COUNTERS__congestion__BITNR 24 |
| #define R_REC_COUNTERS__congestion__WIDTH 8 |
| #define R_REC_COUNTERS__oversize__BITNR 16 |
| #define R_REC_COUNTERS__oversize__WIDTH 8 |
| #define R_REC_COUNTERS__alignment_error__BITNR 8 |
| #define R_REC_COUNTERS__alignment_error__WIDTH 8 |
| #define R_REC_COUNTERS__crc_error__BITNR 0 |
| #define R_REC_COUNTERS__crc_error__WIDTH 8 |
| |
| #define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8) |
| #define R_TR_COUNTERS__deferred__BITNR 24 |
| #define R_TR_COUNTERS__deferred__WIDTH 8 |
| #define R_TR_COUNTERS__late_col__BITNR 16 |
| #define R_TR_COUNTERS__late_col__WIDTH 8 |
| #define R_TR_COUNTERS__multiple_col__BITNR 8 |
| #define R_TR_COUNTERS__multiple_col__WIDTH 8 |
| #define R_TR_COUNTERS__single_col__BITNR 0 |
| #define R_TR_COUNTERS__single_col__WIDTH 8 |
| |
| #define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac) |
| #define R_PHY_COUNTERS__sqe_test_error__BITNR 8 |
| #define R_PHY_COUNTERS__sqe_test_error__WIDTH 8 |
| #define R_PHY_COUNTERS__carrier_loss__BITNR 0 |
| #define R_PHY_COUNTERS__carrier_loss__WIDTH 8 |
| |
| /* |
| !* Parallel printer port registers |
| !*/ |
| |
| #define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) |
| #define R_PAR0_CTRL_DATA__peri_int__BITNR 24 |
| #define R_PAR0_CTRL_DATA__peri_int__WIDTH 1 |
| #define R_PAR0_CTRL_DATA__peri_int__ack 1 |
| #define R_PAR0_CTRL_DATA__peri_int__nop 0 |
| #define R_PAR0_CTRL_DATA__oe__BITNR 20 |
| #define R_PAR0_CTRL_DATA__oe__WIDTH 1 |
| #define R_PAR0_CTRL_DATA__oe__enable 1 |
| #define R_PAR0_CTRL_DATA__oe__disable 0 |
| #define R_PAR0_CTRL_DATA__seli__BITNR 19 |
| #define R_PAR0_CTRL_DATA__seli__WIDTH 1 |
| #define R_PAR0_CTRL_DATA__seli__active 1 |
| #define R_PAR0_CTRL_DATA__seli__inactive 0 |
| #define R_PAR0_CTRL_DATA__autofd__BITNR 18 |
| #define R_PAR0_CTRL_DATA__autofd__WIDTH 1 |
| #define R_PAR0_CTRL_DATA__autofd__active 1 |
| #define R_PAR0_CTRL_DATA__autofd__inactive 0 |
| #define R_PAR0_CTRL_DATA__strb__BITNR 17 |
| #define R_PAR0_CTRL_DATA__strb__WIDTH 1 |
| #define R_PAR0_CTRL_DATA__strb__active 1 |
| #define R_PAR0_CTRL_DATA__strb__inactive 0 |
| #define R_PAR0_CTRL_DATA__init__BITNR 16 |
| #define R_PAR0_CTRL_DATA__init__WIDTH 1 |
| #define R_PAR0_CTRL_DATA__init__active 1 |
| #define R_PAR0_CTRL_DATA__init__inactive 0 |
| #define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 |
| #define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1 |
| #define R_PAR0_CTRL_DATA__ecp_cmd__command 1 |
| #define R_PAR0_CTRL_DATA__ecp_cmd__data 0 |
| #define R_PAR0_CTRL_DATA__data__BITNR 0 |
| #define R_PAR0_CTRL_DATA__data__WIDTH 8 |
| |
| #define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042) |
| #define R_PAR0_CTRL__ctrl__BITNR 0 |
| #define R_PAR0_CTRL__ctrl__WIDTH 5 |
| |
| #define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) |
| #define R_PAR0_STATUS_DATA__mode__BITNR 29 |
| #define R_PAR0_STATUS_DATA__mode__WIDTH 3 |
| #define R_PAR0_STATUS_DATA__mode__manual 0 |
| #define R_PAR0_STATUS_DATA__mode__centronics 1 |
| #define R_PAR0_STATUS_DATA__mode__fastbyte 2 |
| #define R_PAR0_STATUS_DATA__mode__nibble 3 |
| #define R_PAR0_STATUS_DATA__mode__byte 4 |
| #define R_PAR0_STATUS_DATA__mode__ecp_fwd 5 |
| #define R_PAR0_STATUS_DATA__mode__ecp_rev 6 |
| #define R_PAR0_STATUS_DATA__mode__off 7 |
| #define R_PAR0_STATUS_DATA__mode__epp_wr1 5 |
| #define R_PAR0_STATUS_DATA__mode__epp_wr2 6 |
| #define R_PAR0_STATUS_DATA__mode__epp_wr3 7 |
| #define R_PAR0_STATUS_DATA__mode__epp_rd 0 |
| #define R_PAR0_STATUS_DATA__perr__BITNR 28 |
| #define R_PAR0_STATUS_DATA__perr__WIDTH 1 |
| #define R_PAR0_STATUS_DATA__perr__active 1 |
| #define R_PAR0_STATUS_DATA__perr__inactive 0 |
| #define R_PAR0_STATUS_DATA__ack__BITNR 27 |
| #define R_PAR0_STATUS_DATA__ack__WIDTH 1 |
| #define R_PAR0_STATUS_DATA__ack__active 0 |
| #define R_PAR0_STATUS_DATA__ack__inactive 1 |
| #define R_PAR0_STATUS_DATA__busy__BITNR 26 |
| #define R_PAR0_STATUS_DATA__busy__WIDTH 1 |
| #define R_PAR0_STATUS_DATA__busy__active 1 |
| #define R_PAR0_STATUS_DATA__busy__inactive 0 |
| #define R_PAR0_STATUS_DATA__fault__BITNR 25 |
| #define R_PAR0_STATUS_DATA__fault__WIDTH 1 |
| #define R_PAR0_STATUS_DATA__fault__active 0 |
| #define R_PAR0_STATUS_DATA__fault__inactive 1 |
| #define R_PAR0_STATUS_DATA__sel__BITNR 24 |
| #define R_PAR0_STATUS_DATA__sel__WIDTH 1 |
| #define R_PAR0_STATUS_DATA__sel__active 1 |
| #define R_PAR0_STATUS_DATA__sel__inactive 0 |
| #define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 |
| #define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1 |
| #define R_PAR0_STATUS_DATA__ext_mode__enable 1 |
| #define R_PAR0_STATUS_DATA__ext_mode__disable 0 |
| #define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 |
| #define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1 |
| #define R_PAR0_STATUS_DATA__ecp_16__active 1 |
| #define R_PAR0_STATUS_DATA__ecp_16__inactive 0 |
| #define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 |
| #define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1 |
| #define R_PAR0_STATUS_DATA__tr_rdy__ready 1 |
| #define R_PAR0_STATUS_DATA__tr_rdy__busy 0 |
| #define R_PAR0_STATUS_DATA__dav__BITNR 16 |
| #define R_PAR0_STATUS_DATA__dav__WIDTH 1 |
| #define R_PAR0_STATUS_DATA__dav__data 1 |
| #define R_PAR0_STATUS_DATA__dav__nodata 0 |
| #define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 |
| #define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1 |
| #define R_PAR0_STATUS_DATA__ecp_cmd__command 1 |
| #define R_PAR0_STATUS_DATA__ecp_cmd__data 0 |
| #define R_PAR0_STATUS_DATA__data__BITNR 0 |
| #define R_PAR0_STATUS_DATA__data__WIDTH 8 |
| |
| #define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042) |
| #define R_PAR0_STATUS__mode__BITNR 13 |
| #define R_PAR0_STATUS__mode__WIDTH 3 |
| #define R_PAR0_STATUS__mode__manual 0 |
| #define R_PAR0_STATUS__mode__centronics 1 |
| #define R_PAR0_STATUS__mode__fastbyte 2 |
| #define R_PAR0_STATUS__mode__nibble 3 |
| #define R_PAR0_STATUS__mode__byte 4 |
| #define R_PAR0_STATUS__mode__ecp_fwd 5 |
| #define R_PAR0_STATUS__mode__ecp_rev 6 |
| #define R_PAR0_STATUS__mode__off 7 |
| #define R_PAR0_STATUS__mode__epp_wr1 5 |
| #define R_PAR0_STATUS__mode__epp_wr2 6 |
| #define R_PAR0_STATUS__mode__epp_wr3 7 |
| #define R_PAR0_STATUS__mode__epp_rd 0 |
| #define R_PAR0_STATUS__perr__BITNR 12 |
| #define R_PAR0_STATUS__perr__WIDTH 1 |
| #define R_PAR0_STATUS__perr__active 1 |
| #define R_PAR0_STATUS__perr__inactive 0 |
| #define R_PAR0_STATUS__ack__BITNR 11 |
| #define R_PAR0_STATUS__ack__WIDTH 1 |
| #define R_PAR0_STATUS__ack__active 0 |
| #define R_PAR0_STATUS__ack__inactive 1 |
| #define R_PAR0_STATUS__busy__BITNR 10 |
| #define R_PAR0_STATUS__busy__WIDTH 1 |
| #define R_PAR0_STATUS__busy__active 1 |
| #define R_PAR0_STATUS__busy__inactive 0 |
| #define R_PAR0_STATUS__fault__BITNR 9 |
| #define R_PAR0_STATUS__fault__WIDTH 1 |
| #define R_PAR0_STATUS__fault__active 0 |
| #define R_PAR0_STATUS__fault__inactive 1 |
| #define R_PAR0_STATUS__sel__BITNR 8 |
| #define R_PAR0_STATUS__sel__WIDTH 1 |
| #define R_PAR0_STATUS__sel__active 1 |
| #define R_PAR0_STATUS__sel__inactive 0 |
| #define R_PAR0_STATUS__ext_mode__BITNR 7 |
| #define R_PAR0_STATUS__ext_mode__WIDTH 1 |
| #define R_PAR0_STATUS__ext_mode__enable 1 |
| #define R_PAR0_STATUS__ext_mode__disable 0 |
| #define R_PAR0_STATUS__ecp_16__BITNR 6 |
| #define R_PAR0_STATUS__ecp_16__WIDTH 1 |
| #define R_PAR0_STATUS__ecp_16__active 1 |
| #define R_PAR0_STATUS__ecp_16__inactive 0 |
| #define R_PAR0_STATUS__tr_rdy__BITNR 1 |
| #define R_PAR0_STATUS__tr_rdy__WIDTH 1 |
| #define R_PAR0_STATUS__tr_rdy__ready 1 |
| #define R_PAR0_STATUS__tr_rdy__busy 0 |
| #define R_PAR0_STATUS__dav__BITNR 0 |
| #define R_PAR0_STATUS__dav__WIDTH 1 |
| #define R_PAR0_STATUS__dav__data 1 |
| #define R_PAR0_STATUS__dav__nodata 0 |
| |
| #define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040) |
| #define R_PAR_ECP16_DATA__data__BITNR 0 |
| #define R_PAR_ECP16_DATA__data__WIDTH 16 |
| |
| #define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) |
| #define R_PAR0_CONFIG__ioe__BITNR 25 |
| #define R_PAR0_CONFIG__ioe__WIDTH 1 |
| #define R_PAR0_CONFIG__ioe__inv 1 |
| #define R_PAR0_CONFIG__ioe__noninv 0 |
| #define R_PAR0_CONFIG__iseli__BITNR 24 |
| #define R_PAR0_CONFIG__iseli__WIDTH 1 |
| #define R_PAR0_CONFIG__iseli__inv 1 |
| #define R_PAR0_CONFIG__iseli__noninv 0 |
| #define R_PAR0_CONFIG__iautofd__BITNR 23 |
| #define R_PAR0_CONFIG__iautofd__WIDTH 1 |
| #define R_PAR0_CONFIG__iautofd__inv 1 |
| #define R_PAR0_CONFIG__iautofd__noninv 0 |
| #define R_PAR0_CONFIG__istrb__BITNR 22 |
| #define R_PAR0_CONFIG__istrb__WIDTH 1 |
| #define R_PAR0_CONFIG__istrb__inv 1 |
| #define R_PAR0_CONFIG__istrb__noninv 0 |
| #define R_PAR0_CONFIG__iinit__BITNR 21 |
| #define R_PAR0_CONFIG__iinit__WIDTH 1 |
| #define R_PAR0_CONFIG__iinit__inv 1 |
| #define R_PAR0_CONFIG__iinit__noninv 0 |
| #define R_PAR0_CONFIG__iperr__BITNR 20 |
| #define R_PAR0_CONFIG__iperr__WIDTH 1 |
| #define R_PAR0_CONFIG__iperr__inv 1 |
| #define R_PAR0_CONFIG__iperr__noninv 0 |
| #define R_PAR0_CONFIG__iack__BITNR 19 |
| #define R_PAR0_CONFIG__iack__WIDTH 1 |
| #define R_PAR0_CONFIG__iack__inv 1 |
| #define R_PAR0_CONFIG__iack__noninv 0 |
| #define R_PAR0_CONFIG__ibusy__BITNR 18 |
| #define R_PAR0_CONFIG__ibusy__WIDTH 1 |
| #define R_PAR0_CONFIG__ibusy__inv 1 |
| #define R_PAR0_CONFIG__ibusy__noninv 0 |
| #define R_PAR0_CONFIG__ifault__BITNR 17 |
| #define R_PAR0_CONFIG__ifault__WIDTH 1 |
| #define R_PAR0_CONFIG__ifault__inv 1 |
| #define R_PAR0_CONFIG__ifault__noninv 0 |
| #define R_PAR0_CONFIG__isel__BITNR 16 |
| #define R_PAR0_CONFIG__isel__WIDTH 1 |
| #define R_PAR0_CONFIG__isel__inv 1 |
| #define R_PAR0_CONFIG__isel__noninv 0 |
| #define R_PAR0_CONFIG__ext_mode__BITNR 11 |
| #define R_PAR0_CONFIG__ext_mode__WIDTH 1 |
| #define R_PAR0_CONFIG__ext_mode__enable 1 |
| #define R_PAR0_CONFIG__ext_mode__disable 0 |
| #define R_PAR0_CONFIG__wide__BITNR 10 |
| #define R_PAR0_CONFIG__wide__WIDTH 1 |
| #define R_PAR0_CONFIG__wide__enable 1 |
| #define R_PAR0_CONFIG__wide__disable 0 |
| #define R_PAR0_CONFIG__dma__BITNR 9 |
| #define R_PAR0_CONFIG__dma__WIDTH 1 |
| #define R_PAR0_CONFIG__dma__enable 1 |
| #define R_PAR0_CONFIG__dma__disable 0 |
| #define R_PAR0_CONFIG__rle_in__BITNR 8 |
| #define R_PAR0_CONFIG__rle_in__WIDTH 1 |
| #define R_PAR0_CONFIG__rle_in__enable 1 |
| #define R_PAR0_CONFIG__rle_in__disable 0 |
| #define R_PAR0_CONFIG__rle_out__BITNR 7 |
| #define R_PAR0_CONFIG__rle_out__WIDTH 1 |
| #define R_PAR0_CONFIG__rle_out__enable 1 |
| #define R_PAR0_CONFIG__rle_out__disable 0 |
| #define R_PAR0_CONFIG__enable__BITNR 6 |
| #define R_PAR0_CONFIG__enable__WIDTH 1 |
| #define R_PAR0_CONFIG__enable__on 1 |
| #define R_PAR0_CONFIG__enable__reset 0 |
| #define R_PAR0_CONFIG__force__BITNR 5 |
| #define R_PAR0_CONFIG__force__WIDTH 1 |
| #define R_PAR0_CONFIG__force__on 1 |
| #define R_PAR0_CONFIG__force__off 0 |
| #define R_PAR0_CONFIG__ign_ack__BITNR 4 |
| #define R_PAR0_CONFIG__ign_ack__WIDTH 1 |
| #define R_PAR0_CONFIG__ign_ack__ignore 1 |
| #define R_PAR0_CONFIG__ign_ack__wait 0 |
| #define R_PAR0_CONFIG__oe_ack__BITNR 3 |
| #define R_PAR0_CONFIG__oe_ack__WIDTH 1 |
| #define R_PAR0_CONFIG__oe_ack__wait_oe 1 |
| #define R_PAR0_CONFIG__oe_ack__dont_wait 0 |
| #define R_PAR0_CONFIG__oe_ack__epp_addr 1 |
| #define R_PAR0_CONFIG__oe_ack__epp_data 0 |
| #define R_PAR0_CONFIG__epp_addr_data__BITNR 3 |
| #define R_PAR0_CONFIG__epp_addr_data__WIDTH 1 |
| #define R_PAR0_CONFIG__epp_addr_data__wait_oe 1 |
| #define R_PAR0_CONFIG__epp_addr_data__dont_wait 0 |
| #define R_PAR0_CONFIG__epp_addr_data__epp_addr 1 |
| #define R_PAR0_CONFIG__epp_addr_data__epp_data 0 |
| #define R_PAR0_CONFIG__mode__BITNR 0 |
| #define R_PAR0_CONFIG__mode__WIDTH 3 |
| #define R_PAR0_CONFIG__mode__manual 0 |
| #define R_PAR0_CONFIG__mode__centronics 1 |
| #define R_PAR0_CONFIG__mode__fastbyte 2 |
| #define R_PAR0_CONFIG__mode__nibble 3 |
| #define R_PAR0_CONFIG__mode__byte 4 |
| #define R_PAR0_CONFIG__mode__ecp_fwd 5 |
| #define R_PAR0_CONFIG__mode__ecp_rev 6 |
| #define R_PAR0_CONFIG__mode__off 7 |
| #define R_PAR0_CONFIG__mode__epp_wr1 5 |
| #define R_PAR0_CONFIG__mode__epp_wr2 6 |
| #define R_PAR0_CONFIG__mode__epp_wr3 7 |
| #define R_PAR0_CONFIG__mode__epp_rd 0 |
| |
| #define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048) |
| #define R_PAR0_DELAY__fine_hold__BITNR 21 |
| #define R_PAR0_DELAY__fine_hold__WIDTH 3 |
| #define R_PAR0_DELAY__hold__BITNR 16 |
| #define R_PAR0_DELAY__hold__WIDTH 5 |
| #define R_PAR0_DELAY__fine_strb__BITNR 13 |
| #define R_PAR0_DELAY__fine_strb__WIDTH 3 |
| #define R_PAR0_DELAY__strobe__BITNR 8 |
| #define R_PAR0_DELAY__strobe__WIDTH 5 |
| #define R_PAR0_DELAY__fine_setup__BITNR 5 |
| #define R_PAR0_DELAY__fine_setup__WIDTH 3 |
| #define R_PAR0_DELAY__setup__BITNR 0 |
| #define R_PAR0_DELAY__setup__WIDTH 5 |
| |
| #define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050) |
| #define R_PAR1_CTRL_DATA__peri_int__BITNR 24 |
| #define R_PAR1_CTRL_DATA__peri_int__WIDTH 1 |
| #define R_PAR1_CTRL_DATA__peri_int__ack 1 |
| #define R_PAR1_CTRL_DATA__peri_int__nop 0 |
| #define R_PAR1_CTRL_DATA__oe__BITNR 20 |
| #define R_PAR1_CTRL_DATA__oe__WIDTH 1 |
| #define R_PAR1_CTRL_DATA__oe__enable 1 |
| #define R_PAR1_CTRL_DATA__oe__disable 0 |
| #define R_PAR1_CTRL_DATA__seli__BITNR 19 |
| #define R_PAR1_CTRL_DATA__seli__WIDTH 1 |
| #define R_PAR1_CTRL_DATA__seli__active 1 |
| #define R_PAR1_CTRL_DATA__seli__inactive 0 |
| #define R_PAR1_CTRL_DATA__autofd__BITNR 18 |
| #define R_PAR1_CTRL_DATA__autofd__WIDTH 1 |
| #define R_PAR1_CTRL_DATA__autofd__active 1 |
| #define R_PAR1_CTRL_DATA__autofd__inactive 0 |
| #define R_PAR1_CTRL_DATA__strb__BITNR 17 |
| #define R_PAR1_CTRL_DATA__strb__WIDTH 1 |
| #define R_PAR1_CTRL_DATA__strb__active 1 |
| #define R_PAR1_CTRL_DATA__strb__inactive 0 |
| #define R_PAR1_CTRL_DATA__init__BITNR 16 |
| #define R_PAR1_CTRL_DATA__init__WIDTH 1 |
| #define R_PAR1_CTRL_DATA__init__active 1 |
| #define R_PAR1_CTRL_DATA__init__inactive 0 |
| #define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 |
| #define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1 |
| #define R_PAR1_CTRL_DATA__ecp_cmd__command 1 |
| #define R_PAR1_CTRL_DATA__ecp_cmd__data 0 |
| #define R_PAR1_CTRL_DATA__data__BITNR 0 |
| #define R_PAR1_CTRL_DATA__data__WIDTH 8 |
| |
| #define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052) |
| #define R_PAR1_CTRL__ctrl__BITNR 0 |
| #define R_PAR1_CTRL__ctrl__WIDTH 5 |
| |
| #define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050) |
| #define R_PAR1_STATUS_DATA__mode__BITNR 29 |
| #define R_PAR1_STATUS_DATA__mode__WIDTH 3 |
| #define R_PAR1_STATUS_DATA__mode__manual 0 |
| #define R_PAR1_STATUS_DATA__mode__centronics 1 |
| #define R_PAR1_STATUS_DATA__mode__fastbyte 2 |
| #define R_PAR1_STATUS_DATA__mode__nibble 3 |
| #define R_PAR1_STATUS_DATA__mode__byte 4 |
| #define R_PAR1_STATUS_DATA__mode__ecp_fwd 5 |
| #define R_PAR1_STATUS_DATA__mode__ecp_rev 6 |
| #define R_PAR1_STATUS_DATA__mode__off 7 |
| #define R_PAR1_STATUS_DATA__mode__epp_wr1 5 |
| #define R_PAR1_STATUS_DATA__mode__epp_wr2 6 |
| #define R_PAR1_STATUS_DATA__mode__epp_wr3 7 |
| #define R_PAR1_STATUS_DATA__mode__epp_rd 0 |
| #define R_PAR1_STATUS_DATA__perr__BITNR 28 |
| #define R_PAR1_STATUS_DATA__perr__WIDTH 1 |
| #define R_PAR1_STATUS_DATA__perr__active 1 |
| #define R_PAR1_STATUS_DATA__perr__inactive 0 |
| #define R_PAR1_STATUS_DATA__ack__BITNR 27 |
| #define R_PAR1_STATUS_DATA__ack__WIDTH 1 |
| #define R_PAR1_STATUS_DATA__ack__active 0 |
| #define R_PAR1_STATUS_DATA__ack__inactive 1 |
| #define R_PAR1_STATUS_DATA__busy__BITNR 26 |
| #define R_PAR1_STATUS_DATA__busy__WIDTH 1 |
| #define R_PAR1_STATUS_DATA__busy__active 1 |
| #define R_PAR1_STATUS_DATA__busy__inactive 0 |
| #define R_PAR1_STATUS_DATA__fault__BITNR 25 |
| #define R_PAR1_STATUS_DATA__fault__WIDTH 1 |
| #define R_PAR1_STATUS_DATA__fault__active 0 |
| #define R_PAR1_STATUS_DATA__fault__inactive 1 |
| #define R_PAR1_STATUS_DATA__sel__BITNR 24 |
| #define R_PAR1_STATUS_DATA__sel__WIDTH 1 |
| #define R_PAR1_STATUS_DATA__sel__active 1 |
| #define R_PAR1_STATUS_DATA__sel__inactive 0 |
| #define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 |
| #define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1 |
| #define R_PAR1_STATUS_DATA__ext_mode__enable 1 |
| #define R_PAR1_STATUS_DATA__ext_mode__disable 0 |
| #define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 |
| #define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1 |
| #define R_PAR1_STATUS_DATA__tr_rdy__ready 1 |
| #define R_PAR1_STATUS_DATA__tr_rdy__busy 0 |
| #define R_PAR1_STATUS_DATA__dav__BITNR 16 |
| #define R_PAR1_STATUS_DATA__dav__WIDTH 1 |
| #define R_PAR1_STATUS_DATA__dav__data 1 |
| #define R_PAR1_STATUS_DATA__dav__nodata 0 |
| #define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 |
| #define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1 |
| #define R_PAR1_STATUS_DATA__ecp_cmd__command 1 |
| #define R_PAR1_STATUS_DATA__ecp_cmd__data 0 |
| #define R_PAR1_STATUS_DATA__data__BITNR 0 |
| #define R_PAR1_STATUS_DATA__data__WIDTH 8 |
| |
| #define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052) |
| #define R_PAR1_STATUS__mode__BITNR 13 |
| #define R_PAR1_STATUS__mode__WIDTH 3 |
| #define R_PAR1_STATUS__mode__manual 0 |
| #define R_PAR1_STATUS__mode__centronics 1 |
| #define R_PAR1_STATUS__mode__fastbyte 2 |
| #define R_PAR1_STATUS__mode__nibble 3 |
| #define R_PAR1_STATUS__mode__byte 4 |
| #define R_PAR1_STATUS__mode__ecp_fwd 5 |
| #define R_PAR1_STATUS__mode__ecp_rev 6 |
| #define R_PAR1_STATUS__mode__off 7 |
| #define R_PAR1_STATUS__mode__epp_wr1 5 |
| #define R_PAR1_STATUS__mode__epp_wr2 6 |
| #define R_PAR1_STATUS__mode__epp_wr3 7 |
| #define R_PAR1_STATUS__mode__epp_rd 0 |
| #define R_PAR1_STATUS__perr__BITNR 12 |
| #define R_PAR1_STATUS__perr__WIDTH 1 |
| #define R_PAR1_STATUS__perr__active 1 |
| #define R_PAR1_STATUS__perr__inactive 0 |
| #define R_PAR1_STATUS__ack__BITNR 11 |
| #define R_PAR1_STATUS__ack__WIDTH 1 |
| #define R_PAR1_STATUS__ack__active 0 |
| #define R_PAR1_STATUS__ack__inactive 1 |
| #define R_PAR1_STATUS__busy__BITNR 10 |
| #define R_PAR1_STATUS__busy__WIDTH 1 |
| #define R_PAR1_STATUS__busy__active 1 |
| #define R_PAR1_STATUS__busy__inactive 0 |
| #define R_PAR1_STATUS__fault__BITNR 9 |
| #define R_PAR1_STATUS__fault__WIDTH 1 |
| #define R_PAR1_STATUS__fault__active 0 |
| #define R_PAR1_STATUS__fault__inactive 1 |
| #define R_PAR1_STATUS__sel__BITNR 8 |
| #define R_PAR1_STATUS__sel__WIDTH 1 |
| #define R_PAR1_STATUS__sel__active 1 |
| #define R_PAR1_STATUS__sel__inactive 0 |
| #define R_PAR1_STATUS__ext_mode__BITNR 7 |
| #define R_PAR1_STATUS__ext_mode__WIDTH 1 |
| #define R_PAR1_STATUS__ext_mode__enable 1 |
| #define R_PAR1_STATUS__ext_mode__disable 0 |
| #define R_PAR1_STATUS__tr_rdy__BITNR 1 |
| #define R_PAR1_STATUS__tr_rdy__WIDTH 1 |
| #define R_PAR1_STATUS__tr_rdy__ready 1 |
| #define R_PAR1_STATUS__tr_rdy__busy 0 |
| #define R_PAR1_STATUS__dav__BITNR 0 |
| #define R_PAR1_STATUS__dav__WIDTH 1 |
| #define R_PAR1_STATUS__dav__data 1 |
| #define R_PAR1_STATUS__dav__nodata 0 |
| |
| #define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054) |
| #define R_PAR1_CONFIG__ioe__BITNR 25 |
| #define R_PAR1_CONFIG__ioe__WIDTH 1 |
| #define R_PAR1_CONFIG__ioe__inv 1 |
| #define R_PAR1_CONFIG__ioe__noninv 0 |
| #define R_PAR1_CONFIG__iseli__BITNR 24 |
| #define R_PAR1_CONFIG__iseli__WIDTH 1 |
| #define R_PAR1_CONFIG__iseli__inv 1 |
| #define R_PAR1_CONFIG__iseli__noninv 0 |
| #define R_PAR1_CONFIG__iautofd__BITNR 23 |
| #define R_PAR1_CONFIG__iautofd__WIDTH 1 |
| #define R_PAR1_CONFIG__iautofd__inv 1 |
| #define R_PAR1_CONFIG__iautofd__noninv 0 |
| #define R_PAR1_CONFIG__istrb__BITNR 22 |
| #define R_PAR1_CONFIG__istrb__WIDTH 1 |
| #define R_PAR1_CONFIG__istrb__inv 1 |
| #define R_PAR1_CONFIG__istrb__noninv 0 |
| #define R_PAR1_CONFIG__iinit__BITNR 21 |
| #define R_PAR1_CONFIG__iinit__WIDTH 1 |
| #define R_PAR1_CONFIG__iinit__inv 1 |
| #define R_PAR1_CONFIG__iinit__noninv 0 |
| #define R_PAR1_CONFIG__iperr__BITNR 20 |
| #define R_PAR1_CONFIG__iperr__WIDTH 1 |
| #define R_PAR1_CONFIG__iperr__inv 1 |
| #define R_PAR1_CONFIG__iperr__noninv 0 |
| #define R_PAR1_CONFIG__iack__BITNR 19 |
| #define R_PAR1_CONFIG__iack__WIDTH 1 |
| #define R_PAR1_CONFIG__iack__inv 1 |
| #define R_PAR1_CONFIG__iack__noninv 0 |
| #define R_PAR1_CONFIG__ibusy__BITNR 18 |
| #define R_PAR1_CONFIG__ibusy__WIDTH 1 |
| #define R_PAR1_CONFIG__ibusy__inv 1 |
| #define R_PAR1_CONFIG__ibusy__noninv 0 |
| #define R_PAR1_CONFIG__ifault__BITNR 17 |
| #define R_PAR1_CONFIG__ifault__WIDTH 1 |
| #define R_PAR1_CONFIG__ifault__inv 1 |
| #define R_PAR1_CONFIG__ifault__noninv 0 |
| #define R_PAR1_CONFIG__isel__BITNR 16 |
| #define R_PAR1_CONFIG__isel__WIDTH 1 |
| #define R_PAR1_CONFIG__isel__inv 1 |
| #define R_PAR1_CONFIG__isel__noninv 0 |
| #define R_PAR1_CONFIG__ext_mode__BITNR 11 |
| #define R_PAR1_CONFIG__ext_mode__WIDTH 1 |
| #define R_PAR1_CONFIG__ext_mode__enable 1 |
| #define R_PAR1_CONFIG__ext_mode__disable 0 |
| #define R_PAR1_CONFIG__dma__BITNR 9 |
| #define R_PAR1_CONFIG__dma__WIDTH 1 |
| #define R_PAR1_CONFIG__dma__enable 1 |
| #define R_PAR1_CONFIG__dma__disable 0 |
| #define R_PAR1_CONFIG__rle_in__BITNR 8 |
| #define R_PAR1_CONFIG__rle_in__WIDTH 1 |
| #define R_PAR1_CONFIG__rle_in__enable 1 |
| #define R_PAR1_CONFIG__rle_in__disable 0 |
| #define R_PAR1_CONFIG__rle_out__BITNR 7 |
| #define R_PAR1_CONFIG__rle_out__WIDTH 1 |
| #define R_PAR1_CONFIG__rle_out__enable 1 |
| #define R_PAR1_CONFIG__rle_out__disable 0 |
| #define R_PAR1_CONFIG__enable__BITNR 6 |
| #define R_PAR1_CONFIG__enable__WIDTH 1 |
| #define R_PAR1_CONFIG__enable__on 1 |
| #define R_PAR1_CONFIG__enable__reset 0 |
| #define R_PAR1_CONFIG__force__BITNR 5 |
| #define R_PAR1_CONFIG__force__WIDTH 1 |
| #define R_PAR1_CONFIG__force__on 1 |
| #define R_PAR1_CONFIG__force__off 0 |
| #define R_PAR1_CONFIG__ign_ack__BITNR 4 |
| #define R_PAR1_CONFIG__ign_ack__WIDTH 1 |
| #define R_PAR1_CONFIG__ign_ack__ignore 1 |
| #define R_PAR1_CONFIG__ign_ack__wait 0 |
| #define R_PAR1_CONFIG__oe_ack__BITNR 3 |
| #define R_PAR1_CONFIG__oe_ack__WIDTH 1 |
| #define R_PAR1_CONFIG__oe_ack__wait_oe 1 |
| #define R_PAR1_CONFIG__oe_ack__dont_wait 0 |
| #define R_PAR1_CONFIG__oe_ack__epp_addr 1 |
| #define R_PAR1_CONFIG__oe_ack__epp_data 0 |
| #define R_PAR1_CONFIG__epp_addr_data__BITNR 3 |
| #define R_PAR1_CONFIG__epp_addr_data__WIDTH 1 |
| #define R_PAR1_CONFIG__epp_addr_data__wait_oe 1 |
| #define R_PAR1_CONFIG__epp_addr_data__dont_wait 0 |
| #define R_PAR1_CONFIG__epp_addr_data__epp_addr 1 |
| #define R_PAR1_CONFIG__epp_addr_data__epp_data 0 |
| #define R_PAR1_CONFIG__mode__BITNR 0 |
| #define R_PAR1_CONFIG__mode__WIDTH 3 |
| #define R_PAR1_CONFIG__mode__manual 0 |
| #define R_PAR1_CONFIG__mode__centronics 1 |
| #define R_PAR1_CONFIG__mode__fastbyte 2 |
| #define R_PAR1_CONFIG__mode__nibble 3 |
| #define R_PAR1_CONFIG__mode__byte 4 |
| #define R_PAR1_CONFIG__mode__ecp_fwd 5 |
| #define R_PAR1_CONFIG__mode__ecp_rev 6 |
| #define R_PAR1_CONFIG__mode__off 7 |
| #define R_PAR1_CONFIG__mode__epp_wr1 5 |
| #define R_PAR1_CONFIG__mode__epp_wr2 6 |
| #define R_PAR1_CONFIG__mode__epp_wr3 7 |
| #define R_PAR1_CONFIG__mode__epp_rd 0 |
| |
| #define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058) |
| #define R_PAR1_DELAY__fine_hold__BITNR 21 |
| #define R_PAR1_DELAY__fine_hold__WIDTH 3 |
| #define R_PAR1_DELAY__hold__BITNR 16 |
| #define R_PAR1_DELAY__hold__WIDTH 5 |
| #define R_PAR1_DELAY__fine_strb__BITNR 13 |
| #define R_PAR1_DELAY__fine_strb__WIDTH 3 |
| #define R_PAR1_DELAY__strobe__BITNR 8 |
| #define R_PAR1_DELAY__strobe__WIDTH 5 |
| #define R_PAR1_DELAY__fine_setup__BITNR 5 |
| #define R_PAR1_DELAY__fine_setup__WIDTH 3 |
| #define R_PAR1_DELAY__setup__BITNR 0 |
| #define R_PAR1_DELAY__setup__WIDTH 5 |
| |
| /* |
| !* ATA interface registers |
| !*/ |
| |
| #define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) |
| #define R_ATA_CTRL_DATA__sel__BITNR 30 |
| #define R_ATA_CTRL_DATA__sel__WIDTH 2 |
| #define R_ATA_CTRL_DATA__cs1__BITNR 29 |
| #define R_ATA_CTRL_DATA__cs1__WIDTH 1 |
| #define R_ATA_CTRL_DATA__cs1__active 1 |
| #define R_ATA_CTRL_DATA__cs1__inactive 0 |
| #define R_ATA_CTRL_DATA__cs0__BITNR 28 |
| #define R_ATA_CTRL_DATA__cs0__WIDTH 1 |
| #define R_ATA_CTRL_DATA__cs0__active 1 |
| #define R_ATA_CTRL_DATA__cs0__inactive 0 |
| #define R_ATA_CTRL_DATA__addr__BITNR 25 |
| #define R_ATA_CTRL_DATA__addr__WIDTH 3 |
| #define R_ATA_CTRL_DATA__rw__BITNR 24 |
| #define R_ATA_CTRL_DATA__rw__WIDTH 1 |
| #define R_ATA_CTRL_DATA__rw__read 1 |
| #define R_ATA_CTRL_DATA__rw__write 0 |
| #define R_ATA_CTRL_DATA__src_dst__BITNR 23 |
| #define R_ATA_CTRL_DATA__src_dst__WIDTH 1 |
| #define R_ATA_CTRL_DATA__src_dst__dma 1 |
| #define R_ATA_CTRL_DATA__src_dst__register 0 |
| #define R_ATA_CTRL_DATA__handsh__BITNR 22 |
| #define R_ATA_CTRL_DATA__handsh__WIDTH 1 |
| #define R_ATA_CTRL_DATA__handsh__dma 1 |
| #define R_ATA_CTRL_DATA__handsh__pio 0 |
| #define R_ATA_CTRL_DATA__multi__BITNR 21 |
| #define R_ATA_CTRL_DATA__multi__WIDTH 1 |
| #define R_ATA_CTRL_DATA__multi__on 1 |
| #define R_ATA_CTRL_DATA__multi__off 0 |
| #define R_ATA_CTRL_DATA__dma_size__BITNR 20 |
| #define R_ATA_CTRL_DATA__dma_size__WIDTH 1 |
| #define R_ATA_CTRL_DATA__dma_size__byte 1 |
| #define R_ATA_CTRL_DATA__dma_size__word 0 |
| #define R_ATA_CTRL_DATA__data__BITNR 0 |
| #define R_ATA_CTRL_DATA__data__WIDTH 16 |
| |
| #define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) |
| #define R_ATA_STATUS_DATA__busy__BITNR 18 |
| #define R_ATA_STATUS_DATA__busy__WIDTH 1 |
| #define R_ATA_STATUS_DATA__busy__yes 1 |
| #define R_ATA_STATUS_DATA__busy__no 0 |
| #define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 |
| #define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1 |
| #define R_ATA_STATUS_DATA__tr_rdy__ready 1 |
| #define R_ATA_STATUS_DATA__tr_rdy__busy 0 |
| #define R_ATA_STATUS_DATA__dav__BITNR 16 |
| #define R_ATA_STATUS_DATA__dav__WIDTH 1 |
| #define R_ATA_STATUS_DATA__dav__data 1 |
| #define R_ATA_STATUS_DATA__dav__nodata 0 |
| #define R_ATA_STATUS_DATA__data__BITNR 0 |
| #define R_ATA_STATUS_DATA__data__WIDTH 16 |
| |
| #define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) |
| #define R_ATA_CONFIG__enable__BITNR 25 |
| #define R_ATA_CONFIG__enable__WIDTH 1 |
| #define R_ATA_CONFIG__enable__on 1 |
| #define R_ATA_CONFIG__enable__off 0 |
| #define R_ATA_CONFIG__dma_strobe__BITNR 20 |
| #define R_ATA_CONFIG__dma_strobe__WIDTH 5 |
| #define R_ATA_CONFIG__dma_hold__BITNR 15 |
| #define R_ATA_CONFIG__dma_hold__WIDTH 5 |
| #define R_ATA_CONFIG__pio_setup__BITNR 10 |
| #define R_ATA_CONFIG__pio_setup__WIDTH 5 |
| #define R_ATA_CONFIG__pio_strobe__BITNR 5 |
| #define R_ATA_CONFIG__pio_strobe__WIDTH 5 |
| #define R_ATA_CONFIG__pio_hold__BITNR 0 |
| #define R_ATA_CONFIG__pio_hold__WIDTH 5 |
| |
| #define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048) |
| #define R_ATA_TRANSFER_CNT__count__BITNR 0 |
| #define R_ATA_TRANSFER_CNT__count__WIDTH 17 |
| |
| /* |
| !* SCSI registers |
| !*/ |
| |
| #define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044) |
| #define R_SCSI0_CTRL__id_type__BITNR 31 |
| #define R_SCSI0_CTRL__id_type__WIDTH 1 |
| #define R_SCSI0_CTRL__id_type__software 1 |
| #define R_SCSI0_CTRL__id_type__hardware 0 |
| #define R_SCSI0_CTRL__sel_timeout__BITNR 24 |
| #define R_SCSI0_CTRL__sel_timeout__WIDTH 7 |
| #define R_SCSI0_CTRL__synch_per__BITNR 16 |
| #define R_SCSI0_CTRL__synch_per__WIDTH 8 |
| #define R_SCSI0_CTRL__rst__BITNR 15 |
| #define R_SCSI0_CTRL__rst__WIDTH 1 |
| #define R_SCSI0_CTRL__rst__yes 1 |
| #define R_SCSI0_CTRL__rst__no 0 |
| #define R_SCSI0_CTRL__atn__BITNR 14 |
| #define R_SCSI0_CTRL__atn__WIDTH 1 |
| #define R_SCSI0_CTRL__atn__yes 1 |
| #define R_SCSI0_CTRL__atn__no 0 |
| #define R_SCSI0_CTRL__my_id__BITNR 9 |
| #define R_SCSI0_CTRL__my_id__WIDTH 4 |
| #define R_SCSI0_CTRL__target_id__BITNR 4 |
| #define R_SCSI0_CTRL__target_id__WIDTH 4 |
| #define R_SCSI0_CTRL__fast_20__BITNR 3 |
| #define R_SCSI0_CTRL__fast_20__WIDTH 1 |
| #define R_SCSI0_CTRL__fast_20__yes 1 |
| #define R_SCSI0_CTRL__fast_20__no 0 |
| #define R_SCSI0_CTRL__bus_width__BITNR 2 |
| #define R_SCSI0_CTRL__bus_width__WIDTH 1 |
| #define R_SCSI0_CTRL__bus_width__wide 1 |
| #define R_SCSI0_CTRL__bus_width__narrow 0 |
| #define R_SCSI0_CTRL__synch__BITNR 1 |
| #define R_SCSI0_CTRL__synch__WIDTH 1 |
| #define R_SCSI0_CTRL__synch__synch 1 |
| #define R_SCSI0_CTRL__synch__asynch 0 |
| #define R_SCSI0_CTRL__enable__BITNR 0 |
| #define R_SCSI0_CTRL__enable__WIDTH 1 |
| #define R_SCSI0_CTRL__enable__on 1 |
| #define R_SCSI0_CTRL__enable__off 0 |
| |
| #define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040) |
| #define R_SCSI0_CMD_DATA__parity_in__BITNR 26 |
| #define R_SCSI0_CMD_DATA__parity_in__WIDTH 1 |
| #define R_SCSI0_CMD_DATA__parity_in__on 0 |
| #define R_SCSI0_CMD_DATA__parity_in__off 1 |
| #define R_SCSI0_CMD_DATA__skip__BITNR 25 |
| #define R_SCSI0_CMD_DATA__skip__WIDTH 1 |
| #define R_SCSI0_CMD_DATA__skip__on 1 |
| #define R_SCSI0_CMD_DATA__skip__off 0 |
| #define R_SCSI0_CMD_DATA__clr_status__BITNR 24 |
| #define R_SCSI0_CMD_DATA__clr_status__WIDTH 1 |
| #define R_SCSI0_CMD_DATA__clr_status__yes 1 |
| #define R_SCSI0_CMD_DATA__clr_status__nop 0 |
| #define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 |
| #define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4 |
| #define R_SCSI0_CMD_DATA__command__BITNR 16 |
| #define R_SCSI0_CMD_DATA__command__WIDTH 4 |
| #define R_SCSI0_CMD_DATA__command__full_din_1 0 |
| #define R_SCSI0_CMD_DATA__command__full_dout_1 1 |
| #define R_SCSI0_CMD_DATA__command__full_stat_1 2 |
| #define R_SCSI0_CMD_DATA__command__resel_din 3 |
| #define R_SCSI0_CMD_DATA__command__resel_dout 4 |
| #define R_SCSI0_CMD_DATA__command__resel_stat 5 |
| #define R_SCSI0_CMD_DATA__command__arb_only 6 |
| #define R_SCSI0_CMD_DATA__command__full_din_3 8 |
| #define R_SCSI0_CMD_DATA__command__full_dout_3 9 |
| #define R_SCSI0_CMD_DATA__command__full_stat_3 10 |
| #define R_SCSI0_CMD_DATA__command__man_data_in 11 |
| #define R_SCSI0_CMD_DATA__command__man_data_out 12 |
| #define R_SCSI0_CMD_DATA__command__man_rat 13 |
| #define R_SCSI0_CMD_DATA__data_out__BITNR 0 |
| #define R_SCSI0_CMD_DATA__data_out__WIDTH 16 |
| |
| #define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040) |
| #define R_SCSI0_DATA__data_out__BITNR 0 |
| #define R_SCSI0_DATA__data_out__WIDTH 16 |
| |
| #define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042) |
| #define R_SCSI0_CMD__asynch_setup__BITNR 4 |
| #define R_SCSI0_CMD__asynch_setup__WIDTH 4 |
| #define R_SCSI0_CMD__command__BITNR 0 |
| #define R_SCSI0_CMD__command__WIDTH 4 |
| #define R_SCSI0_CMD__command__full_din_1 0 |
| #define R_SCSI0_CMD__command__full_dout_1 1 |
| #define R_SCSI0_CMD__command__full_stat_1 2 |
| #define R_SCSI0_CMD__command__resel_din 3 |
| #define R_SCSI0_CMD__command__resel_dout 4 |
| #define R_SCSI0_CMD__command__resel_stat 5 |
| #define R_SCSI0_CMD__command__arb_only 6 |
| #define R_SCSI0_CMD__command__full_din_3 8 |
| #define R_SCSI0_CMD__command__full_dout_3 9 |
| #define R_SCSI0_CMD__command__full_stat_3 10 |
| #define R_SCSI0_CMD__command__man_data_in 11 |
| #define R_SCSI0_CMD__command__man_data_out 12 |
| #define R_SCSI0_CMD__command__man_rat 13 |
| |
| #define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043) |
| #define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 |
| #define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1 |
| #define R_SCSI0_STATUS_CTRL__parity_in__on 0 |
| #define R_SCSI0_STATUS_CTRL__parity_in__off 1 |
| #define R_SCSI0_STATUS_CTRL__skip__BITNR 1 |
| #define R_SCSI0_STATUS_CTRL__skip__WIDTH 1 |
| #define R_SCSI0_STATUS_CTRL__skip__on 1 |
| #define R_SCSI0_STATUS_CTRL__skip__off 0 |
| #define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 |
| #define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1 |
| #define R_SCSI0_STATUS_CTRL__clr_status__yes 1 |
| #define R_SCSI0_STATUS_CTRL__clr_status__nop 0 |
| |
| #define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048) |
| #define R_SCSI0_STATUS__tst_arb_won__BITNR 23 |
| #define R_SCSI0_STATUS__tst_arb_won__WIDTH 1 |
| #define R_SCSI0_STATUS__tst_resel__BITNR 22 |
| #define R_SCSI0_STATUS__tst_resel__WIDTH 1 |
| #define R_SCSI0_STATUS__parity_error__BITNR 21 |
| #define R_SCSI0_STATUS__parity_error__WIDTH 1 |
| #define R_SCSI0_STATUS__bus_reset__BITNR 20 |
| #define R_SCSI0_STATUS__bus_reset__WIDTH 1 |
| #define R_SCSI0_STATUS__bus_reset__yes 1 |
| #define R_SCSI0_STATUS__bus_reset__no 0 |
| #define R_SCSI0_STATUS__resel_target__BITNR 15 |
| #define R_SCSI0_STATUS__resel_target__WIDTH 4 |
| #define R_SCSI0_STATUS__resel__BITNR 14 |
| #define R_SCSI0_STATUS__resel__WIDTH 1 |
| #define R_SCSI0_STATUS__resel__yes 1 |
| #define R_SCSI0_STATUS__resel__no 0 |
| #define R_SCSI0_STATUS__curr_phase__BITNR 11 |
| #define R_SCSI0_STATUS__curr_phase__WIDTH 3 |
| #define R_SCSI0_STATUS__curr_phase__ph_undef 0 |
| #define R_SCSI0_STATUS__curr_phase__ph_msg_in 7 |
| #define R_SCSI0_STATUS__curr_phase__ph_msg_out 6 |
| #define R_SCSI0_STATUS__curr_phase__ph_status 3 |
| #define R_SCSI0_STATUS__curr_phase__ph_command 2 |
| #define R_SCSI0_STATUS__curr_phase__ph_data_in 5 |
| #define R_SCSI0_STATUS__curr_phase__ph_data_out 4 |
| #define R_SCSI0_STATUS__curr_phase__ph_resel 1 |
| #define R_SCSI0_STATUS__last_seq_step__BITNR 6 |
| #define R_SCSI0_STATUS__last_seq_step__WIDTH 5 |
| #define R_SCSI0_STATUS__last_seq_step__st_bus_free 24 |
| #define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8 |
| #define R_SCSI0_STATUS__last_seq_step__st_resel_req 29 |
| #define R_SCSI0_STATUS__last_seq_step__st_msg_1 2 |
| #define R_SCSI0_STATUS__last_seq_step__st_manual 28 |
| #define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30 |
| #define R_SCSI0_STATUS__last_seq_step__st_msg_2 6 |
| #define R_SCSI0_STATUS__last_seq_step__st_msg_3 22 |
| #define R_SCSI0_STATUS__last_seq_step__st_answer 3 |
| #define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1 |
| #define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15 |
| #define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0 |
| #define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25 |
| #define R_SCSI0_STATUS__last_seq_step__st_synch_din 13 |
| #define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9 |
| #define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4 |
| #define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12 |
| #define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5 |
| #define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11 |
| #define R_SCSI0_STATUS__last_seq_step__st_iwr 27 |
| #define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21 |
| #define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7 |
| #define R_SCSI0_STATUS__last_seq_step__st_cc 31 |
| #define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14 |
| #define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23 |
| #define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17 |
| #define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20 |
| #define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16 |
| #define R_SCSI0_STATUS__last_seq_step__st_manual_req 10 |
| #define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18 |
| #define R_SCSI0_STATUS__valid_status__BITNR 5 |
| #define R_SCSI0_STATUS__valid_status__WIDTH 1 |
| #define R_SCSI0_STATUS__valid_status__yes 1 |
| #define R_SCSI0_STATUS__valid_status__no 0 |
| #define R_SCSI0_STATUS__seq_status__BITNR 0 |
| #define R_SCSI0_STATUS__seq_status__WIDTH 5 |
| #define R_SCSI0_STATUS__seq_status__info_seq_complete 0 |
| #define R_SCSI0_STATUS__seq_status__info_parity_error 1 |
| #define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2 |
| #define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3 |
| #define R_SCSI0_STATUS__seq_status__info_arb_lost 4 |
| #define R_SCSI0_STATUS__seq_status__info_sel_timeout 5 |
| #define R_SCSI0_STATUS__seq_status__info_unexp_bf 6 |
| #define R_SCSI0_STATUS__seq_status__info_illegal_op 7 |
| #define R_SCSI0_STATUS__seq_status__info_rec_recvd 8 |
| #define R_SCSI0_STATUS__seq_status__info_reselected 9 |
| #define R_SCSI0_STATUS__seq_status__info_unhandled_status 10 |
| #define R_SCSI0_STATUS__seq_status__info_bus_reset 11 |
| #define R_SCSI0_STATUS__seq_status__info_illegal_bf 12 |
| #define R_SCSI0_STATUS__seq_status__info_bus_free 13 |
| |
| #define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040) |
| #define R_SCSI0_DATA_IN__data_in__BITNR 0 |
| #define R_SCSI0_DATA_IN__data_in__WIDTH 16 |
| |
| #define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054) |
| #define R_SCSI1_CTRL__id_type__BITNR 31 |
| #define R_SCSI1_CTRL__id_type__WIDTH 1 |
| #define R_SCSI1_CTRL__id_type__software 1 |
| #define R_SCSI1_CTRL__id_type__hardware 0 |
| #define R_SCSI1_CTRL__sel_timeout__BITNR 24 |
| #define R_SCSI1_CTRL__sel_timeout__WIDTH 7 |
| #define R_SCSI1_CTRL__synch_per__BITNR 16 |
| #define R_SCSI1_CTRL__synch_per__WIDTH 8 |
| #define R_SCSI1_CTRL__rst__BITNR 15 |
| #define R_SCSI1_CTRL__rst__WIDTH 1 |
| #define R_SCSI1_CTRL__rst__yes 1 |
| #define R_SCSI1_CTRL__rst__no 0 |
| #define R_SCSI1_CTRL__atn__BITNR 14 |
| #define R_SCSI1_CTRL__atn__WIDTH 1 |
| #define R_SCSI1_CTRL__atn__yes 1 |
| #define R_SCSI1_CTRL__atn__no 0 |
| #define R_SCSI1_CTRL__my_id__BITNR 9 |
| #define R_SCSI1_CTRL__my_id__WIDTH 4 |
| #define R_SCSI1_CTRL__target_id__BITNR 4 |
| #define R_SCSI1_CTRL__target_id__WIDTH 4 |
| #define R_SCSI1_CTRL__fast_20__BITNR 3 |
| #define R_SCSI1_CTRL__fast_20__WIDTH 1 |
| #define R_SCSI1_CTRL__fast_20__yes 1 |
| #define R_SCSI1_CTRL__fast_20__no 0 |
| #define R_SCSI1_CTRL__bus_width__BITNR 2 |
| #define R_SCSI1_CTRL__bus_width__WIDTH 1 |
| #define R_SCSI1_CTRL__bus_width__wide 1 |
| #define R_SCSI1_CTRL__bus_width__narrow 0 |
| #define R_SCSI1_CTRL__synch__BITNR 1 |
| #define R_SCSI1_CTRL__synch__WIDTH 1 |
| #define R_SCSI1_CTRL__synch__synch 1 |
| #define R_SCSI1_CTRL__synch__asynch 0 |
| #define R_SCSI1_CTRL__enable__BITNR 0 |
| #define R_SCSI1_CTRL__enable__WIDTH 1 |
| #define R_SCSI1_CTRL__enable__on 1 |
| #define R_SCSI1_CTRL__enable__off 0 |
| |
| #define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050) |
| #define R_SCSI1_CMD_DATA__parity_in__BITNR 26 |
| #define R_SCSI1_CMD_DATA__parity_in__WIDTH 1 |
| #define R_SCSI1_CMD_DATA__parity_in__on 0 |
| #define R_SCSI1_CMD_DATA__parity_in__off 1 |
| #define R_SCSI1_CMD_DATA__skip__BITNR 25 |
| #define R_SCSI1_CMD_DATA__skip__WIDTH 1 |
| #define R_SCSI1_CMD_DATA__skip__on 1 |
| #define R_SCSI1_CMD_DATA__skip__off 0 |
| #define R_SCSI1_CMD_DATA__clr_status__BITNR 24 |
| #define R_SCSI1_CMD_DATA__clr_status__WIDTH 1 |
| #define R_SCSI1_CMD_DATA__clr_status__yes 1 |
| #define R_SCSI1_CMD_DATA__clr_status__nop 0 |
| #define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 |
| #define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4 |
| #define R_SCSI1_CMD_DATA__command__BITNR 16 |
| #define R_SCSI1_CMD_DATA__command__WIDTH 4 |
| #define R_SCSI1_CMD_DATA__command__full_din_1 0 |
| #define R_SCSI1_CMD_DATA__command__full_dout_1 1 |
| #define R_SCSI1_CMD_DATA__command__full_stat_1 2 |
| #define R_SCSI1_CMD_DATA__command__resel_din 3 |
| #define R_SCSI1_CMD_DATA__command__resel_dout 4 |
| #define R_SCSI1_CMD_DATA__command__resel_stat 5 |
| #define R_SCSI1_CMD_DATA__command__arb_only 6 |
| #define R_SCSI1_CMD_DATA__command__full_din_3 8 |
| #define R_SCSI1_CMD_DATA__command__full_dout_3 9 |
| #define R_SCSI1_CMD_DATA__command__full_stat_3 10 |
| #define R_SCSI1_CMD_DATA__command__man_data_in 11 |
| #define R_SCSI1_CMD_DATA__command__man_data_out 12 |
| #define R_SCSI1_CMD_DATA__command__man_rat 13 |
| #define R_SCSI1_CMD_DATA__data_out__BITNR 0 |
| #define R_SCSI1_CMD_DATA__data_out__WIDTH 16 |
| |
| #define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050) |
| #define R_SCSI1_DATA__data_out__BITNR 0 |
| #define R_SCSI1_DATA__data_out__WIDTH 16 |
| |
| #define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052) |
| #define R_SCSI1_CMD__asynch_setup__BITNR 4 |
| #define R_SCSI1_CMD__asynch_setup__WIDTH 4 |
| #define R_SCSI1_CMD__command__BITNR 0 |
| #define R_SCSI1_CMD__command__WIDTH 4 |
| #define R_SCSI1_CMD__command__full_din_1 0 |
| #define R_SCSI1_CMD__command__full_dout_1 1 |
| #define R_SCSI1_CMD__command__full_stat_1 2 |
| #define R_SCSI1_CMD__command__resel_din 3 |
| #define R_SCSI1_CMD__command__resel_dout 4 |
| #define R_SCSI1_CMD__command__resel_stat 5 |
| #define R_SCSI1_CMD__command__arb_only 6 |
| #define R_SCSI1_CMD__command__full_din_3 8 |
| #define R_SCSI1_CMD__command__full_dout_3 9 |
| #define R_SCSI1_CMD__command__full_stat_3 10 |
| #define R_SCSI1_CMD__command__man_data_in 11 |
| #define R_SCSI1_CMD__command__man_data_out 12 |
| #define R_SCSI1_CMD__command__man_rat 13 |
| |
| #define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053) |
| #define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 |
| #define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1 |
| #define R_SCSI1_STATUS_CTRL__parity_in__on 0 |
| #define R_SCSI1_STATUS_CTRL__parity_in__off 1 |
| #define R_SCSI1_STATUS_CTRL__skip__BITNR 1 |
| #define R_SCSI1_STATUS_CTRL__skip__WIDTH 1 |
| #define R_SCSI1_STATUS_CTRL__skip__on 1 |
| #define R_SCSI1_STATUS_CTRL__skip__off 0 |
| #define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 |
| #define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1 |
| #define R_SCSI1_STATUS_CTRL__clr_status__yes 1 |
| #define R_SCSI1_STATUS_CTRL__clr_status__nop 0 |
| |
| #define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058) |
| #define R_SCSI1_STATUS__tst_arb_won__BITNR 23 |
| #define R_SCSI1_STATUS__tst_arb_won__WIDTH 1 |
| #define R_SCSI1_STATUS__tst_resel__BITNR 22 |
| #define R_SCSI1_STATUS__tst_resel__WIDTH 1 |
| #define R_SCSI1_STATUS__parity_error__BITNR 21 |
| #define R_SCSI1_STATUS__parity_error__WIDTH 1 |
| #define R_SCSI1_STATUS__bus_reset__BITNR 20 |
| #define R_SCSI1_STATUS__bus_reset__WIDTH 1 |
| #define R_SCSI1_STATUS__bus_reset__yes 1 |
| #define R_SCSI1_STATUS__bus_reset__no 0 |
| #define R_SCSI1_STATUS__resel_target__BITNR 15 |
| #define R_SCSI1_STATUS__resel_target__WIDTH 4 |
| #define R_SCSI1_STATUS__resel__BITNR 14 |
| #define R_SCSI1_STATUS__resel__WIDTH 1 |
| #define R_SCSI1_STATUS__resel__yes 1 |
| #define R_SCSI1_STATUS__resel__no 0 |
| #define R_SCSI1_STATUS__curr_phase__BITNR 11 |
| #define R_SCSI1_STATUS__curr_phase__WIDTH 3 |
| #define R_SCSI1_STATUS__curr_phase__ph_undef 0 |
| #define R_SCSI1_STATUS__curr_phase__ph_msg_in 7 |
| #define R_SCSI1_STATUS__curr_phase__ph_msg_out 6 |
| #define R_SCSI1_STATUS__curr_phase__ph_status 3 |
| #define R_SCSI1_STATUS__curr_phase__ph_command 2 |
| #define R_SCSI1_STATUS__curr_phase__ph_data_in 5 |
| #define R_SCSI1_STATUS__curr_phase__ph_data_out 4 |
| #define R_SCSI1_STATUS__curr_phase__ph_resel 1 |
| #define R_SCSI1_STATUS__last_seq_step__BITNR 6 |
| #define R_SCSI1_STATUS__last_seq_step__WIDTH 5 |
| #define R_SCSI1_STATUS__last_seq_step__st_bus_free 24 |
| #define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8 |
| #define R_SCSI1_STATUS__last_seq_step__st_resel_req 29 |
| #define R_SCSI1_STATUS__last_seq_step__st_msg_1 2 |
| #define R_SCSI1_STATUS__last_seq_step__st_manual 28 |
| #define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30 |
| #define R_SCSI1_STATUS__last_seq_step__st_msg_2 6 |
| #define R_SCSI1_STATUS__last_seq_step__st_msg_3 22 |
| #define R_SCSI1_STATUS__last_seq_step__st_answer 3 |
| #define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1 |
| #define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15 |
| #define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0 |
| #define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25 |
| #define R_SCSI1_STATUS__last_seq_step__st_synch_din 13 |
| #define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9 |
| #define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4 |
| #define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12 |
| #define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5 |
| #define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11 |
| #define R_SCSI1_STATUS__last_seq_step__st_iwr 27 |
| #define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21 |
| #define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7 |
| #define R_SCSI1_STATUS__last_seq_step__st_cc 31 |
| #define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14 |
| #define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23 |
| #define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17 |
| #define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20 |
| #define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16 |
| #define R_SCSI1_STATUS__last_seq_step__st_manual_req 10 |
| #define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18 |
| #define R_SCSI1_STATUS__valid_status__BITNR 5 |
| #define R_SCSI1_STATUS__valid_status__WIDTH 1 |
| #define R_SCSI1_STATUS__valid_status__yes 1 |
| #define R_SCSI1_STATUS__valid_status__no 0 |
| #define R_SCSI1_STATUS__seq_status__BITNR 0 |
| #define R_SCSI1_STATUS__seq_status__WIDTH 5 |
| #define R_SCSI1_STATUS__seq_status__info_seq_complete 0 |
| #define R_SCSI1_STATUS__seq_status__info_parity_error 1 |
| #define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2 |
| #define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3 |
| #define |
