tree d52c9828d47a2948952dec9e12463e02f121efd4
parent 2d6608b57c50c54c3e46649110e8ea5a40959c30
author Andrew Jeffery <andrew@aj.id.au> 1624844165 +0930
committer Joel Stanley <joel@jms.id.au> 1625112432 +0930

ARM: dts: everest: Add phase corrections for eMMC

The values were determined experimentally via boot tests, not by
measuring the bus behaviour with a scope. We plan to do scope
measurements to confirm or refine the values and will update the
devicetree if necessary once these have been obtained.

However, with the patch we can write and read data without issue, where
as booting the system without the patch failed at the point of mounting
the rootfs.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20210628013605.1257346-1-andrew@aj.id.au
Fixes: 2fc88f92359d ("mmc: sdhci-of-aspeed: Expose clock phase controls")
Fixes: a5c5168478d7 ("ARM: dts: aspeed: Add Everest BMC machine")
Signed-off-by: Joel Stanley <joel@jms.id.au>