tree 1baebbcd4ea1e406cf93580ae323397f8accc089
parent c949c30b2640e52b580e1a230e3561d1662195ba
parent 0db7f5cd4aeba4cc63d0068598b3350eba8bb4cd
author Linus Torvalds <torvalds@linux-foundation.org> 1561799061 +0800
committer Linus Torvalds <torvalds@linux-foundation.org> 1561799061 +0800
mergetag object 0db7f5cd4aeba4cc63d0068598b3350eba8bb4cd
 type commit
 tag riscv-for-v5.2/fixes-rc7
 tagger Paul Walmsley <paul.walmsley@sifive.com> 1561761312 -0700
 
 Minor RISC-V fixes and one defconfig update for the v5.2-rc series.
 
 The fixes have no functional impact:
 
 - Fix some comment text in the memory management vmalloc_fault path.
 
 - Fix some warnings from the DT compiler in our newly-added DT files.
 
 - Change the newly-added DT bindings such that SoC IP blocks with
   external I/O are marked as "disabled" by default, then enable them
   explicitly in board DT files when the devices are used on the board.
   This aligns the bindings with existing upstream practice.
 
 - Add the MIT license as an option for a minor header file, at the
   request of one of the U-Boot maintainers.
 
 The RISC-V defconfig update builds the SiFive SPI driver and the
 MMC-SPI driver by default.  The intention here is to make v5.2 more
 usable for testers and users with RISC-V hardware.
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Merge tag 'riscv-for-v5.2/fixes-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Paul Walmsley:
 "Minor RISC-V fixes and one defconfig update.

  The fixes have no functional impact:

   - Fix some comment text in the memory management vmalloc_fault path.

   - Fix some warnings from the DT compiler in our newly-added DT files.

   - Change the newly-added DT bindings such that SoC IP blocks with
     external I/O are marked as "disabled" by default, then enable them
     explicitly in board DT files when the devices are used on the
     board. This aligns the bindings with existing upstream practice.

   - Add the MIT license as an option for a minor header file, at the
     request of one of the U-Boot maintainers.

  The RISC-V defconfig update builds the SiFive SPI driver and the
  MMC-SPI driver by default. The intention here is to make v5.2 more
  usable for testers and users with RISC-V hardware"

* tag 'riscv-for-v5.2/fixes-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: mm: Fix code comment
  dt-bindings: clock: sifive: add MIT license as an option for the header file
  dt-bindings: riscv: resolve 'make dt_binding_check' warnings
  riscv: dts: Re-organize the DT nodes
  RISC-V: defconfig: enable MMC & SPI for RISC-V