blob: 312bef6bd583ce92d1382cfb8bbefbb0ba834f32 [file] [log] [blame]
/* $Id: serial.c,v 1.25 2004/09/29 10:33:49 starvik Exp $
*
* Serial port driver for the ETRAX 100LX chip
*
* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Axis Communications AB
*
* Many, many authors. Based once upon a time on serial.c for 16x50.
*
* $Log: serial.c,v $
* Revision 1.25 2004/09/29 10:33:49 starvik
* Resolved a dealock when printing debug from kernel.
*
* Revision 1.24 2004/08/27 23:25:59 johana
* rs_set_termios() must call change_speed() if c_iflag has changed or
* automatic XOFF handling will be enabled and transmitter will stop
* if 0x13 is received.
*
* Revision 1.23 2004/08/24 06:57:13 starvik
* More whitespace cleanup
*
* Revision 1.22 2004/08/24 06:12:20 starvik
* Whitespace cleanup
*
* Revision 1.20 2004/05/24 12:00:20 starvik
* Big merge of stuff from Linux 2.4 (e.g. manual mode for the serial port).
*
* Revision 1.19 2004/05/17 13:12:15 starvik
* Kernel console hook
* Big merge from Linux 2.4 still pending.
*
* Revision 1.18 2003/10/28 07:18:30 starvik
* Compiles with debug info
*
* Revision 1.17 2003/07/04 08:27:37 starvik
* Merge of Linux 2.5.74
*
* Revision 1.16 2003/06/13 10:05:19 johana
* Help the user to avoid trouble by:
* Forcing mixed mode for status/control lines if not all pins are used.
*
* Revision 1.15 2003/06/13 09:43:01 johana
* Merged in the following changes from os/linux/arch/cris/drivers/serial.c
* + some minor changes to reduce diff.
*
* Revision 1.49 2003/05/30 11:31:54 johana
* Merged in change-branch--serial9bit that adds CMSPAR support for sticky
* parity (mark/space)
*
* Revision 1.48 2003/05/30 11:03:57 johana
* Implemented rs_send_xchar() by disabling the DMA and writing manually.
* Added e100_disable_txdma_channel() and e100_enable_txdma_channel().
* Fixed rs_throttle() and rs_unthrottle() to properly call rs_send_xchar
* instead of setting info->x_char and check the CRTSCTS flag before
* controlling the rts pin.
*
* Revision 1.14 2003/04/09 08:12:44 pkj
* Corrected typo changes made upstream.
*
* Revision 1.13 2003/04/09 05:20:47 starvik
* Merge of Linux 2.5.67
*
* Revision 1.11 2003/01/22 06:48:37 starvik
* Fixed warnings issued by GCC 3.2.1
*
* Revision 1.9 2002/12/13 09:07:47 starvik
* Alert user that RX_TIMEOUT_TICKS==0 doesn't work
*
* Revision 1.8 2002/12/11 13:13:57 starvik
* Added arch/ to v10 specific includes
* Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
*
* Revision 1.7 2002/12/06 07:13:57 starvik
* Corrected work queue stuff
* Removed CONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST
*
* Revision 1.6 2002/11/21 07:17:46 starvik
* Change static inline to extern inline where otherwise outlined with gcc-3.2
*
* Revision 1.5 2002/11/14 15:59:49 starvik
* Linux 2.5 port of the latest serial driver from 2.4. The work queue stuff
* probably doesn't work yet.
*
* Revision 1.42 2002/11/05 09:08:47 johana
* Better implementation of rs_stop() and rs_start() that uses the XOFF
* register to start/stop transmission.
* change_speed() also initilises XOFF register correctly so that
* auto_xoff is enabled when IXON flag is set by user.
* This gives fast XOFF response times.
*
* Revision 1.41 2002/11/04 18:40:57 johana
* Implemented rs_stop() and rs_start().
* Simple tests using hwtestserial indicates that this should be enough
* to make it work.
*
* Revision 1.40 2002/10/14 05:33:18 starvik
* RS-485 uses fast timers even if SERIAL_FAST_TIMER is disabled
*
* Revision 1.39 2002/09/30 21:00:57 johana
* Support for CONFIG_ETRAX_SERx_DTR_RI_DSR_CD_MIXED where the status and
* control pins can be mixed between PA and PB.
* If no serial port uses MIXED old solution is used
* (saves a few bytes and cycles).
* control_pins struct uses masks instead of bit numbers.
* Corrected dummy values and polarity in line_info() so
* /proc/tty/driver/serial is now correct.
* (the E100_xxx_GET() macros is really active low - perhaps not obvious)
*
* Revision 1.38 2002/08/23 11:01:36 starvik
* Check that serial port is enabled in all interrupt handlers to avoid
* restarts of DMA channels not assigned to serial ports
*
* Revision 1.37 2002/08/13 13:02:37 bjornw
* Removed some warnings because of unused code
*
* Revision 1.36 2002/08/08 12:50:01 starvik
* Serial interrupt is shared with synchronous serial port driver
*
* Revision 1.35 2002/06/03 10:40:49 starvik
* Increased RS-485 RTS toggle timer to 2 characters
*
* Revision 1.34 2002/05/28 18:59:36 johana
* Whitespace and comment fixing to be more like etrax100ser.c 1.71.
*
* Revision 1.33 2002/05/28 17:55:43 johana
* RS-485 uses FAST_TIMER if enabled, and starts a short (one char time)
* timer from tranismit_chars (interrupt context).
* The timer toggles RTS in interrupt context when expired giving minimum
* latencies.
*
* Revision 1.32 2002/05/22 13:58:00 johana
* Renamed rs_write() to raw_write() and made it inline.
* New rs_write() handles RS-485 if configured and enabled
* (moved code from e100_write_rs485()).
* RS-485 ioctl's uses copy_from_user() instead of verify_area().
*
* Revision 1.31 2002/04/22 11:20:03 johana
* Updated copyright years.
*
* Revision 1.30 2002/04/22 09:39:12 johana
* RS-485 support compiles.
*
* Revision 1.29 2002/01/14 16:10:01 pkj
* Allocate the receive buffers dynamically. The static 4kB buffer was
* too small for the peaks. This means that we can get rid of the extra
* buffer and the copying to it. It also means we require less memory
* under normal operations, but can use more when needed (there is a
* cap at 64kB for safety reasons). If there is no memory available
* we panic(), and die a horrible death...
*
* Revision 1.28 2001/12/18 15:04:53 johana
* Cleaned up write_rs485() - now it works correctly without padding extra
* char.
* Added sane default initialisation of rs485.
* Added #ifdef around dummy variables.
*
* Revision 1.27 2001/11/29 17:00:41 pkj
* 2kB seems to be too small a buffer when using 921600 bps,
* so increase it to 4kB (this was already done for the elinux
* version of the serial driver).
*
* Revision 1.26 2001/11/19 14:20:41 pkj
* Minor changes to comments and unused code.
*
* Revision 1.25 2001/11/12 20:03:43 pkj
* Fixed compiler warnings.
*
* Revision 1.24 2001/11/12 15:10:05 pkj
* Total redesign of the receiving part of the serial driver.
* Uses eight chained descriptors to write to a 4kB buffer.
* This data is then serialised into a 2kB buffer. From there it
* is copied into the TTY's flip buffers when they become available.
* A lot of copying, and the sizes of the buffers might need to be
* tweaked, but all in all it should work better than the previous
* version, without the need to modify the TTY code in any way.
* Also note that erroneous bytes are now correctly marked in the
* flag buffers (instead of always marking the first byte).
*
* Revision 1.23 2001/10/30 17:53:26 pkj
* * Set info->uses_dma to 0 when a port is closed.
* * Mark the timer1 interrupt as a fast one (SA_INTERRUPT).
* * Call start_flush_timer() in start_receive() if
* CONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST is defined.
*
* Revision 1.22 2001/10/30 17:44:03 pkj
* Use %lu for received and transmitted counters in line_info().
*
* Revision 1.21 2001/10/30 17:40:34 pkj
* Clean-up. The only change to functionality is that
* CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS(=5) is used instead of
* MAX_FLUSH_TIME(=8).
*
* Revision 1.20 2001/10/30 15:24:49 johana
* Added char_time stuff from 2.0 driver.
*
* Revision 1.19 2001/10/30 15:23:03 johana
* Merged with 1.13.2 branch + fixed indentation
* and changed CONFIG_ETRAX100_XYS to CONFIG_ETRAX_XYZ
*
* Revision 1.18 2001/09/24 09:27:22 pkj
* Completed ext_baud_table[] in cflag_to_baud() and cflag_to_etrax_baud().
*
* Revision 1.17 2001/08/24 11:32:49 ronny
* More fixes for the CONFIG_ETRAX_SERIAL_PORT0 define.
*
* Revision 1.16 2001/08/24 07:56:22 ronny
* Added config ifdefs around ser0 irq requests.
*
* Revision 1.15 2001/08/16 09:10:31 bjarne
* serial.c - corrected the initialization of rs_table, the wrong defines
* where used.
* Corrected a test in timed_flush_handler.
* Changed configured to enabled.
* serial.h - Changed configured to enabled.
*
* Revision 1.14 2001/08/15 07:31:23 bjarne
* Introduced two new members to the e100_serial struct.
* configured - Will be set to 1 if the port has been configured in .config
* uses_dma - Should be set to 1 if the port uses DMA. Currently it is set
* to 1
* when a port is opened. This is used to limit the DMA interrupt
* routines to only manipulate DMA channels actually used by the
* serial driver.
*
* Revision 1.13.2.2 2001/10/17 13:57:13 starvik
* Receiver was broken by the break fixes
*
* Revision 1.13.2.1 2001/07/20 13:57:39 ronny
* Merge with new stuff from etrax100ser.c. Works but haven't checked stuff
* like break handling.
*
* Revision 1.13 2001/05/09 12:40:31 johana
* Use DMA_NBR and IRQ_NBR defines from dma.h and irq.h
*
* Revision 1.12 2001/04/19 12:23:07 bjornw
* CONFIG_RS485 -> CONFIG_ETRAX_RS485
*
* Revision 1.11 2001/04/05 14:29:48 markusl
* Updated according to review remarks i.e.
* -Use correct types in port structure to avoid compiler warnings
* -Try to use IO_* macros whenever possible
* -Open should never return -EBUSY
*
* Revision 1.10 2001/03/05 13:14:07 bjornw
* Another spelling fix
*
* Revision 1.9 2001/02/23 13:46:38 bjornw
* Spellling check
*
* Revision 1.8 2001/01/23 14:56:35 markusl
* Made use of ser1 optional
* Needed by USB
*
* Revision 1.7 2001/01/19 16:14:48 perf
* Added kernel options for serial ports 234.
* Changed option names from CONFIG_ETRAX100_XYZ to CONFIG_ETRAX_XYZ.
*
* Revision 1.6 2000/11/22 16:36:09 bjornw
* Please marketing by using the correct case when spelling Etrax.
*
* Revision 1.5 2000/11/21 16:43:37 bjornw
* Fixed so it compiles under CONFIG_SVINTO_SIM
*
* Revision 1.4 2000/11/15 17:34:12 bjornw
* Added a timeout timer for flushing input channels. The interrupt-based
* fast flush system should be easy to merge with this later (works the same
* way, only with an irq instead of a system timer_list)
*
* Revision 1.3 2000/11/13 17:19:57 bjornw
* * Incredibly, this almost complete rewrite of serial.c worked (at least
* for output) the first time.
*
* Items worth noticing:
*
* No Etrax100 port 1 workarounds (does only compile on 2.4 anyway now)
* RS485 is not ported (why can't it be done in userspace as on x86 ?)
* Statistics done through async_icount - if any more stats are needed,
* that's the place to put them or in an arch-dep version of it.
* timeout_interrupt and the other fast timeout stuff not ported yet
* There be dragons in this 3k+ line driver
*
* Revision 1.2 2000/11/10 16:50:28 bjornw
* First shot at a 2.4 port, does not compile totally yet
*
* Revision 1.1 2000/11/10 16:47:32 bjornw
* Added verbatim copy of rev 1.49 etrax100ser.c from elinux
*
* Revision 1.49 2000/10/30 15:47:14 tobiasa
* Changed version number.
*
* Revision 1.48 2000/10/25 11:02:43 johana
* Changed %ul to %lu in printf's
*
* Revision 1.47 2000/10/18 15:06:53 pkj
* Compile correctly with CONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST and
* CONFIG_ETRAX_SERIAL_PROC_ENTRY together.
* Some clean-up of the /proc/serial file.
*
* Revision 1.46 2000/10/16 12:59:40 johana
* Added CONFIG_ETRAX_SERIAL_PROC_ENTRY for statistics and debug info.
*
* Revision 1.45 2000/10/13 17:10:59 pkj
* Do not flush DMAs while flipping TTY buffers.
*
* Revision 1.44 2000/10/13 16:34:29 pkj
* Added a delay in ser_interrupt() for 2.3ms when an error is detected.
* We do not know why this delay is required yet, but without it the
* irmaflash program does not work (this was the program that needed
* the ser_interrupt() to be needed in the first place). This should not
* affect normal use of the serial ports.
*
* Revision 1.43 2000/10/13 16:30:44 pkj
* New version of the fast flush of serial buffers code. This time
* it is localized to the serial driver and uses a fast timer to
* do the work.
*
* Revision 1.42 2000/10/13 14:54:26 bennyo
* Fix for switching RTS when using rs485
*
* Revision 1.41 2000/10/12 11:43:44 pkj
* Cleaned up a number of comments.
*
* Revision 1.40 2000/10/10 11:58:39 johana
* Made RS485 support generic for all ports.
* Toggle rts in interrupt if no delay wanted.
* WARNING: No true transmitter empty check??
* Set d_wait bit when sending data so interrupt is delayed until
* fifo flushed. (Fix tcdrain() problem)
*
* Revision 1.39 2000/10/04 16:08:02 bjornw
* * Use virt_to_phys etc. for DMA addresses
* * Removed CONFIG_FLUSH_DMA_FAST hacks
* * Indentation fix
*
* Revision 1.38 2000/10/02 12:27:10 mattias
* * added variable used when using fast flush on serial dma.
* (CONFIG_FLUSH_DMA_FAST)
*
* Revision 1.37 2000/09/27 09:44:24 pkj
* Uncomment definition of SERIAL_HANDLE_EARLY_ERRORS.
*
* Revision 1.36 2000/09/20 13:12:52 johana
* Support for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS:
* Number of timer ticks between flush of receive fifo (1 tick = 10ms).
* Try 0-3 for low latency applications. Approx 5 for high load
* applications (e.g. PPP). Maybe this should be more adaptive some day...
*
* Revision 1.35 2000/09/20 10:36:08 johana
* Typo in get_lsr_info()
*
* Revision 1.34 2000/09/20 10:29:59 johana
* Let rs_chars_in_buffer() check fifo content as well.
* get_lsr_info() might work now (not tested).
* Easier to change the port to debug.
*
* Revision 1.33 2000/09/13 07:52:11 torbjore
* Support RS485
*
* Revision 1.32 2000/08/31 14:45:37 bjornw
* After sending a break we need to reset the transmit DMA channel
*
* Revision 1.31 2000/06/21 12:13:29 johana
* Fixed wait for all chars sent when closing port.
* (Used to always take 1 second!)
* Added shadows for directions of status/ctrl signals.
*
* Revision 1.30 2000/05/29 16:27:55 bjornw
* Simulator ifdef moved a bit
*
* Revision 1.29 2000/05/09 09:40:30 mattias
* * Added description of dma registers used in timeout_interrupt
* * Removed old code
*
* Revision 1.28 2000/05/08 16:38:58 mattias
* * Bugfix for flushing fifo in timeout_interrupt
* Problem occurs when bluetooth stack waits for a small number of bytes
* containing an event acknowledging free buffers in bluetooth HW
* As before, data was stuck in fifo until more data came on uart and
* flushed it up to the stack.
*
* Revision 1.27 2000/05/02 09:52:28 jonasd
* Added fix for peculiar etrax behaviour when eop is forced on an empty
* fifo. This is used when flashing the IRMA chip. Disabled by default.
*
* Revision 1.26 2000/03/29 15:32:02 bjornw
* 2.0.34 updates
*
* Revision 1.25 2000/02/16 16:59:36 bjornw
* * Receive DMA directly into the flip-buffer, eliminating an intermediary
* receive buffer and a memcpy. Will avoid some overruns.
* * Error message on debug port if an overrun or flip buffer overrun occurs.
* * Just use the first byte in the flag flip buffer for errors.
* * Check for timeout on the serial ports only each 5/100 s, not 1/100.
*
* Revision 1.24 2000/02/09 18:02:28 bjornw
* * Clear serial errors (overrun, framing, parity) correctly. Before, the
* receiver would get stuck if an error occurred and we did not restart
* the input DMA.
* * Cosmetics (indentation, some code made into inlines)
* * Some more debug options
* * Actually shut down the serial port (DMA irq, DMA reset, receiver stop)
* when the last open is closed. Corresponding fixes in startup().
* * rs_close() "tx FIFO wait" code moved into right place, bug & -> && fixed
* and make a special case out of port 1 (R_DMA_CHx_STATUS is broken for that)
* * e100_disable_rx/enable_rx just disables/enables the receiver, not RTS
*
* Revision 1.23 2000/01/24 17:46:19 johana
* Wait for flush of DMA/FIFO when closing port.
*
* Revision 1.22 2000/01/20 18:10:23 johana
* Added TIOCMGET ioctl to return modem status.
* Implemented modem status/control that works with the extra signals
* (DTR, DSR, RI,CD) as well.
* 3 different modes supported:
* ser0 on PB (Bundy), ser1 on PB (Lisa) and ser2 on PA (Bundy)
* Fixed DEF_TX value that caused the serial transmitter pin (txd) to go to 0 when
* closing the last filehandle, NASTY!.
* Added break generation, not tested though!
* Use IRQF_SHARED when request_irq() for ser2 and ser3 (shared with) par0 and par1.
* You can't use them at the same time (yet..), but you can hopefully switch
* between ser2/par0, ser3/par1 with the same kernel config.
* Replaced some magic constants with defines
*
*
*/
static char *serial_version = "$Revision: 1.25 $";
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/fcntl.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <asm/uaccess.h>
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/delay.h>
#include <asm/arch/svinto.h>
/* non-arch dependent serial structures are in linux/serial.h */
#include <linux/serial.h>
/* while we keep our own stuff (struct e100_serial) in a local .h file */
#include "serial.h"
#include <asm/fasttimer.h>
#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
#ifndef CONFIG_ETRAX_FAST_TIMER
#error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
#endif
#endif
#if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
#error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
#endif
#if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
#error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
#endif
/*
* All of the compatibilty code so we can compile serial.c against
* older kernels is hidden in serial_compat.h
*/
#if defined(LOCAL_HEADERS)
#include "serial_compat.h"
#endif
struct tty_driver *serial_driver;
/* serial subtype definitions */
#ifndef SERIAL_TYPE_NORMAL
#define SERIAL_TYPE_NORMAL 1
#endif
/* number of characters left in xmit buffer before we ask for more */
#define WAKEUP_CHARS 256
//#define SERIAL_DEBUG_INTR
//#define SERIAL_DEBUG_OPEN
//#define SERIAL_DEBUG_FLOW
//#define SERIAL_DEBUG_DATA
//#define SERIAL_DEBUG_THROTTLE
//#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
//#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
/* Enable this to use serial interrupts to handle when you
expect the first received event on the serial port to
be an error, break or similar. Used to be able to flash IRMA
from eLinux */
#define SERIAL_HANDLE_EARLY_ERRORS
/* Defined and used in n_tty.c, but we need it here as well */
#define TTY_THRESHOLD_THROTTLE 128
/* Due to buffersizes and threshold values, our SERIAL_DESCR_BUF_SIZE
* must not be to high or flow control won't work if we leave it to the tty
* layer so we have our own throttling in flush_to_flip
* TTY_FLIPBUF_SIZE=512,
* TTY_THRESHOLD_THROTTLE/UNTHROTTLE=128
* BUF_SIZE can't be > 128
*/
/* Currently 16 descriptors x 128 bytes = 2048 bytes */
#define SERIAL_DESCR_BUF_SIZE 256
#define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
#define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
/* We don't want to load the system with massive fast timer interrupt
* on high baudrates so limit it to 250 us (4kHz) */
#define MIN_FLUSH_TIME_USEC 250
/* Add an x here to log a lot of timer stuff */
#define TIMERD(x)
/* Debug details of interrupt handling */
#define DINTR1(x) /* irq on/off, errors */
#define DINTR2(x) /* tx and rx */
/* Debug flip buffer stuff */
#define DFLIP(x)
/* Debug flow control and overview of data flow */
#define DFLOW(x)
#define DBAUD(x)
#define DLOG_INT_TRIG(x)
//#define DEBUG_LOG_INCLUDED
#ifndef DEBUG_LOG_INCLUDED
#define DEBUG_LOG(line, string, value)
#else
struct debug_log_info
{
unsigned long time;
unsigned long timer_data;
// int line;
const char *string;
int value;
};
#define DEBUG_LOG_SIZE 4096
struct debug_log_info debug_log[DEBUG_LOG_SIZE];
int debug_log_pos = 0;
#define DEBUG_LOG(_line, _string, _value) do { \
if ((_line) == SERIAL_DEBUG_LINE) {\
debug_log_func(_line, _string, _value); \
}\
}while(0)
void debug_log_func(int line, const char *string, int value)
{
if (debug_log_pos < DEBUG_LOG_SIZE) {
debug_log[debug_log_pos].time = jiffies;
debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
// debug_log[debug_log_pos].line = line;
debug_log[debug_log_pos].string = string;
debug_log[debug_log_pos].value = value;
debug_log_pos++;
}
/*printk(string, value);*/
}
#endif
#ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
/* Default number of timer ticks before flushing rx fifo
* When using "little data, low latency applications: use 0
* When using "much data applications (PPP)" use ~5
*/
#define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
#endif
unsigned long timer_data_to_ns(unsigned long timer_data);
static void change_speed(struct e100_serial *info);
static void rs_throttle(struct tty_struct * tty);
static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
static int rs_write(struct tty_struct * tty, int from_user,
const unsigned char *buf, int count);
#ifdef CONFIG_ETRAX_RS485
static int e100_write_rs485(struct tty_struct * tty, int from_user,
const unsigned char *buf, int count);
#endif
static int get_lsr_info(struct e100_serial * info, unsigned int *value);
#define DEF_BAUD 115200 /* 115.2 kbit/s */
#define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
#define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
/* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
#define DEF_TX 0x80 /* or SERIAL_CTRL_B */
/* offsets from R_SERIALx_CTRL */
#define REG_DATA 0
#define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
#define REG_TR_DATA 0
#define REG_STATUS 1
#define REG_TR_CTRL 1
#define REG_REC_CTRL 2
#define REG_BAUD 3
#define REG_XOFF 4 /* this is a 32 bit register */
/* The bitfields are the same for all serial ports */
#define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
#define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
#define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
#define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
#define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
#define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
/* Values for info->errorcode */
#define ERRCODE_SET_BREAK (TTY_BREAK)
#define ERRCODE_INSERT 0x100
#define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
#define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
/*
* General note regarding the use of IO_* macros in this file:
*
* We will use the bits defined for DMA channel 6 when using various
* IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
* the same for all channels (which of course they are).
*
* We will also use the bits defined for serial port 0 when writing commands
* to the different ports, as these bits too are the same for all ports.
*/
/* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
static const unsigned long e100_ser_int_mask = 0
#ifdef CONFIG_ETRAX_SERIAL_PORT0
| IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT1
| IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT2
| IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT3
| IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
#endif
;
unsigned long r_alt_ser_baudrate_shadow = 0;
/* this is the data for the four serial ports in the etrax100 */
/* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
/* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
static struct e100_serial rs_table[] = {
{ .baud = DEF_BAUD,
.port = (unsigned char *)R_SERIAL0_CTRL,
.irq = 1U << 12, /* uses DMA 6 and 7 */
.oclrintradr = R_DMA_CH6_CLR_INTR,
.ofirstadr = R_DMA_CH6_FIRST,
.ocmdadr = R_DMA_CH6_CMD,
.ostatusadr = R_DMA_CH6_STATUS,
.iclrintradr = R_DMA_CH7_CLR_INTR,
.ifirstadr = R_DMA_CH7_FIRST,
.icmdadr = R_DMA_CH7_CMD,
.idescradr = R_DMA_CH7_DESCR,
.flags = STD_FLAGS,
.rx_ctrl = DEF_RX,
.tx_ctrl = DEF_TX,
.iseteop = 2,
#ifdef CONFIG_ETRAX_SERIAL_PORT0
.enabled = 1,
#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
.dma_out_enabled = 1,
#else
.dma_out_enabled = 0,
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
.dma_in_enabled = 1,
#else
.dma_in_enabled = 0
#endif
#else
.enabled = 0,
.dma_out_enabled = 0,
.dma_in_enabled = 0
#endif
}, /* ttyS0 */
#ifndef CONFIG_SVINTO_SIM
{ .baud = DEF_BAUD,
.port = (unsigned char *)R_SERIAL1_CTRL,
.irq = 1U << 16, /* uses DMA 8 and 9 */
.oclrintradr = R_DMA_CH8_CLR_INTR,
.ofirstadr = R_DMA_CH8_FIRST,
.ocmdadr = R_DMA_CH8_CMD,
.ostatusadr = R_DMA_CH8_STATUS,
.iclrintradr = R_DMA_CH9_CLR_INTR,
.ifirstadr = R_DMA_CH9_FIRST,
.icmdadr = R_DMA_CH9_CMD,
.idescradr = R_DMA_CH9_DESCR,
.flags = STD_FLAGS,
.rx_ctrl = DEF_RX,
.tx_ctrl = DEF_TX,
.iseteop = 3,
#ifdef CONFIG_ETRAX_SERIAL_PORT1
.enabled = 1,
#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
.dma_out_enabled = 1,
#else
.dma_out_enabled = 0,
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
.dma_in_enabled = 1,
#else
.dma_in_enabled = 0
#endif
#else
.enabled = 0,
.dma_out_enabled = 0,
.dma_in_enabled = 0
#endif
}, /* ttyS1 */
{ .baud = DEF_BAUD,
.port = (unsigned char *)R_SERIAL2_CTRL,
.irq = 1U << 4, /* uses DMA 2 and 3 */
.oclrintradr = R_DMA_CH2_CLR_INTR,
.ofirstadr = R_DMA_CH2_FIRST,
.ocmdadr = R_DMA_CH2_CMD,
.ostatusadr = R_DMA_CH2_STATUS,
.iclrintradr = R_DMA_CH3_CLR_INTR,
.ifirstadr = R_DMA_CH3_FIRST,
.icmdadr = R_DMA_CH3_CMD,
.idescradr = R_DMA_CH3_DESCR,
.flags = STD_FLAGS,
.rx_ctrl = DEF_RX,
.tx_ctrl = DEF_TX,
.iseteop = 0,
#ifdef CONFIG_ETRAX_SERIAL_PORT2
.enabled = 1,
#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
.dma_out_enabled = 1,
#else
.dma_out_enabled = 0,
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
.dma_in_enabled = 1,
#else
.dma_in_enabled = 0
#endif
#else
.enabled = 0,
.dma_out_enabled = 0,
.dma_in_enabled = 0
#endif
}, /* ttyS2 */
{ .baud = DEF_BAUD,
.port = (unsigned char *)R_SERIAL3_CTRL,
.irq = 1U << 8, /* uses DMA 4 and 5 */
.oclrintradr = R_DMA_CH4_CLR_INTR,
.ofirstadr = R_DMA_CH4_FIRST,
.ocmdadr = R_DMA_CH4_CMD,
.ostatusadr = R_DMA_CH4_STATUS,
.iclrintradr = R_DMA_CH5_CLR_INTR,
.ifirstadr = R_DMA_CH5_FIRST,
.icmdadr = R_DMA_CH5_CMD,
.idescradr = R_DMA_CH5_DESCR,
.flags = STD_FLAGS,
.rx_ctrl = DEF_RX,
.tx_ctrl = DEF_TX,
.iseteop = 1,
#ifdef CONFIG_ETRAX_SERIAL_PORT3
.enabled = 1,
#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
.dma_out_enabled = 1,
#else
.dma_out_enabled = 0,
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
.dma_in_enabled = 1,
#else
.dma_in_enabled = 0
#endif
#else
.enabled = 0,
.dma_out_enabled = 0,
.dma_in_enabled = 0
#endif
} /* ttyS3 */
#endif
};
#define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
static struct ktermios *serial_termios[NR_PORTS];
static struct ktermios *serial_termios_locked[NR_PORTS];
#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
static struct fast_timer fast_timers[NR_PORTS];
#endif
#ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
#define PROCSTAT(x) x
struct ser_statistics_type {
int overrun_cnt;
int early_errors_cnt;
int ser_ints_ok_cnt;
int errors_cnt;
unsigned long int processing_flip;
unsigned long processing_flip_still_room;
unsigned long int timeout_flush_cnt;
int rx_dma_ints;
int tx_dma_ints;
int rx_tot;
int tx_tot;
};
static struct ser_statistics_type ser_stat[NR_PORTS];
#else
#define PROCSTAT(x)
#endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
/* RS-485 */
#if defined(CONFIG_ETRAX_RS485)
#ifdef CONFIG_ETRAX_FAST_TIMER
static struct fast_timer fast_timers_rs485[NR_PORTS];
#endif
#if defined(CONFIG_ETRAX_RS485_ON_PA)
static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
#endif
#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
#endif
#endif
/* Info and macros needed for each ports extra control/status signals. */
#define E100_STRUCT_PORT(line, pinname) \
((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
(R_PORT_PA_DATA): ( \
(CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
(R_PORT_PB_DATA):&dummy_ser[line]))
#define E100_STRUCT_SHADOW(line, pinname) \
((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
(&port_pa_data_shadow): ( \
(CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
(&port_pb_data_shadow):&dummy_ser[line]))
#define E100_STRUCT_MASK(line, pinname) \
((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
(1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
(CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
(1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
#define DUMMY_DTR_MASK 1
#define DUMMY_RI_MASK 2
#define DUMMY_DSR_MASK 4
#define DUMMY_CD_MASK 8
static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
/* If not all status pins are used or disabled, use mixed mode */
#ifdef CONFIG_ETRAX_SERIAL_PORT0
#define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
#if SER0_PA_BITSUM != -4
# if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
#endif
#define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
#if SER0_PB_BITSUM != -4
# if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
#endif
#endif /* PORT0 */
#ifdef CONFIG_ETRAX_SERIAL_PORT1
#define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
#if SER1_PA_BITSUM != -4
# if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
#endif
#define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
#if SER1_PB_BITSUM != -4
# if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
#endif
#endif /* PORT1 */
#ifdef CONFIG_ETRAX_SERIAL_PORT2
#define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
#if SER2_PA_BITSUM != -4
# if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
#endif
#define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
#if SER2_PB_BITSUM != -4
# if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
#endif
#endif /* PORT2 */
#ifdef CONFIG_ETRAX_SERIAL_PORT3
#define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
#if SER3_PA_BITSUM != -4
# if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
#endif
#define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
#if SER3_PB_BITSUM != -4
# if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
# if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
# endif
# endif
#endif
#endif /* PORT3 */
#if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
#define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
#endif
#ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
/* The pins can be mixed on PA and PB */
#define CONTROL_PINS_PORT_NOT_USED(line) \
&dummy_ser[line], &dummy_ser[line], \
&dummy_ser[line], &dummy_ser[line], \
&dummy_ser[line], &dummy_ser[line], \
&dummy_ser[line], &dummy_ser[line], \
DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
struct control_pins
{
volatile unsigned char *dtr_port;
unsigned char *dtr_shadow;
volatile unsigned char *ri_port;
unsigned char *ri_shadow;
volatile unsigned char *dsr_port;
unsigned char *dsr_shadow;
volatile unsigned char *cd_port;
unsigned char *cd_shadow;
unsigned char dtr_mask;
unsigned char ri_mask;
unsigned char dsr_mask;
unsigned char cd_mask;
};
static const struct control_pins e100_modem_pins[NR_PORTS] =
{
/* Ser 0 */
{
#ifdef CONFIG_ETRAX_SERIAL_PORT0
E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
E100_STRUCT_MASK(0,DTR),
E100_STRUCT_MASK(0,RI),
E100_STRUCT_MASK(0,DSR),
E100_STRUCT_MASK(0,CD)
#else
CONTROL_PINS_PORT_NOT_USED(0)
#endif
},
/* Ser 1 */
{
#ifdef CONFIG_ETRAX_SERIAL_PORT1
E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
E100_STRUCT_MASK(1,DTR),
E100_STRUCT_MASK(1,RI),
E100_STRUCT_MASK(1,DSR),
E100_STRUCT_MASK(1,CD)
#else
CONTROL_PINS_PORT_NOT_USED(1)
#endif
},
/* Ser 2 */
{
#ifdef CONFIG_ETRAX_SERIAL_PORT2
E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
E100_STRUCT_MASK(2,DTR),
E100_STRUCT_MASK(2,RI),
E100_STRUCT_MASK(2,DSR),
E100_STRUCT_MASK(2,CD)
#else
CONTROL_PINS_PORT_NOT_USED(2)
#endif
},
/* Ser 3 */
{
#ifdef CONFIG_ETRAX_SERIAL_PORT3
E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
E100_STRUCT_MASK(3,DTR),
E100_STRUCT_MASK(3,RI),
E100_STRUCT_MASK(3,DSR),
E100_STRUCT_MASK(3,CD)
#else
CONTROL_PINS_PORT_NOT_USED(3)
#endif
}
};
#else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
/* All pins are on either PA or PB for each serial port */
#define CONTROL_PINS_PORT_NOT_USED(line) \
&dummy_ser[line], &dummy_ser[line], \
DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
struct control_pins
{
volatile unsigned char *port;
unsigned char *shadow;
unsigned char dtr_mask;
unsigned char ri_mask;
unsigned char dsr_mask;
unsigned char cd_mask;
};
#define dtr_port port
#define dtr_shadow shadow
#define ri_port port
#define ri_shadow shadow
#define dsr_port port
#define dsr_shadow shadow
#define cd_port port
#define cd_shadow shadow
static const struct control_pins e100_modem_pins[NR_PORTS] =
{
/* Ser 0 */
{
#ifdef CONFIG_ETRAX_SERIAL_PORT0
E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
E100_STRUCT_MASK(0,DTR),
E100_STRUCT_MASK(0,RI),
E100_STRUCT_MASK(0,DSR),
E100_STRUCT_MASK(0,CD)
#else
CONTROL_PINS_PORT_NOT_USED(0)
#endif
},
/* Ser 1 */
{
#ifdef CONFIG_ETRAX_SERIAL_PORT1
E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
E100_STRUCT_MASK(1,DTR),
E100_STRUCT_MASK(1,RI),
E100_STRUCT_MASK(1,DSR),
E100_STRUCT_MASK(1,CD)
#else
CONTROL_PINS_PORT_NOT_USED(1)
#endif
},
/* Ser 2 */
{
#ifdef CONFIG_ETRAX_SERIAL_PORT2
E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
E100_STRUCT_MASK(2,DTR),
E100_STRUCT_MASK(2,RI),
E100_STRUCT_MASK(2,DSR),
E100_STRUCT_MASK(2,CD)
#else
CONTROL_PINS_PORT_NOT_USED(2)
#endif
},
/* Ser 3 */
{
#ifdef CONFIG_ETRAX_SERIAL_PORT3
E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
E100_STRUCT_MASK(3,DTR),
E100_STRUCT_MASK(3,RI),
E100_STRUCT_MASK(3,DSR),
E100_STRUCT_MASK(3,CD)
#else
CONTROL_PINS_PORT_NOT_USED(3)
#endif
}
};
#endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
#define E100_RTS_MASK 0x20
#define E100_CTS_MASK 0x40
/* All serial port signals are active low:
* active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
* inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
*
* These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
*/
/* Output */
#define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
/* Input */
#define E100_CTS_GET(info) ((info)->port[REG_STATUS] & E100_CTS_MASK)
/* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
/* Is an output */
#define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
/* Normally inputs */
#define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
#define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
/* Input */
#define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
/*
* tmp_buf is used as a temporary buffer by serial_write. We need to
* lock it in case the memcpy_fromfs blocks while swapping in a page,
* and some other program tries to do a serial write at the same time.
* Since the lock will only come under contention when the system is
* swapping and available memory is low, it makes sense to share one
* buffer across all the serial ports, since it significantly saves
* memory if large numbers of serial ports are open.
*/
static unsigned char *tmp_buf;
static DEFINE_MUTEX(tmp_buf_mutex);
/* Calculate the chartime depending on baudrate, numbor of bits etc. */
static void update_char_time(struct e100_serial * info)
{
tcflag_t cflags = info->tty->termios->c_cflag;
int bits;
/* calc. number of bits / data byte */
/* databits + startbit and 1 stopbit */
if ((cflags & CSIZE) == CS7)
bits = 9;
else
bits = 10;
if (cflags & CSTOPB) /* 2 stopbits ? */
bits++;
if (cflags & PARENB) /* parity bit ? */
bits++;
/* calc timeout */
info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
info->flush_time_usec = 4*info->char_time_usec;
if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
info->flush_time_usec = MIN_FLUSH_TIME_USEC;
}
/*
* This function maps from the Bxxxx defines in asm/termbits.h into real
* baud rates.
*/
static int
cflag_to_baud(unsigned int cflag)
{
static int baud_table[] = {
0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
4800, 9600, 19200, 38400 };
static int ext_baud_table[] = {
0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
0, 0, 0, 0, 0, 0, 0, 0 };
if (cflag & CBAUDEX)
return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
else
return baud_table[cflag & CBAUD];
}
/* and this maps to an etrax100 hardware baud constant */
static unsigned char
cflag_to_etrax_baud(unsigned int cflag)
{
char retval;
static char baud_table[] = {
-1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
static char ext_baud_table[] = {
-1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
if (cflag & CBAUDEX)
retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
else
retval = baud_table[cflag & CBAUD];
if (retval < 0) {
printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
retval = 5; /* choose default 9600 instead */
}
return retval | (retval << 4); /* choose same for both TX and RX */
}
/* Various static support functions */
/* Functions to set or clear DTR/RTS on the requested line */
/* It is complicated by the fact that RTS is a serial port register, while
* DTR might not be implemented in the HW at all, and if it is, it can be on
* any general port.
*/
static inline void
e100_dtr(struct e100_serial *info, int set)
{
#ifndef CONFIG_SVINTO_SIM
unsigned char mask = e100_modem_pins[info->line].dtr_mask;
#ifdef SERIAL_DEBUG_IO
printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
printk("ser%i shadow before 0x%02X get: %i\n",
info->line, *e100_modem_pins[info->line].dtr_shadow,
E100_DTR_GET(info));
#endif
/* DTR is active low */
{
unsigned long flags;
save_flags(flags);
cli();
*e100_modem_pins[info->line].dtr_shadow &= ~mask;
*e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
*e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
restore_flags(flags);
}
#ifdef SERIAL_DEBUG_IO
printk("ser%i shadow after 0x%02X get: %i\n",
info->line, *e100_modem_pins[info->line].dtr_shadow,
E100_DTR_GET(info));
#endif
#endif
}
/* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
* 0=0V , 1=3.3V
*/
static inline void
e100_rts(struct e100_serial *info, int set)
{
#ifndef CONFIG_SVINTO_SIM
unsigned long flags;
save_flags(flags);
cli();
info->rx_ctrl &= ~E100_RTS_MASK;
info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
info->port[REG_REC_CTRL] = info->rx_ctrl;
restore_flags(flags);
#ifdef SERIAL_DEBUG_IO
printk("ser%i rts %i\n", info->line, set);
#endif
#endif
}
/* If this behaves as a modem, RI and CD is an output */
static inline void
e100_ri_out(struct e100_serial *info, int set)
{
#ifndef CONFIG_SVINTO_SIM
/* RI is active low */
{
unsigned char mask = e100_modem_pins[info->line].ri_mask;
unsigned long flags;
save_flags(flags);
cli();
*e100_modem_pins[info->line].ri_shadow &= ~mask;
*e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
*e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
restore_flags(flags);
}
#endif
}
static inline void
e100_cd_out(struct e100_serial *info, int set)
{
#ifndef CONFIG_SVINTO_SIM
/* CD is active low */
{
unsigned char mask = e100_modem_pins[info->line].cd_mask;
unsigned long flags;
save_flags(flags);
cli();
*e100_modem_pins[info->line].cd_shadow &= ~mask;
*e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
*e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
restore_flags(flags);
}
#endif
}
static inline void
e100_disable_rx(struct e100_serial *info)
{
#ifndef CONFIG_SVINTO_SIM
/* disable the receiver */
info->port[REG_REC_CTRL] =
(info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
#endif
}
static inline void
e100_enable_rx(struct e100_serial *info)
{
#ifndef CONFIG_SVINTO_SIM
/* enable the receiver */
info->port[REG_REC_CTRL] =
(info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
#endif
}
/* the rx DMA uses both the dma_descr and the dma_eop interrupts */
static inline void
e100_disable_rxdma_irq(struct e100_serial *info)
{
#ifdef SERIAL_DEBUG_INTR
printk("rxdma_irq(%d): 0\n",info->line);
#endif
DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
*R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
}
static inline void
e100_enable_rxdma_irq(struct e100_serial *info)
{
#ifdef SERIAL_DEBUG_INTR
printk("rxdma_irq(%d): 1\n",info->line);
#endif
DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
*R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
}
/* the tx DMA uses only dma_descr interrupt */
static void e100_disable_txdma_irq(struct e100_serial *info)
{
#ifdef SERIAL_DEBUG_INTR
printk("txdma_irq(%d): 0\n",info->line);
#endif
DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
*R_IRQ_MASK2_CLR = info->irq;
}
static void e100_enable_txdma_irq(struct e100_serial *info)
{
#ifdef SERIAL_DEBUG_INTR
printk("txdma_irq(%d): 1\n",info->line);
#endif
DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
*R_IRQ_MASK2_SET = info->irq;
}
static void e100_disable_txdma_channel(struct e100_serial *info)
{
unsigned long flags;
/* Disable output DMA channel for the serial port in question
* ( set to something other then serialX)
*/
save_flags(flags);
cli();
DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
if (info->line == 0) {
if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
}
} else if (info->line == 1) {
if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
}
} else if (info->line == 2) {
if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
}
} else if (info->line == 3) {
if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
}
}
*R_GEN_CONFIG = genconfig_shadow;
restore_flags(flags);
}
static void e100_enable_txdma_channel(struct e100_serial *info)
{
unsigned long flags;
save_flags(flags);
cli();
DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
/* Enable output DMA channel for the serial port in question */
if (info->line == 0) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
} else if (info->line == 1) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
} else if (info->line == 2) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
} else if (info->line == 3) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
}
*R_GEN_CONFIG = genconfig_shadow;
restore_flags(flags);
}
static void e100_disable_rxdma_channel(struct e100_serial *info)
{
unsigned long flags;
/* Disable input DMA channel for the serial port in question
* ( set to something other then serialX)
*/
save_flags(flags);
cli();
if (info->line == 0) {
if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
}
} else if (info->line == 1) {
if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
}
} else if (info->line == 2) {
if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
}
} else if (info->line == 3) {
if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
}
}
*R_GEN_CONFIG = genconfig_shadow;
restore_flags(flags);
}
static void e100_enable_rxdma_channel(struct e100_serial *info)
{
unsigned long flags;
save_flags(flags);
cli();
/* Enable input DMA channel for the serial port in question */
if (info->line == 0) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
} else if (info->line == 1) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
} else if (info->line == 2) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
} else if (info->line == 3) {
genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
}
*R_GEN_CONFIG = genconfig_shadow;
restore_flags(flags);
}
#ifdef SERIAL_HANDLE_EARLY_ERRORS
/* in order to detect and fix errors on the first byte
we have to use the serial interrupts as well. */
static inline void
e100_disable_serial_data_irq(struct e100_serial *info)
{
#ifdef SERIAL_DEBUG_INTR
printk("ser_irq(%d): 0\n",info->line);
#endif
DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
*R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
}
static inline void
e100_enable_serial_data_irq(struct e100_serial *info)
{
#ifdef SERIAL_DEBUG_INTR
printk("ser_irq(%d): 1\n",info->line);
printk("**** %d = %d\n",
(8+2*info->line),
(1U << (8+2*info->line)));
#endif
DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
*R_IRQ_MASK1_SET = (1U << (8+2*info->line));
}
#endif
static inline void
e100_disable_serial_tx_ready_irq(struct e100_serial *info)
{
#ifdef SERIAL_DEBUG_INTR
printk("ser_tx_irq(%d): 0\n",info->line);
#endif
DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
*R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
}
static inline void
e100_enable_serial_tx_ready_irq(struct e100_serial *info)
{
#ifdef SERIAL_DEBUG_INTR
printk("ser_tx_irq(%d): 1\n",info->line);
printk("**** %d = %d\n",
(8+1+2*info->line),
(1U << (8+1+2*info->line)));
#endif
DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
*R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
}
static inline void e100_enable_rx_irq(struct e100_serial *info)
{
if (info->uses_dma_in)
e100_enable_rxdma_irq(info);
else
e100_enable_serial_data_irq(info);
}
static inline void e100_disable_rx_irq(struct e100_serial *info)
{
if (info->uses_dma_in)
e100_disable_rxdma_irq(info);
else
e100_disable_serial_data_irq(info);
}
#if defined(CONFIG_ETRAX_RS485)
/* Enable RS-485 mode on selected port. This is UGLY. */
static int
e100_enable_rs485(struct tty_struct *tty,struct rs485_control *r)
{
struct e100_serial * info = (struct e100_serial *)tty->driver_data;
#if defined(CONFIG_ETRAX_RS485_ON_PA)
*R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
#endif
#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
rs485_port_g_bit, 1);
#endif
#if defined(CONFIG_ETRAX_RS485_LTC1387)
REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1);
REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
#endif
info->rs485.rts_on_send = 0x01 & r->rts_on_send;
info->rs485.rts_after_sent = 0x01 & r->rts_after_sent;
if (r->delay_rts_before_send >= 1000)
info->rs485.delay_rts_before_send = 1000;
else
info->rs485.delay_rts_before_send = r->delay_rts_before_send;
info->rs485.enabled = r->enabled;
/* printk("rts: on send = %i, after = %i, enabled = %i",
info->rs485.rts_on_send,
info->rs485.rts_after_sent,
info->rs485.enabled
);
*/
return 0;
}
static int
e100_write_rs485(struct tty_struct *tty, int from_user,
const unsigned char *buf, int count)
{
struct e100_serial * info = (struct e100_serial *)tty->driver_data;
int old_enabled = info->rs485.enabled;
/* rs485 is always implicitly enabled if we're using the ioctl()
* but it doesn't have to be set in the rs485_control
* (to be backward compatible with old apps)
* So we store, set and restore it.
*/
info->rs485.enabled = 1;
/* rs_write now deals with RS485 if enabled */
count = rs_write(tty, from_user, buf, count);
info->rs485.enabled = old_enabled;
return count;
}
#ifdef CONFIG_ETRAX_FAST_TIMER
/* Timer function to toggle RTS when using FAST_TIMER */
static void rs485_toggle_rts_timer_function(unsigned long data)
{
struct e100_serial *info = (struct e100_serial *)data;
fast_timers_rs485[info->line].function = NULL;
e100_rts(info, info->rs485.rts_after_sent);
#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
e100_enable_rx(info);
e100_enable_rx_irq(info);
#endif
}
#endif
#endif /* CONFIG_ETRAX_RS485 */
/*
* ------------------------------------------------------------
* rs_stop() and rs_start()
*
* This routines are called before setting or resetting tty->stopped.
* They enable or disable transmitter using the XOFF registers, as necessary.
* ------------------------------------------------------------
*/
static void
rs_stop(struct tty_struct *tty)
{
struct e100_serial *info = (struct e100_serial *)tty->driver_data;
if (info) {
unsigned long flags;
unsigned long xoff;
save_flags(flags); cli();
DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
CIRC_CNT(info->xmit.head,
info->xmit.tail,SERIAL_XMIT_SIZE)));
xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->tty));
xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
if (tty->termios->c_iflag & IXON ) {
xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
}
*((unsigned long *)&info->port[REG_XOFF]) = xoff;
restore_flags(flags);
}
}
static void
rs_start(struct tty_struct *tty)
{
struct e100_serial *info = (struct e100_serial *)tty->driver_data;
if (info) {
unsigned long flags;
unsigned long xoff;
save_flags(flags); cli();
DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
CIRC_CNT(info->xmit.head,
info->xmit.tail,SERIAL_XMIT_SIZE)));
xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
if (tty->termios->c_iflag & IXON ) {
xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
}
*((unsigned long *)&info->port[REG_XOFF]) = xoff;
if (!info->uses_dma_out &&
info->xmit.head != info->xmit.tail && info->xmit.buf)
e100_enable_serial_tx_ready_irq(info);
restore_flags(flags);
}
}
/*
* ----------------------------------------------------------------------
*
* Here starts the interrupt handling routines. All of the following
* subroutines are declared as inline and are folded into
* rs_interrupt(). They were separated out for readability's sake.
*
* Note: rs_interrupt() is a "fast" interrupt, which means that it
* runs with interrupts turned off. People who may want to modify
* rs_interrupt() should try to keep the interrupt handler as fast as
* possible. After you are done making modifications, it is not a bad
* idea to do:
*
* gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
*
* and look at the resulting assemble code in serial.s.
*
* - Ted Ts'o (tytso@mit.edu), 7-Mar-93
* -----------------------------------------------------------------------
*/
/*
* This routine is used by the interrupt handler to schedule
* processing in the software interrupt portion of the driver.
*/
static void rs_sched_event(struct e100_serial *info, int event)
{
if (info->event & (1 << event))
return;
info->event |= 1 << event;
schedule_work(&info->work);
}
/* The output DMA channel is free - use it to send as many chars as possible
* NOTES:
* We don't pay attention to info->x_char, which means if the TTY wants to
* use XON/XOFF it will set info->x_char but we won't send any X char!
*
* To implement this, we'd just start a DMA send of 1 byte pointing at a
* buffer containing the X char, and skip updating xmit. We'd also have to
* check if the last sent char was the X char when we enter this function
* the next time, to avoid updating xmit with the sent X value.
*/
static void
transmit_chars_dma(struct e100_serial *info)
{
unsigned int c, sentl;
struct etrax_dma_descr *descr;
#ifdef CONFIG_SVINTO_SIM
/* This will output too little if tail is not 0 always since
* we don't reloop to send the other part. Anyway this SHOULD be a
* no-op - transmit_chars_dma would never really be called during sim
* since rs_write does not write into the xmit buffer then.
*/
if (info->xmit.tail)
printk("Error in serial.c:transmit_chars-dma(), tail!=0\n");
if (info->xmit.head != info->xmit.tail) {
SIMCOUT(info->xmit.buf + info->xmit.tail,
CIRC_CNT(info->xmit.head,
info->xmit.tail,
SERIAL_XMIT_SIZE));
info->xmit.head = info->xmit.tail; /* move back head */
info->tr_running = 0;
}
return;
#endif
/* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
*info->oclrintradr =
IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
#ifdef SERIAL_DEBUG_INTR
if (info->line == SERIAL_DEBUG_LINE)
printk("tc\n");
#endif
if (!info->tr_running) {
/* weirdo... we shouldn't get here! */
printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
return;
}
descr = &info->tr_descr;
/* first get the amount of bytes sent during the last DMA transfer,
and update xmit accordingly */
/* if the stop bit was not set, all data has been sent */
if (!(descr->status & d_stop)) {
sentl = descr->sw_len;
} else
/* otherwise we find the amount of data sent here */
sentl = descr->hw_len;
DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
/* update stats */
info->icount.tx += sentl;
/* update xmit buffer */
info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
/* if there is only a few chars left in the buf, wake up the blocked
write if any */
if (CIRC_CNT(info->xmit.head,
info->xmit.tail,
SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
/* find out the largest amount of consecutive bytes we want to send now */
c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
/* Don't send all in one DMA transfer - divide it so we wake up
* application before all is sent
*/
if (c >= 4*WAKEUP_CHARS)
c = c/2;
if (c <= 0) {
/* our job here is done, don't schedule any new DMA transfer */
info->tr_running = 0;
#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
if (info->rs485.enabled) {
/* Set a short timer to toggle RTS */
start_one_shot_timer(&fast_timers_rs485[info->line],
rs485_toggle_rts_timer_function,
(unsigned long)info,
info->char_time_usec*2,
"RS-485");
}
#endif /* RS485 */
return;
}
/* ok we can schedule a dma send of c chars starting at info->xmit.tail */
/* set up the descriptor correctly for output */
DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
descr->sw_len = c;
descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
descr->status = 0;
*info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
*info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
/* DMA is now running (hopefully) */
} /* transmit_chars_dma */
static void
start_transmit(struct e100_serial *info)
{
#if 0
if (info->line == SERIAL_DEBUG_LINE)
printk("x\n");
#endif
info->tr_descr.sw_len = 0;
info->tr_descr.hw_len = 0;
info->tr_descr.status = 0;
info->tr_running = 1;
if (info->uses_dma_out)
transmit_chars_dma(info);
else
e100_enable_serial_tx_ready_irq(info);
} /* start_transmit */
#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
static int serial_fast_timer_started = 0;
static int serial_fast_timer_expired = 0;
static void flush_timeout_function(unsigned long data);
#define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
unsigned long timer_flags; \
save_flags(timer_flags); \
cli(); \
if (fast_timers[info->line].function == NULL) { \
serial_fast_timer_started++; \
TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
start_one_shot_timer(&fast_timers[info->line], \
flush_timeout_function, \
(unsigned long)info, \
(usec), \
string); \
} \
else { \
TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
} \
restore_flags(timer_flags); \
}
#define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
#else
#define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
#define START_FLUSH_FAST_TIMER(info, string)
#endif
static struct etrax_recv_buffer *
alloc_recv_buffer(unsigned int size)
{
struct etrax_recv_buffer *buffer;
if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
return NULL;
buffer->next = NULL;
buffer->length = 0;
buffer->error = TTY_NORMAL;
return buffer;
}
static void
append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
{
unsigned long flags;
save_flags(flags);
cli();
if (!info->first_recv_buffer)
info->first_recv_buffer = buffer;
else
info->last_recv_buffer->next = buffer;
info->last_recv_buffer = buffer;
info->recv_cnt += buffer->length;
if (info->recv_cnt > info->max_recv_cnt)
info->max_recv_cnt = info->recv_cnt;
restore_flags(flags);
}
static int
add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
{
struct etrax_recv_buffer *buffer;
if (info->uses_dma_in) {
if (!(buffer = alloc_recv_buffer(4)))
return 0;
buffer->length = 1;
buffer->error = flag;
buffer->buffer[0] = data;
append_recv_buffer(info, buffer);
info->icount.rx++;
} else {
struct tty_struct *tty = info->tty;
*tty->flip.char_buf_ptr = data;
*tty->flip.flag_buf_ptr = flag;
tty->flip.flag_buf_ptr++;
tty->flip.char_buf_ptr++;
tty->flip.count++;
info->icount.rx++;
}
return 1;
}
static unsigned int handle_descr_data(struct e100_serial *info,
struct etrax_dma_descr *descr,
unsigned int recvl)
{
struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
if (info->recv_cnt + recvl > 65536) {
printk(KERN_CRIT
"%s: Too much pending incoming serial data! Dropping %u bytes.\n", __FUNCTION__, recvl);
return 0;
}
buffer->length = recvl;
if (info->errorcode == ERRCODE_SET_BREAK)
buffer->error = TTY_BREAK;
info->errorcode = 0;
append_recv_buffer(info, buffer);
if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
panic("%s: Failed to allocate memory for receive buffer!\n", __FUNCTION__);
descr->buf = virt_to_phys(buffer->buffer);
return recvl;
}
static unsigned int handle_all_descr_data(struct e100_serial *info)
{
struct etrax_dma_descr *descr;
unsigned int recvl;
unsigned int ret = 0;
while (1)
{
descr = &info->rec_descr[info->cur_rec_descr];
if (descr == phys_to_virt(*info->idescradr))
break;
if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
info->cur_rec_descr = 0;
/* find out how many bytes were read */
/* if the eop bit was not set, all data has been received */
if (!(descr->status & d_eop)) {
recvl = descr->sw_len;
} else {
/* otherwise we find the amount of data received here */
recvl = descr->hw_len;
}
/* Reset the status information */
descr->status = 0;
DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
if (info->tty->stopped) {
unsigned char *buf = phys_to_virt(descr->buf);
DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
}
);
/* update stats */
info->icount.rx += recvl;
ret += handle_descr_data(info, descr, recvl);
}
return ret;
}
static void receive_chars_dma(struct e100_serial *info)
{
struct tty_struct *tty;
unsigned char rstat;
#ifdef CONFIG_SVINTO_SIM
/* No receive in the simulator. Will probably be when the rest of
* the serial interface works, and this piece will just be removed.
*/
return;
#endif
/* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
*info->iclrintradr =
IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
tty = info->tty;
if (!tty) /* Something wrong... */
return;
#ifdef SERIAL_HANDLE_EARLY_ERRORS
if (info->uses_dma_in)
e100_enable_serial_data_irq(info);
#endif
if (info->errorcode == ERRCODE_INSERT_BREAK)
add_char_and_flag(info, '\0', TTY_BREAK);
handle_all_descr_data(info);
/* Read the status register to detect errors */
rstat = info->port[REG_STATUS];
if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
}
if (rstat & SER_ERROR_MASK) {
/* If we got an error, we must reset it by reading the
* data_in field
*/
unsigned char data = info->port[REG_DATA];
PROCSTAT(ser_stat[info->line].errors_cnt++);
DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
((rstat & SER_ERROR_MASK) << 8) | data);
if (rstat & SER_PAR_ERR_MASK)
add_char_and_flag(info, data, TTY_PARITY);
else if (rstat & SER_OVERRUN_MASK)
add_char_and_flag(info, data, TTY_OVERRUN);
else if (rstat & SER_FRAMING_ERR_MASK)
add_char_and_flag(info, data, TTY_FRAME);
}
START_FLUSH_FAST_TIMER(info, "receive_chars");
/* Restart the receiving DMA */
*info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
}
static int start_recv_dma(struct e100_serial *info)
{
struct etrax_dma_descr *descr = info->rec_descr;
struct etrax_recv_buffer *buffer;
int i;
/* Set up the receiving descriptors */
for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
panic("%s: Failed to allocate memory for receive buffer!\n", __FUNCTION__);
descr[i].ctrl = d_int;
descr[i].buf = virt_to_phys(buffer->buffer);
descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
descr[i].hw_len = 0;
descr[i].status = 0;
descr[i].next = virt_to_phys(&descr[i+1]);
}
/* Link the last descriptor to the first */
descr[i-1].next = virt_to_phys(&descr[0]);
/* Start with the first descriptor in the list */
info->cur_rec_descr = 0;
/* Start the DMA */
*info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
*info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
/* Input DMA should be running now */
return 1;
}
static void
start_receive(struct e100_serial *info)
{
#ifdef CONFIG_SVINTO_SIM
/* No receive in the simulator. Will probably be when the rest of
* the serial interface works, and this piece will just be removed.
*/
return;
#endif
info->tty->flip.count = 0;
if (info->uses_dma_in) {
/* reset the input dma channel to be sure it works */
*info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
start_recv_dma(info);
}
}
/* the bits in the MASK2 register are laid out like this:
DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
where I is the input channel and O is the output channel for the port.
info->irq is the bit number for the DMAO_DESCR so to check the others we
shift info->irq to the left.
*/
/* dma output channel interrupt handler
this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
DMA8(ser1) when they have finished a descriptor with the intr flag set.
*/
static irqreturn_t
tr_interrupt(int irq, void *dev_id)
{
struct e100_serial *info;
unsigned long ireg;
int i;
int handled = 0;
#ifdef CONFIG_SVINTO_SIM
/* No receive in the simulator. Will probably be when the rest of
* the serial interface works, and this piece will just be removed.
*/
{
const char *s = "What? tr_interrupt in simulator??\n";
SIMCOUT(s,strlen(s));
}
return IRQ_HANDLED;
#endif
/* find out the line that caused this irq and get it from rs_table */
ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
for (i = 0; i < NR_PORTS; i++) {
info = rs_table + i;
if (!info->enabled || !info->uses_dma_out)
continue;
/* check for dma_descr (don't need to check for dma_eop in output dma for serial */
if (ireg & info->irq) {
handled = 1;
/* we can send a new dma bunch. make it so. */
DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
/* Read jiffies_usec first,
* we want this time to be as late as possible
*/
PROCSTAT(ser_stat[info->line].tx_dma_ints++);
info->last_tx_active_usec = GET_JIFFIES_USEC();
info->last_tx_active = jiffies;
transmit_chars_dma(info);
}
/* FIXME: here we should really check for a change in the
status lines and if so call status_handle(info) */
}
return IRQ_RETVAL(handled);
} /* tr_interrupt */
/* dma input channel interrupt handler */
static irqreturn_t
rec_interrupt(int irq, void *dev_id)
{
struct e100_serial *info;
unsigned long ireg;
int i;
int handled = 0;
#ifdef CONFIG_SVINTO_SIM
/* No receive in the simulator. Will probably be when the rest of
* the serial interface works, and this piece will just be removed.
*/
{
const char *s = "What? rec_interrupt in simulator??\n";
SIMCOUT(s,strlen(s));
}
return IRQ_HANDLED;
#endif
/* find out the line that caused this irq and get it from rs_table */
ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
for (i = 0; i < NR_PORTS; i++) {
info = rs_table + i;
if (!info->enabled || !info->uses_dma_in)
continue;
/* check for both dma_eop and dma_descr for the input dma channel */
if (ireg & ((info->irq << 2) | (info->irq << 3))) {
handled = 1;
/* we have received something */
receive_chars_dma(info);
}
/* FIXME: here we should really check for a change in the
status lines and if so call status_handle(info) */
}
return IRQ_RETVAL(handled);
} /* rec_interrupt */
static int force_eop_if_needed(struct e100_serial *info)
{
/* We check data_avail bit to determine if data has
* arrived since last time
*/
unsigned char rstat = info->port[REG_STATUS];
/* error or datavail? */
if (rstat & SER_ERROR_MASK) {
/* Some error has occurred. If there has been valid data, an
* EOP interrupt will be made automatically. If no data, the
* normal ser_interrupt should be enabled and handle it.
* So do nothing!
*/
DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
rstat | (info->line << 8));
return 0;
}
if (rstat & SER_DATA_AVAIL_MASK) {
/* Ok data, no error, count it */
TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
rstat | (info->line << 8)));
/* Read data to clear status flags */
(void)info->port[REG_DATA];
info->forced_eop = 0;
START_FLUSH_FAST_TIMER(info, "magic");
return 0;
}
/* hit the timeout, force an EOP for the input
* dma channel if we haven't already
*/
if (!info->forced_eop) {
info->forced_eop = 1;
PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
FORCE_EOP(info);
}
return 1;
}
static void flush_to_flip_buffer(struct e100_serial *info)
{
struct tty_struct *tty;
struct etrax_recv_buffer *buffer;
unsigned int length;
unsigned long flags;
int max_flip_size;
if (!info->first_recv_buffer)
return;
save_flags(flags);
cli();
if (!(tty = info->tty)) {
restore_flags(flags);
return;
}
length = tty->flip.count;
/* Don't flip more than the ldisc has room for.
* The return value from ldisc.receive_room(tty) - might not be up to
* date, the previous flip of up to TTY_FLIPBUF_SIZE might be on the
* processed and not accounted for yet.
* Since we use DMA, 1 SERIAL_DESCR_BUF_SIZE could be on the way.
* Lets buffer data here and let flow control take care of it.
* Since we normally flip large chunks, the ldisc don't react
* with throttle until too late if we flip to much.
*/
max_flip_size = tty->ldisc.receive_room(tty);
if (max_flip_size < 0)
max_flip_size = 0;
if (max_flip_size <= (TTY_FLIPBUF_SIZE + /* Maybe not accounted for */
length + info->recv_cnt + /* We have this queued */
2*SERIAL_DESCR_BUF_SIZE + /* This could be on the way */
TTY_THRESHOLD_THROTTLE)) { /* Some slack */
/* check TTY_THROTTLED first so it indicates our state */
if (!test_and_set_bit(TTY_THROTTLED, &tty->flags)) {
DFLOW(DEBUG_LOG(info->line,"flush_to_flip throttles room %lu\n", max_flip_size));
rs_throttle(tty);
}
#if 0
else if (max_flip_size <= (TTY_FLIPBUF_SIZE + /* Maybe not accounted for */
length + info->recv_cnt + /* We have this queued */
SERIAL_DESCR_BUF_SIZE + /* This could be on the way */
TTY_THRESHOLD_THROTTLE)) { /* Some slack */
DFLOW(DEBUG_LOG(info->line,"flush_to_flip throttles again! %lu\n", max_flip_size));
rs_throttle(tty);
}
#endif
}
if (max_flip_size > TTY_FLIPBUF_SIZE)
max_flip_size = TTY_FLIPBUF_SIZE;
while ((buffer = info->first_recv_buffer) && length < max_flip_size) {
unsigned int count = buffer->length;
if (length + count > max_flip_size)
count = max_flip_size - length;
memcpy(tty->flip.char_buf_ptr + length, buffer->buffer, count);
memset(tty->flip.flag_buf_ptr + length, TTY_NORMAL, count);
tty->flip.flag_buf_ptr[length] = buffer->error;
length += count;
info->recv_cnt -= count;
DFLIP(DEBUG_LOG(info->line,"flip: %i\n", length));
if (count == buffer->length) {
info->first_recv_buffer = buffer->next;
kfree(buffer);
} else {
buffer->length -= count;
memmove(buffer->buffer, buffer->buffer + count, buffer->length);
buffer->error = TTY_NORMAL;
}
}
if (!info->first_recv_buffer)
info->last_recv_buffer = NULL;
tty->flip.count = length;
DFLIP(if (tty->ldisc.chars_in_buffer(tty) > 3500) {
DEBUG_LOG(info->line, "ldisc %lu\n",
tty->ldisc.chars_in_buffer(tty));
DEBUG_LOG(info->line, "flip.count %lu\n",
tty->flip.count);
}
);
restore_flags(flags);
DFLIP(
if (1) {
DEBUG_LOG(info->line, "*** rxtot %i\n", info->icount.rx);
DEBUG_LOG(info->line, "ldisc %lu\n", tty->ldisc.chars_in_buffer(tty));
DEBUG_LOG(info->line, "room %lu\n", tty->ldisc.receive_room(tty));
}
);
/* this includes a check for low-latency */
tty_flip_buffer_push(tty);
}
static void check_flush_timeout(struct e100_serial *info)
{
/* Flip what we've got (if we can) */
flush_to_flip_buffer(info);
/* We might need to flip later, but not to fast
* since the system is busy processing input... */
if (info->first_recv_buffer)
START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
/* Force eop last, since data might have come while we're processing
* and if we started the slow timer above, we won't start a fast
* below.
*/
force_eop_if_needed(info);
}
#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
static void flush_timeout_function(unsigned long data)
{
struct e100_serial *info = (struct e100_serial *)data;
fast_timers[info->line].function = NULL;
serial_fast_timer_expired++;
TIMERD(DEBUG_LOG(info->line, "flush_timout %i ", info->line));
TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
check_flush_timeout(info);
}
#else
/* dma fifo/buffer timeout handler
forces an end-of-packet for the dma input channel if no chars
have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
*/
static struct timer_list flush_timer;
static void
timed_flush_handler(unsigned long ptr)
{
struct e100_serial *info;
int i;
#ifdef CONFIG_SVINTO_SIM
return;
#endif
for (i = 0; i < NR_PORTS; i++) {
info = rs_table + i;
if (info->uses_dma_in)
check_flush_timeout(info);
}
/* restart flush timer */
mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
}
#endif
#ifdef SERIAL_HANDLE_EARLY_ERRORS
/* If there is an error (ie break) when the DMA is running and
* there are no bytes in the fifo the DMA is stopped and we get no
* eop interrupt. Thus we have to monitor the first bytes on a DMA
* transfer, and if it is without error we can turn the serial
* interrupts off.
*/
/*
BREAK handling on ETRAX 100:
ETRAX will generate interrupt although there is no stop bit between the
characters.
Depending on how long the break sequence is, the end of the breaksequence
will look differently:
| indicates start/end of a character.
B= Break character (0x00) with framing error.
E= Error byte with parity error received after B characters.
F= "Faked" valid byte received immediately after B characters.
V= Valid byte
1.
B BL ___________________________ V
.._|__________|__________| |valid data |
Multiple frame errors with data == 0x00 (B),
the timing matches up "perfectly" so no extra ending char is detected.
The RXD pin is 1 in the last interrupt, in that case
we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
know if another byte will come and this really is case 2. below
(e.g F=0xFF or 0xFE)
If RXD pin is 0 we can expect another character (see 2. below).
2.
B B E or F__________________..__ V
.._|__________|__________|______ | |valid data
"valid" or
parity error
Multiple frame errors with data == 0x00 (B),
but the part of the break trigs is interpreted as a start bit (and possibly
some 0 bits followed by a number of 1 bits and a stop bit).
Depending on parity settings etc. this last character can be either
a fake "valid" char (F) or have a parity error (E).
If the character is valid it will be put in the buffer,
we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
will set the flags so the tty will handle it,
if it's an error byte it will not be put in the buffer
and we set info->errorcode = ERRCODE_INSERT_BREAK.
To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
of the last faulty char (B) and compares it with the current time:
If the time elapsed time is less then 2*char_time_usec we will assume
it's a faked F char and not a Valid char and set
info->errorcode = ERRCODE_SET_BREAK.
Flaws in the above solution:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
We use the timer to distinguish a F character from a V character,
if a V character is to close after the break we might make the wrong decision.
TODO: The break will be delayed until an F or V character is received.
*/
static
struct e100_serial * handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
{
unsigned long data_read;
struct tty_struct *tty = info->tty;
if (!tty) {
printk("!NO TTY!\n");
return info;
}
if (tty->flip.count >= TTY_FLIPBUF_SIZE - TTY_THRESHOLD_THROTTLE) {
/* check TTY_THROTTLED first so it indicates our state */
if (!test_and_set_bit(TTY_THROTTLED, &tty->flags)) {
DFLOW(DEBUG_LOG(info->line, "rs_throttle flip.count: %i\n", tty->flip.count));
rs_throttle(tty);
}
}
if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
DEBUG_LOG(info->line, "force FLIP! %i\n", tty->flip.count);
tty->flip.work.func((void *) tty);
if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
DEBUG_LOG(info->line, "FLIP FULL! %i\n", tty->flip.count);
return info; /* if TTY_DONT_FLIP is set */
}
}
/* Read data and status at the same time */
data_read = *((unsigned long *)&info->port[REG_DATA_STATUS32]);
more_data:
if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
}
DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
IO_MASK(R_SERIAL0_READ, par_err) |
IO_MASK(R_SERIAL0_READ, overrun) )) {
/* An error */
info->last_rx_active_usec = GET_JIFFIES_USEC();
info->last_rx_active = jiffies;
DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
DLOG_INT_TRIG(
if (!log_int_trig1_pos) {
log_int_trig1_pos = log_int_pos;
log_int(rdpc(), 0, 0);
}
);
if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
(data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
/* Most likely a break, but we get interrupts over and
* over again.
*/
if (!info->break_detected_cnt) {
DEBUG_LOG(info->line, "#BRK start\n", 0);
}
if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
/* The RX pin is high now, so the break
* must be over, but....
* we can't really know if we will get another
* last byte ending the break or not.
* And we don't know if the byte (if any) will
* have an error or look valid.
*/
DEBUG_LOG(info->line, "# BL BRK\n", 0);
info->errorcode = ERRCODE_INSERT_BREAK;
}
info->break_detected_cnt++;
} else {
/* The error does not look like a break, but could be
* the end of one
*/
if (info->break_detected_cnt) {
DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
info->errorcode = ERRCODE_INSERT_BREAK;
} else {
if (info->errorcode == ERRCODE_INSERT_BREAK) {
info->icount.brk++;
*tty->flip.char_buf_ptr = 0;
*tty->flip.flag_buf_ptr = TTY_BREAK;
tty->flip.flag_buf_ptr++;
tty->flip.char_buf_ptr++;
tty->flip.count++;
info->icount.rx++;
}
*tty->flip.char_buf_ptr = IO_EXTRACT(R_SERIAL0_READ, data_in, data_read);
if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
info->icount.parity++;
*tty->flip.flag_buf_ptr = TTY_PARITY;
} else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
info->icount.overrun++;
*tty->flip.flag_buf_ptr = TTY_OVERRUN;
} else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
info->icount.frame++;
*tty->flip.flag_buf_ptr = TTY_FRAME;
}
info->errorcode = 0;
}
info->break_detected_cnt = 0;
}
} else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
/* No error */
DLOG_INT_TRIG(
if (!log_int_trig1_pos) {
if (log_int_pos >= log_int_size) {
log_int_pos = 0;
}
log_int_trig0_pos = log_int_pos;
log_int(rdpc(), 0, 0);
}
);
*tty->flip.char_buf_ptr = IO_EXTRACT(R_SERIAL0_READ, data_in, data_read);
*tty->flip.flag_buf_ptr = 0;
} else {
DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
}
tty->flip.flag_buf_ptr++;
tty->flip.char_buf_ptr++;
tty->flip.count++;
info->icount.rx++;
data_read = *((unsigned long *)&info->port[REG_DATA_STATUS32]);
if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
goto more_data;
}
tty_flip_buffer_push(info->tty);
return info;
}
static struct e100_serial* handle_ser_rx_interrupt(struct e100_serial *info)
{
unsigned char rstat;
#ifdef SERIAL_DEBUG_INTR
printk("Interrupt from serport %d\n", i);
#endif
/* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
if (!info->uses_dma_in) {
return handle_ser_rx_interrupt_no_dma(info);
}
/* DMA is used */
rstat = info->port[REG_STATUS];
if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
}
if (rstat & SER_ERROR_MASK) {
unsigned char data;
info->last_rx_active_usec = GET_JIFFIES_USEC();
info->last_rx_active = jiffies;
/* If we got an error, we must reset it by reading the
* data_in field
*/
data = info->port[REG_DATA];
DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
/* Most likely a break, but we get interrupts over and
* over again.
*/
if (!info->break_detected_cnt) {
DEBUG_LOG(info->line, "#BRK start\n", 0);
}
if (rstat & SER_RXD_MASK) {
/* The RX pin is high now, so the break
* must be over, but....
* we can't really know if we will get another
* last byte ending the break or not.
* And we don't know if the byte (if any) will
* have an error or look valid.
*/
DEBUG_LOG(info->line, "# BL BRK\n", 0);
info->errorcode = ERRCODE_INSERT_BREAK;
}
info->break_detected_cnt++;
} else {
/* The error does not look like a break, but could be
* the end of one
*/
if (info->break_detected_cnt) {
DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
info->errorcode = ERRCODE_INSERT_BREAK;
} else {
if (info->errorcode == ERRCODE_INSERT_BREAK) {
info->icount.brk++;
add_char_and_flag(info, '\0', TTY_BREAK);
}
if (rstat & SER_PAR_ERR_MASK) {
info->icount.parity++;
add_char_and_flag(info, data, TTY_PARITY);
} else if (rstat & SER_OVERRUN_MASK) {
info->icount.overrun++;
add_char_and_flag(info, data, TTY_OVERRUN);
} else if (rstat & SER_FRAMING_ERR_MASK) {
info->icount.frame++;
add_char_and_flag(info, data, TTY_FRAME);
}