Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt

Qualcomm QUSB2 phy controller
=============================

QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.

Required properties:
 - compatible: compatible list, contains
	       "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
	       "qcom,qusb2-v2-phy" for QUSB2 V2 PHY.

 - reg: offset and length of the PHY register set.
 - #phy-cells: must be 0.

 - clocks: a list of phandles and clock-specifier pairs,
	   one for each entry in clock-names.
 - clock-names: must be "cfg_ahb" for phy config clock,
			"ref" for 19.2 MHz ref clk,
			"iface" for phy interface clock (Optional).

 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
 - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.

 - resets: Phandle to reset to phy block.

Optional properties:
 - nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim'
		tuning parameter value for qusb2 phy.

 - qcom,tcsr-syscon: Phandle to TCSR syscon register region.

Example:
	hsusb_phy: phy@7411000 {
		compatible = "qcom,msm8996-qusb2-phy";
		reg = <0x7411000 0x180>;
		#phy-cells = <0>;

		clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
			<&gcc GCC_RX1_USB2_CLKREF_CLK>,
		clock-names = "cfg_ahb", "ref";

		vdda-pll-supply = <&pm8994_l12>;
		vdda-phy-dpdm-supply = <&pm8994_l24>;

		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
		nvmem-cells = <&qusb2p_hstx_trim>;
        };