tag | db788cda1d3f358b86b90c974840a17f213c78e5 | |
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tagger | Simon Horman <horms@verge.net.au> | Fri Mar 14 09:31:18 2014 +0900 |
object | a51a9d67ba061c1263d078c27e8a3020d61fe236 |
Fourth Round of Renesas ARM Based SoC Clock Updates for v3.15 r8a7791 (R-Car M2) SoC * Correct SCIFA3-5 clocks
commit | a51a9d67ba061c1263d078c27e8a3020d61fe236 | [log] [tgz] |
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author | Geert Uytterhoeven <geert+renesas@linux-m68k.org> | Wed Mar 12 19:40:39 2014 +0100 |
committer | Simon Horman <horms+renesas@verge.net.au> | Thu Mar 13 10:37:14 2014 +0900 |
tree | c1c4823f05c2bdc1746cf447a7202eff15263cf6 | |
parent | d93023f81d2c79595e64e4f516f03af4e4c73c13 [diff] |
ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks The MSTP clocks for SCIFA3-5 are MSTP1106-1108, not MSTP1105-1107 Also reinsert them at the correct position to preserve sort order. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>