Documentation/devicetree/bindings/clock/fsl,plldig.yaml

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding

maintainers:
  - Wen He <wen.he_1@nxp.com>

description: |
  NXP LS1028A has a clock domain PXLCLK0 used for the Display output
  interface in the display core, as implemented in TSMC CLN28HPM PLL.
  which generate and offers pixel clocks to Display.

properties:
  compatible:
    const: fsl,ls1028a-plldig

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  '#clock-cells':
    const: 0

  fsl,vco-hz:
     description: Optional for VCO frequency of the PLL in Hertz.
        The VCO frequency of this PLL cannot be changed during runtime
        only at startup. Therefore, the output frequencies are very
        limited and might not even closely match the requested frequency.
        To work around this restriction the user may specify its own
        desired VCO frequency for the PLL.
     minimum: 650000000
     maximum: 1300000000
     default: 1188000000

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'

additionalProperties: false

examples:
  # Display PIXEL Clock node:
  - |
    dpclk: clock-display@f1f0000 {
        compatible = "fsl,ls1028a-plldig";
        reg = <0x0 0xf1f0000 0x0 0xffff>;
        #clock-cells = <0>;
        clocks = <&osc_27m>;
    };

...