)]}' { "commit": "b0bb1269b9788a35af68587505d8df90498df75f", "tree": "d9cc2ef42c93947c59638f412d479b0fd36f7e9b", "parents": [ "72cf0b07418a9c8349aa9137194b1ccba6e54a9d", "8fef9900d43feb9d5017c72840966733085e3e82" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun May 19 09:56:36 2019 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun May 19 09:56:36 2019 -0700" }, "message": "Merge tag \u0027riscv-for-linus-5.2-mw2\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux\n\nPull RISC-V updates from Palmer Dabbelt:\n \"This contains an assortment of RISC-V related patches that I\u0027d like to\n target for the 5.2 merge window. Most of the patches are cleanups, but\n there are a handful of user-visible changes:\n\n - The nosmp and nr_cpus command-line arguments are now supported,\n which work like normal.\n\n - The SBI console no longer installs itself as a preferred console,\n we rely on standard mechanisms (/chosen, command-line, hueristics)\n instead.\n\n - sfence_remove_sfence_vma{,_asid} now pass their arguments along to\n the SBI call.\n\n - Modules now support BUG().\n\n - A missing sfence.vma during boot has been added. This bug only\n manifests during boot.\n\n - The arch/riscv support for SiFive\u0027s L2 cache controller has been\n merged, which should un-block the EDAC framework work.\n\n I\u0027ve only tested this on QEMU again, as I didn\u0027t have time to get\n things running on the Unleashed. The latest master from this morning\n merges in cleanly and passes the tests as well\"\n\n* tag \u0027riscv-for-linus-5.2-mw2\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux: (31 commits)\n riscv: fix locking violation in page fault handler\n RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs\n RISC-V: Add DT documentation for SiFive L2 Cache Controller\n RISC-V: Avoid using invalid intermediate translations\n riscv: Support BUG() in kernel module\n riscv: Add the support for c.ebreak check in is_valid_bugaddr()\n riscv: support trap-based WARN()\n riscv: fix sbi_remote_sfence_vma{,_asid}.\n riscv: move switch_mm to its own file\n riscv: move flush_icache_{all,mm} to cacheflush.c\n tty: Don\u0027t force RISCV SBI console as preferred console\n RISC-V: Access CSRs using CSR numbers\n RISC-V: Add interrupt related SCAUSE defines in asm/csr.h\n RISC-V: Use tabs to align macro values in asm/csr.h\n RISC-V: Fix minor checkpatch issues.\n RISC-V: Support nr_cpus command line option.\n RISC-V: Implement nosmp commandline option.\n RISC-V: Add RISC-V specific arch_match_cpu_phys_id\n riscv: vdso: drop unnecessary cc-ldoption\n riscv: call pm_power_off from machine_halt / machine_power_off\n ...\n", "tree_diff": [] }