TI clock driver changes for 5.5

As the clock and reset handling is tightly coupled on the hardware level
on OMAP SoCs, we must ensure the events are sequenced properly. This
series makes sure that the clock side is behaving properly, and the
sequencing of the events is left for the bus driver (ti-sysc.)

The series also includes revamp of the TI divider clock implementation
to handle max divider values properly in cases where the max value is
not limited by the bitfield of the IO register but instead limited to
some arbitrary value. Previously this resulted in too high divider
values to be used in some cases causing HW malfunction.

Additionally, a couple of smaller changes needed by remoteproc support
are added; checking of the standby status and some missing clkctrl data
for omap5/dra7.
ARM: dts: omap3: fix DPLL4 M4 divider max value

The maximum divider value for DPLL4 M4 divider appears wrong. For most
OMAP3 family SoCs this is 16, but it is defined as 32, which is maybe
only valid for omap36xx. To avoid any overflows in trying to write this
register, set the max to 16 for all omap3 family, except omap36xx. For
omap36xx the maximum is set to 31, as it appears value 32 is not working
properly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Adam Ford <aford173@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
2 files changed