Samsung SoC clock drivers changes for 6.10
1. Allow choice of manual or firmware-driven control over PLLs, needed
to fully implement CPU clock controllers on Exynos850.
2. Correct PLL clock IDs on ExynosAutov9.
3. Google GS101:
- Propagate certain clock rates to allow setting proper SPI clock
rates.
- Add HSI0 and HSI2 clock controllers.
- Mark certain clocks critical.
4. Convert old S3C64xx clock controller bindings to DT schema.
clk: samsung: gs101: drop unused HSI2 clock parent data
Drop static const arrays with HSI2 clocks parent data which are not
referenced by any clock. This might cause -Werror=unused-const-variable
warnings.
Reported-by: Stephen Boyd <sboyd@kernel.org>
Closes: https://lore.kernel.org/all/8bf65df598680f0785c3d6db70acfb9a.sboyd@kernel.org/
Fixes: 093c290084a4 ("clk: samsung: gs101: add support for cmu_hsi2")
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240507055948.34554-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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