| /* |
| * Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x) |
| * |
| * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> |
| * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| #include "omap3-igep.dtsi" |
| #include "omap-gpmc-smsc911x.dtsi" |
| |
| / { |
| model = "IGEPv2 (TI OMAP AM/DM37x)"; |
| compatible = "isee,omap3-igep0020", "ti,omap3"; |
| |
| leds { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&leds_pins>; |
| compatible = "gpio-leds"; |
| |
| boot { |
| label = "omap3:green:boot"; |
| gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; |
| default-state = "on"; |
| }; |
| |
| user0 { |
| label = "omap3:red:user0"; |
| gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| user1 { |
| label = "omap3:red:user1"; |
| gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; |
| default-state = "off"; |
| }; |
| |
| user2 { |
| label = "omap3:green:user1"; |
| gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; |
| }; |
| }; |
| |
| /* HS USB Port 1 Power */ |
| hsusb1_power: hsusb1_power_reg { |
| compatible = "regulator-fixed"; |
| regulator-name = "hsusb1_vbus"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ |
| startup-delay-us = <70000>; |
| }; |
| |
| /* HS USB Host PHY on PORT 1 */ |
| hsusb1_phy: hsusb1_phy { |
| compatible = "usb-nop-xceiv"; |
| reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ |
| vcc-supply = <&hsusb1_power>; |
| }; |
| }; |
| |
| &omap3_pmx_core { |
| pinctrl-names = "default"; |
| pinctrl-0 = < |
| &tfp410_pins |
| &dss_pins |
| >; |
| |
| tfp410_pins: tfp410_dvi_pins { |
| pinctrl-single,pins = < |
| 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ |
| >; |
| }; |
| |
| dss_pins: pinmux_dss_dvi_pins { |
| pinctrl-single,pins = < |
| 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ |
| 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ |
| 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ |
| 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ |
| 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ |
| 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ |
| 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ |
| 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ |
| 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ |
| 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ |
| 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ |
| 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ |
| 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ |
| 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ |
| 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ |
| 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ |
| 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ |
| 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ |
| 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ |
| 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ |
| 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ |
| 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ |
| 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ |
| 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ |
| 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ |
| 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ |
| 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ |
| 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ |
| >; |
| }; |
| }; |
| |
| &omap3_pmx_core2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = < |
| &hsusbb1_pins |
| >; |
| |
| hsusbb1_pins: pinmux_hsusbb1_pins { |
| pinctrl-single,pins = < |
| OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ |
| OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ |
| OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ |
| OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ |
| OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ |
| OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ |
| OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ |
| OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ |
| OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ |
| OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ |
| OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ |
| OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ |
| >; |
| }; |
| |
| leds_pins: pinmux_leds_pins { |
| pinctrl-single,pins = < |
| OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ |
| OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ |
| OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ |
| >; |
| }; |
| }; |
| |
| &i2c3 { |
| clock-frequency = <100000>; |
| |
| /* |
| * Display monitor features are burnt in the EEPROM |
| * as EDID data. |
| */ |
| eeprom@50 { |
| compatible = "ti,eeprom"; |
| reg = <0x50>; |
| }; |
| }; |
| |
| &gpmc { |
| ranges = <0 0 0x00000000 0x20000000>, |
| <5 0 0x2c000000 0x01000000>; |
| |
| nand@0,0 { |
| linux,mtd-name= "micron,mt29c4g96maz"; |
| reg = <0 0 0>; |
| nand-bus-width = <16>; |
| ti,nand-ecc-opt = "bch8"; |
| |
| gpmc,sync-clk-ps = <0>; |
| gpmc,cs-on-ns = <0>; |
| gpmc,cs-rd-off-ns = <44>; |
| gpmc,cs-wr-off-ns = <44>; |
| gpmc,adv-on-ns = <6>; |
| gpmc,adv-rd-off-ns = <34>; |
| gpmc,adv-wr-off-ns = <44>; |
| gpmc,we-off-ns = <40>; |
| gpmc,oe-off-ns = <54>; |
| gpmc,access-ns = <64>; |
| gpmc,rd-cycle-ns = <82>; |
| gpmc,wr-cycle-ns = <82>; |
| gpmc,wr-access-ns = <40>; |
| gpmc,wr-data-mux-bus-ns = <0>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| partition@0 { |
| label = "SPL"; |
| reg = <0 0x100000>; |
| }; |
| partition@80000 { |
| label = "U-Boot"; |
| reg = <0x100000 0x180000>; |
| }; |
| partition@1c0000 { |
| label = "Environment"; |
| reg = <0x280000 0x100000>; |
| }; |
| partition@280000 { |
| label = "Kernel"; |
| reg = <0x380000 0x300000>; |
| }; |
| partition@780000 { |
| label = "Filesystem"; |
| reg = <0x680000 0x1f980000>; |
| }; |
| }; |
| |
| ethernet@gpmc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&smsc911x_pins>; |
| reg = <5 0 0xff>; |
| interrupt-parent = <&gpio6>; |
| interrupts = <16 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| }; |
| |
| &usbhshost { |
| port1-mode = "ehci-phy"; |
| }; |
| |
| &usbhsehci { |
| phys = <&hsusb1_phy>; |
| }; |
| |
| &vpll2 { |
| /* Needed for DSS */ |
| regulator-name = "vdds_dsi"; |
| }; |
