tag 54e2321ee9f3e573e440833b1a230de9a7c0cf8a
tagger Linus Walleij <linus.walleij@linaro.org> Mon May 25 09:27:53 2015 +0200
object 984cffdeaeb7ea5a21f49a89f638d84d62d08992

Pin control fixes for the v4.1 kernel cycle:

- IRQ trigger fix for the Intel Cherryview.
- GPIO-to-pin mapping fix for the Cygnus driver.
- GPIO-to-pin mapping fix for the Meson8b driver.

commit 984cffdeaeb7ea5a21f49a89f638d84d62d08992
author Carlo Caione <carlo@endlessm.com> Sun May 17 17:57:38 2015 +0200
committer Linus Walleij <linus.walleij@linaro.org> Tue May 19 11:40:52 2015 +0200
tree 1251eeeeed538d8ba92b9f2788be9fdf817f40b5
parent 75e9143927a893aebad18b79e1bbeff4892c0d35

pinctrl: Fix gpio/pin mapping for Meson8b

The num_pins field in the struct meson_domain_data must include also the
missing pins in the Meson8b SoC, otherwise the GPIO <-> pin mapping is
broken on this platform. Avoid also the dinamic allocation for GPIOs.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>