Pin control fixes for v5.18:

- Fix some register offsets on Intel Alderlake

- Fix the order the UFS and SDC pins on Qualcomm SM6350

- Fix a build error in Mediatek Moore.

- Fix a pin function table in the Sunplus SP7021.

- Fix some Kconfig and static keywords on the Samsung
  Tesla FSD SoC.

- Fix up the EOI function for edge triggered IRQs and keep
  the block clock enabled for level IRQs in the
  STM32 driver.

- Fix some bits and order in the Rockchip RK3308 driver.

- Handle the errorpath in the Pistachio driver probe()
pinctrl: pistachio: fix use of irq_of_parse_and_map()

The irq_of_parse_and_map() function returns 0 on failure, and does not
return an negative value.

Fixes: cefc03e5995e ("pinctrl: Add Pistachio SoC pin control driver")
Reported-by: Zeal Robot <>
Signed-off-by: Lv Ruyi <>
Signed-off-by: Linus Walleij <>
1 file changed