MMP3 QSEVEN: fix build error when CPUFREQ and DEVFREQ

   Ported BetaRC 6006-MMP3 QSEVEN: fix build error when CPUFREQ and DEVFREQ
    are disabled

Signed-off-by: Danfeng Hong <hongd@marvell.com>
(cherry picked from commit e22379893be749dc85ec0338988ff841e66a46fa)

Signed-off-by: Wen-chien Jesse Sung <jesse.sung@canonical.com>
diff --git a/arch/arm/mach-mmp/clock-mmp3.c b/arch/arm/mach-mmp/clock-mmp3.c
index d8f8911..ba56f99 100644
--- a/arch/arm/mach-mmp/clock-mmp3.c
+++ b/arch/arm/mach-mmp/clock-mmp3.c
@@ -1154,13 +1154,17 @@
 	__raw_writel(tmp, clk->clk_rst);\
 }
 
+#ifdef CONFIG_DDR_DEVFREQ
 struct pm_qos_request_list gc_qos_ddrfreq_min;
+#endif
 static bool gc_force_high_rate = false;
 static struct delayed_work gc_idle_work;
 static void gc_set_constraint(struct work_struct *work)
 {
        gc_force_high_rate = true;
+#ifdef CONFIG_DDR_DEVFREQ
        pm_qos_update_request(&gc_qos_ddrfreq_min, PM_QOS_DEFAULT_VALUE);
+#endif
 }
 
 static void gc_clk_init(struct clk *clk)
@@ -1179,8 +1183,10 @@
 */
 	INIT_DELAYED_WORK(&gc_idle_work, gc_set_constraint);
 	gc_force_high_rate = true;
+#ifdef CONFIG_DDR_DEVFREQ
 	pm_qos_add_request(&gc_qos_ddrfreq_min, PM_QOS_DDR_DEVFREQ_MIN,
-	PM_QOS_DEFAULT_VALUE);
+		PM_QOS_DEFAULT_VALUE);
+#endif
 }
 
 static int gc_clk_setrate(struct clk *clk, unsigned long rate)
@@ -1245,7 +1251,9 @@
 	 */
 
 	cancel_delayed_work_sync(&gc_idle_work);
+#ifdef CONFIG_DDR_DEVFREQ
 	pm_qos_update_request(&gc_qos_ddrfreq_min, DDR_CONSTRAINT_LVL1);
+#endif
 
 	if (gc_force_high_rate == true)
 		gc_clk_setrate(clk, 533333333);
diff --git a/drivers/video/pxa168fb.c b/drivers/video/pxa168fb.c
index e6e6dc1..253aca3 100644
--- a/drivers/video/pxa168fb.c
+++ b/drivers/video/pxa168fb.c
@@ -1168,7 +1168,9 @@
 static irqreturn_t pxa168fb_threaded_handle_irq(int irq, void *dev_id)
 {
 	if (atomic_read(&framedone)) {
+#ifdef CONFIG_DDR_DEVFREQ
 //		wakeup_ddr_fc_seq();	//paul tmp
+#endif
 		atomic_set(&framedone, 0);
 	}