| From 7e479fdcf0534f34e6035d8aa1ea67b08e41b734 Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Fri, 3 Mar 2017 14:18:16 +0100 |
| Subject: [PATCH 024/286] arm64: dts: r8a7795: Remove unit-addresses and regs |
| from integrated caches |
| |
| The Cortex-A57/A53 cache controllers are integrated controllers, and |
| thus the device nodes representing them should not have unit-addresses |
| or reg properties. |
| |
| Fixes: 6f7bf82cc912441f ("arm64: dts: r8a7795: Fix W=1 dtc warnings") |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit d165856de103a6d317a9c9a5782eacd5dc90a9dc) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++---- |
| 1 file changed, 2 insertions(+), 4 deletions(-) |
| |
| --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi |
| +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi |
| @@ -109,17 +109,15 @@ |
| enable-method = "psci"; |
| }; |
| |
| - L2_CA57: cache-controller@0 { |
| + L2_CA57: cache-controller-0 { |
| compatible = "cache"; |
| - reg = <0>; |
| power-domains = <&sysc R8A7795_PD_CA57_SCU>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| |
| - L2_CA53: cache-controller@100 { |
| + L2_CA53: cache-controller-1 { |
| compatible = "cache"; |
| - reg = <0x100>; |
| power-domains = <&sysc R8A7795_PD_CA53_SCU>; |
| cache-unified; |
| cache-level = <2>; |
